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2013 International Conference on Indium Phosphide and Related Materials (IPRM)最新文献

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High-speed directly modulated laser for applications beyond 100GbE 用于100GbE以上应用的高速直接调制激光器
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562613
W. Kobayashi, T. Fujisawa, Toshio Ito, T. Yamanaka, Y. Shibata, T. Tadokoro, H. Sanjoh
Recent results are reported for a 1.3-μm InGaAlAs directly modulated laser (DML) with a ridge waveguide structure. We realized a 3-dB-down electrical-to-optical (E/O) response of 34 GHz for a 150-μm DML. Clear eye openings were obtained at 43 Gb/s up to 60°C and at 50 Gb/s at 25°C.
报道了具有脊波导结构的1.3 μm InGaAlAs直接调制激光器(DML)的最新研究结果。我们在150 μm DML上实现了34 GHz的3db -down电光(E/O)响应。在60°C和25°C下,分别以43 Gb/s和50 Gb/s的速度获得清晰的眼开口。
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引用次数: 3
III–V MOS technology: From planar to 3D and 4D III-V MOS技术:从平面到3D和4D
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562562
P. Ye
Recently, III-V MOSFETs with high drain currents (Ids>1mA/μm) and high transconductances (gm>1mS/μm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of deep sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V MOS technology developed very recently. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec. The total drain current per pitch can be further enhanced by introducing 4D structures.
最近,由于对高k/III-V接口的更好理解和显著改进,已经在亚微米通道长度(Lch)下实现了高漏极电流(Ids>1mA/μm)和高跨导(gm>1mS/μm)的III-V mosfet。然而,要实现超过14nm技术节点的III-V场效应管,一个主要挑战是如何有效地控制短通道效应(SCE)。由于沟道材料具有较高的介电常数和较低的带隙,III-V型mosfet比其Si对应物更容易受到SCE的影响。因此,将三维(3D)结构引入到深度低于100nm的III-V场效应管的制造中是必要的。在这次演讲中,我们将回顾最近发展的III-V MOS技术的材料和器件方面。我们还将报告一些新的进展,通过演示20-80 nm通道长度的III-V栅极全方位纳米线mosfet, EOT=1.2nm,最低SS=63 mV/dec。通过引入4D结构,可以进一步提高每节距总漏极电流。
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引用次数: 0
Preparation of single-domain Si(100) surfaces with in situ control in CVD ambient CVD环境下原位控制单畴Si(100)表面的制备
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562580
S. Bruckner, O. Supplie, P. Kleinschmidt, A. Dobrich, H. Doscher, T. Hannappel
III-V films grown heteroepitaxially on Si(100) substrates by metal-organic chemical vapor deposition (MOCVD) are desired for the combination of optoelectronics with microelectronic devices. Difficulties regarding device quality are related to the formation of the crucial III-V/Si(100) interface, where single-layer steps on the substrate surface induce antiphase disorder in the epitaxial film. In principle, double-layer steps on the Si(100) substrate prevent the occurrence of antiphase disorder. While the preparation of silicon surfaces is well-established in UHV, preparation in H2 ambient differs considerably. Considered energetically least favorable on both the clean and the monohydride-terminated Si(100) surface, single domain surfaces with double layer steps in the unusual DA configuration were recently prepared in MOCVD ambient. The DA step formation on Si(100) with 2° offcut in CVD ambient is suggested to originate in vacancy generation and diffusion on the terraces accompanied by preferential annihilation at the step edges. Here, we investigate Si removal and vacancy formation on Si(100) substrates with large terraces under CVD preparation conditions. With in situ reflection anisotropy spectroscopy (RAS), we directly observe the domain formation in dependence of the preparation route. Oscillations in transient RA measurements indicate layer by layer Si removal during annealing in hydrogen. Based on scanning tunneling microscopy results, we conclude that vacancy island formation and anisotropic expansion preferentially in parallel to the dimer rows of the terraces explains the layer-by-layer Si removal process.
利用金属有机化学气相沉积(MOCVD)技术在Si(100)衬底上异质外延生长III-V薄膜是光电子与微电子器件结合的理想材料。器件质量方面的困难与关键的III-V/Si(100)界面的形成有关,其中衬底表面的单层台阶会导致外延膜中的反相紊乱。原则上,Si(100)衬底上的双层台阶可以防止反相无序的发生。虽然硅表面的制备在特高压环境下是成熟的,但在H2环境下的制备却有很大的不同。考虑到清洁和单氢端Si(100)表面在能量上最不利,最近在MOCVD环境下制备了具有双层台阶的异常DA结构的单畴表面。在CVD环境下,具有2°边切的Si(100)上的DA阶梯的形成是由台阶上的空位生成和扩散引起的,阶梯边缘有优先湮灭。在这里,我们研究了在CVD制备条件下具有大台阶的Si(100)衬底上Si的去除和空位的形成。利用原位反射各向异性光谱(RAS),我们直接观察到与制备路线相关的畴形成。瞬态RA测量的振荡表明在氢退火过程中硅的逐层去除。基于扫描隧道显微镜的结果,我们认为空位岛的形成和各向异性膨胀优先平行于梯田的二聚体行解释了硅的逐层去除过程。
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引用次数: 0
5 GHz low-power RTD-based amplifier MMIC with a high figure-of-merit of 24.5 dB/mW 5ghz低功率rtd放大器MMIC,具有24.5 dB/mW的高品质系数
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562608
Jongwon Lee, Jooseok Lee, Jaehong Park, Kyounghoon Yang
A low dc power RTD microwave amplifier utilizing a hybrid-coupled reflection-type topology is presented. The low-power microwave amplifier, which consists of a quadrature hybrid coupler and two RTDs, is implemented using an InP-based MMIC technology. The fabricated RTD amplifier shows low dc power consumption of 470 W with high gain of 11.5 dB at 5 GHz, resulting in high FOM of 24.5 dB/mW. The amplifier IC is the first demonstration of a low-power microwave amplifier based on the RTD device technology.
提出了一种采用混合耦合反射型拓扑结构的低直流功率RTD微波放大器。该低功率微波放大器由一个正交混合耦合器和两个rtd组成,采用基于inp的MMIC技术实现。所制备的RTD放大器在5 GHz时具有470w的低直流功耗和11.5 dB的高增益,从而获得24.5 dB/mW的高FOM。该放大器集成电路是基于RTD器件技术的低功率微波放大器的首次演示。
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引用次数: 5
Self-aligned quantum-dot growth for single-photon sources 单光子源的自对准量子点生长
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562566
U. W. Pohl, A. Strittmatter, J. Schulze, D. Quandt, T. Germann, W. Unrau, T. Heindel, O. Hitzemann, D. Bimberg, S. Reitzenstein
The buried oxide current-aperture in a pin diode-structure is used to create a strain field for the self-aligned nucleation of site-controlled single quantum dots. A single-photon source fabricated applying this approach shows spectrally very narrow emission lines (FWHM ≤ 25 μeV) and spectrally pure single-photon emission with a second-order autocorrelation g(2)(0) = 0.05.
利用引脚二极管结构中埋藏的氧化电流孔为位控单量子点的自对准成核提供了应变场。利用该方法制备的单光子源发射谱线非常窄(FWHM≤25 μeV),单光子发射谱线很纯,二阶自相关系数g(2)(0) = 0.05。
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引用次数: 1
Tunable InP photonic integrated circuit for millimeter wave generation 毫米波产生的可调谐InP光子集成电路
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562624
M. Lamponi, M. Chtioui, F. Lelarge, G. Kervella, E. Rouvalis, C. Renaud, M. Fice, G. Carpintero, F. van Dijk
We demonstrate a fully integrated tunable continuous-wave (CW) millimeter wave heterodyne synthesizer. DFB lasers, SOA amplifiers, passive waveguides, beam combiners, high speed photodetectors have been integrated on the same InP-based platform. Millimeter wave generation up to 110 GHz has been demonstrated.
我们展示了一个完全集成的可调谐连续波(CW)毫米波外差合成器。DFB激光器、SOA放大器、无源波导、光束合并器、高速光电探测器已经集成在同一个基于inp的平台上。高达110千兆赫的毫米波产生已被证明。
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引用次数: 1
New fabrication method of trapezoidal polarization converters for inp-based photonic integrated circuits 基于光子集成电路的梯形偏振变换器的新制造方法
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562622
D. Dzibrou, J. V. D. van der Tol, M. Smit
This paper presents a new way to make trapezoidal polarization converters. The fabrication process has four steps, two steps less than the standard fabrication. The fabricated converters have a 97.9% polarization conversion and loss below 0.5 dB at a wavelength of 1.55 μm.
提出了一种制作梯形偏振变换器的新方法。制造过程有四个步骤,比标准制造少两个步骤。在波长为1.55 μm时,转换器的极化转化率为97.9%,损耗小于0.5 dB。
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引用次数: 2
Ultrashort pulse generators using resonant tunneling diodes with improved power performance 采用谐振隧道二极管的超短脉冲发生器,提高了功率性能
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562645
D. Wu, Jie Pan, Katsutaro Mizumaki, M. Mori, K. Maezawa
RTD pulse generators were designed and fabricated for improved power performance. 10-ps class pulse width with higher peak power was demonstrated for the circuit having an exponentially tapered transmission line impedance converter.
为提高功率性能,设计制作了RTD脉冲发生器。采用指数锥形传输线阻抗变换器的电路演示了具有更高峰值功率的10ps级脉冲宽度。
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引用次数: 0
Simulation and fabrication of InGaAs planar Gunn diode on InP substrate InP衬底InGaAs平面Gunn二极管的模拟与制备
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562607
V. Papageorgiou, A. Khalid, Chong Li, D. Cumming
This paper describes the simulation and fabrication of the first planar Gunn diode based on InGaAs on InP substrate. Gunn devices were simulated using the Sentaurus Device software. The fabricated planar Gunn diodes are 1.3 μm long and 120 micron wide and the measured and simulated results are in excellent agreement.
本文介绍了在InP衬底上基于InGaAs的第一个平面Gunn二极管的仿真和制作。使用Sentaurus Device软件模拟了Gunn个设备。所制备的平面Gunn二极管长1.3 μm,宽120 μm,测量结果与模拟结果吻合良好。
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引用次数: 0
Impact of Al2O3 ALD temperature on Al2O3/GaSb metal-oxide-semiconductor interface properties Al2O3 ALD温度对Al2O3/GaSb金属-氧化物-半导体界面性能的影响
Pub Date : 2013-05-19 DOI: 10.1109/ICIPRM.2013.6562633
M. Yokoyama, Y. Asakura, H. Yokoyama, M. Takenaka, S. Takagi
We have investigated the impact of the Al2O3 atomiclayer-deposition (ALD) temperature on Al2O3/GaSb metal-oxidesemiconductor (MOS) interface properties. We have found that the GaSb MOS interfaces are severely degraded with increasing the ALD temperature. X-ray photoelectron spectroscopy (XPS) measurements clarified that the main cause of the interface deterioration is the reduction of Sb oxides from GaSb surfaces.
我们研究了Al2O3原子层沉积(ALD)温度对Al2O3/GaSb金属氧化物半导体(MOS)界面性能的影响。我们发现,随着ALD温度的升高,GaSb MOS接口严重退化。x射线光电子能谱(XPS)测量表明,界面恶化的主要原因是砷化镓表面的锑氧化物的还原。
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引用次数: 4
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2013 International Conference on Indium Phosphide and Related Materials (IPRM)
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