Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043364
D. Jurišić, G. Moschytz
One of the problems with on-chip active-RC filters is that in order to satisfy tight specifications accurately, they need to be fine-tuned. This becomes more difficult with increasing filter order. In this paper, we introduce a simplified tuning method which is obtained by a new structure consisting of a filter section of second- or third-order (Biquad or Bitriplet which is referred to as a ‘tuning block’), in cascade with a ladder-RLC filter (passive LC, or simulated-active RC). The cut-off frequency of the resulting filter can be simply tuned by adjusting one component of the tuning block. The new ladder tuning-block (LTB) is compared with two conventional structures, a cascade of Biquads and a single-ladder filter. Fine tuning these two structures is considerably more complicated. It is shown that beside the advantage of ease of tuning, the sensitivity to component tolerances of the new structure is lower than that of the two conventional ones, for the price of a slightly higher filter order.
{"title":"Ladder-Biquad filter partitioning for on-chip tuning","authors":"D. Jurišić, G. Moschytz","doi":"10.1109/ECCTD.2011.6043364","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043364","url":null,"abstract":"One of the problems with on-chip active-RC filters is that in order to satisfy tight specifications accurately, they need to be fine-tuned. This becomes more difficult with increasing filter order. In this paper, we introduce a simplified tuning method which is obtained by a new structure consisting of a filter section of second- or third-order (Biquad or Bitriplet which is referred to as a ‘tuning block’), in cascade with a ladder-RLC filter (passive LC, or simulated-active RC). The cut-off frequency of the resulting filter can be simply tuned by adjusting one component of the tuning block. The new ladder tuning-block (LTB) is compared with two conventional structures, a cascade of Biquads and a single-ladder filter. Fine tuning these two structures is considerably more complicated. It is shown that beside the advantage of ease of tuning, the sensitivity to component tolerances of the new structure is lower than that of the two conventional ones, for the price of a slightly higher filter order.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132303006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043638
F. Butti, P. Bruschi, M. Piotto
Very low frequency Gm-C filters are critical cells that should be carefully designed in order to avoid an excessive occupation of silicon area, especially when a high dynamic range is required. In this work we propose a routine, which exploits the MATLAB Optimization Toolbox in order to perform an optimum sizing of low frequency Gm-C integrators. The target is minimizing the integrator area, while satisfying design specifications such as unity gain frequency and dynamic range. Upper and lower bounds have been assigned to several design parameters to obtain solutions compatible with real processes. The interaction between noise and low frequency specifications has been investigated and their impact on the area occupation has been shown. The accuracy of the routine, configured with the parameters of a commercial process, has been shown using electrical simulations.
{"title":"An automated area optimization routine for the design of very low frequency Gm-C integrators","authors":"F. Butti, P. Bruschi, M. Piotto","doi":"10.1109/ECCTD.2011.6043638","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043638","url":null,"abstract":"Very low frequency Gm-C filters are critical cells that should be carefully designed in order to avoid an excessive occupation of silicon area, especially when a high dynamic range is required. In this work we propose a routine, which exploits the MATLAB Optimization Toolbox in order to perform an optimum sizing of low frequency Gm-C integrators. The target is minimizing the integrator area, while satisfying design specifications such as unity gain frequency and dynamic range. Upper and lower bounds have been assigned to several design parameters to obtain solutions compatible with real processes. The interaction between noise and low frequency specifications has been investigated and their impact on the area occupation has been shown. The accuracy of the routine, configured with the parameters of a commercial process, has been shown using electrical simulations.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133056689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043613
A. Axholt, H. Sjöland
A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm, including AC coupling capacitors. It was measured using an on chip 24 GHz differential LC VCO for input signal generation.
{"title":"A 2.25mW inductor-less 24 GHz CML frequency divider in 90nm CMOS","authors":"A. Axholt, H. Sjöland","doi":"10.1109/ECCTD.2011.6043613","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043613","url":null,"abstract":"A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm, including AC coupling capacitors. It was measured using an on chip 24 GHz differential LC VCO for input signal generation.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043378
S. Tsukiyama, M. Fukui
In the statistical static timing analysis (S-STA), the timing information, such as a gate delay, a signal arrival time, and a slack, is treated as a random variable, and the statistical maximum operation is an important basic operation. Since the maximum of two Gaussian random variables is not Gaussian, various techniques for representing a non-Gaussian distribution have been proposed. Among them, the Gaussian mixture model is distinguished from the others in that it can handle various correlations, non-Gaussian distributions, and slew distributions easily, which are important in S-STA. In this paper, we propose a new statistical maximum operation for Gaussian mixture models, which takes the cumulative distribution function curve into account, and show some experimental results to evaluate its performance.
{"title":"A new statistical maximum operation for Gaussian mixture models and its evaluations","authors":"S. Tsukiyama, M. Fukui","doi":"10.1109/ECCTD.2011.6043378","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043378","url":null,"abstract":"In the statistical static timing analysis (S-STA), the timing information, such as a gate delay, a signal arrival time, and a slack, is treated as a random variable, and the statistical maximum operation is an important basic operation. Since the maximum of two Gaussian random variables is not Gaussian, various techniques for representing a non-Gaussian distribution have been proposed. Among them, the Gaussian mixture model is distinguished from the others in that it can handle various correlations, non-Gaussian distributions, and slew distributions easily, which are important in S-STA. In this paper, we propose a new statistical maximum operation for Gaussian mixture models, which takes the cumulative distribution function curve into account, and show some experimental results to evaluate its performance.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043624
Yusuke Tsubaki, Y. Horio, K. Aihara
We propose a forced chaos generator with a CMOS variable active inductor circuit. Two values of the equivalent inductance of the active inductor in the proposed circuit are switched by an external periodic square-wave voltage, so that a stretching-and-folding mechanism of chaotic motion is realized. The chaotic dynamics are confirmed through SPICE simulations with TSMC 0.35 µm CMOS semiconductor process parameters. Moreover, we present bifurcation phenomena, which are generated when the amplitude and the period of the external signal are changed as bifurcation parameters. A prototype chip for the proposed circuit was designed and fabricated with TSMC 0.25 µm CMOS semiconductor process.
{"title":"Forced chaos generator with switched CMOS active inductance","authors":"Yusuke Tsubaki, Y. Horio, K. Aihara","doi":"10.1109/ECCTD.2011.6043624","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043624","url":null,"abstract":"We propose a forced chaos generator with a CMOS variable active inductor circuit. Two values of the equivalent inductance of the active inductor in the proposed circuit are switched by an external periodic square-wave voltage, so that a stretching-and-folding mechanism of chaotic motion is realized. The chaotic dynamics are confirmed through SPICE simulations with TSMC 0.35 µm CMOS semiconductor process parameters. Moreover, we present bifurcation phenomena, which are generated when the amplitude and the period of the external signal are changed as bifurcation parameters. A prototype chip for the proposed circuit was designed and fabricated with TSMC 0.25 µm CMOS semiconductor process.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114472840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043642
P. Pouyan, E. Hertz, P. Nilsson
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized and implemented on an FPGA and as an ASIC. The results of such implementations are compared with metrics such as performance and area. The performance in the parabolic architecture is shown to exceed the CORDIC architecture by a factor 4.2, in a 65 nm Standard-VT ASIC implementation.
{"title":"A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm","authors":"P. Pouyan, E. Hertz, P. Nilsson","doi":"10.1109/ECCTD.2011.6043642","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043642","url":null,"abstract":"High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized and implemented on an FPGA and as an ASIC. The results of such implementations are compared with metrics such as performance and area. The performance in the parabolic architecture is shown to exceed the CORDIC architecture by a factor 4.2, in a 65 nm Standard-VT ASIC implementation.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114659305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043346
P. Kmon, P. Grybos, R. Szczygiel, M. Zoladz
This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut off frequencies and the voltage gain are controlled thanks to the on-chip register. User is able to change the low cut off frequency in the 60 mHz – 100 Hz range in each channel independently while the high cut off frequency and the voltage gain can be set to 4.7 kHz / 12 kHz and 139 V/V / 1100 V/V respectively. The input referred noise depends on the bandwidth of the recording channel and is equal to 3.7 µV (100 Hz – 12 kHz) or to 7.6 µV (3 Hz – 12 kHz). This paper deals with problems that are present in a multichannel integrated recording electronics for neurobiology experiments such as: ability to record input signals in the frequency range below a single Hz, and the spread of the cut off frequencies from channel to channel in such systems. Up to our knowledge the solution presented in this paper is the first one reporting the multichannel IC that is able both to record extremely low frequency signals in each channel with a small spread of this parameter from channel to channel.
{"title":"Tuning the low cut-off frequency in multichannel neural recording amplifiers by the on-chip correction DACs","authors":"P. Kmon, P. Grybos, R. Szczygiel, M. Zoladz","doi":"10.1109/ECCTD.2011.6043346","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043346","url":null,"abstract":"This paper presents a design and measurements of multichannel integrated circuits dedicated to recording of neurobiological signals. 64 recording channels have been implemented in a single chip using a commercially available CMOS 180 nm process. A single recording amplifier consumes only 25 µW from 1.8 V supply and occupies 0.13 mm2 of the silicon area. Its main parameters such as the low/high cut off frequencies and the voltage gain are controlled thanks to the on-chip register. User is able to change the low cut off frequency in the 60 mHz – 100 Hz range in each channel independently while the high cut off frequency and the voltage gain can be set to 4.7 kHz / 12 kHz and 139 V/V / 1100 V/V respectively. The input referred noise depends on the bandwidth of the recording channel and is equal to 3.7 µV (100 Hz – 12 kHz) or to 7.6 µV (3 Hz – 12 kHz). This paper deals with problems that are present in a multichannel integrated recording electronics for neurobiology experiments such as: ability to record input signals in the frequency range below a single Hz, and the spread of the cut off frequencies from channel to channel in such systems. Up to our knowledge the solution presented in this paper is the first one reporting the multichannel IC that is able both to record extremely low frequency signals in each channel with a small spread of this parameter from channel to channel.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134507988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043641
P. Nilsson, Syed Nadeemuddin
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs with an arbitrary number of stages. Here, a six stage CORDIC is used as an example to show the methodology. The paper shows that the complexity can be decreased by 29 % and the dynamic power consumption can be reduced by 59 %.
{"title":"Power reductions in unrolled CORDIC architectures","authors":"P. Nilsson, Syed Nadeemuddin","doi":"10.1109/ECCTD.2011.6043641","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043641","url":null,"abstract":"This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs with an arbitrary number of stages. Here, a six stage CORDIC is used as an example to show the methodology. The paper shows that the complexity can be decreased by 29 % and the dynamic power consumption can be reduced by 59 %.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133619448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043313
P. Payandehnia, B. Forouzandeh, A. Abbasfar, S. Sheikhaei, K. Nanbakhsh
This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output driver for a wireline transmitter is designed in a 90nm CMOS technology. To model nonidealities of the active-inductor that affects the transmitter performance, an accurate large-signal, wide-band characterization technique, based on Least Square Estimation is described. Amplification of high frequency components of 10 Gb/s and 12.5 Gb/s transmitted signals over two kinds of NELCO channels using active inductors in the transmitter side, improves SNDR in the receiver side by 3 dB, as compared to the case with no inductor peaking, for the same power consumption. The transmitter circuit consumes 8.4 mW from a 1.2V power supply.
{"title":"A 12.5Gb/s active-inductor based transmitter for I/O applications","authors":"P. Payandehnia, B. Forouzandeh, A. Abbasfar, S. Sheikhaei, K. Nanbakhsh","doi":"10.1109/ECCTD.2011.6043313","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043313","url":null,"abstract":"This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output driver for a wireline transmitter is designed in a 90nm CMOS technology. To model nonidealities of the active-inductor that affects the transmitter performance, an accurate large-signal, wide-band characterization technique, based on Least Square Estimation is described. Amplification of high frequency components of 10 Gb/s and 12.5 Gb/s transmitted signals over two kinds of NELCO channels using active inductors in the transmitter side, improves SNDR in the receiver side by 3 dB, as compared to the case with no inductor peaking, for the same power consumption. The transmitter circuit consumes 8.4 mW from a 1.2V power supply.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043372
J. Wellmann, W. Mathis, M. Kahmann
In this paper, the use of the SB-ZePoC Coding-Scheme for a high precision AC Power-Standard (TET-Watt) is proposed. The use of SB-ZePoC allows a novel approach to binary switched precision-sources, as the switching-rate is low compared to sigma-delta modulation. The structure of the system allows to reference the output amplitude directly to a DC-voltage-reference or switching a binary source directly. To reduce HF-switching noise, a feed-forward compensation-circuit is implemented. This reduces the demands to the passive output-filtering.
{"title":"An AC Power-Standard using ZePoC-Coding and feed-forward HF-compensation","authors":"J. Wellmann, W. Mathis, M. Kahmann","doi":"10.1109/ECCTD.2011.6043372","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043372","url":null,"abstract":"In this paper, the use of the SB-ZePoC Coding-Scheme for a high precision AC Power-Standard (TET-Watt) is proposed. The use of SB-ZePoC allows a novel approach to binary switched precision-sources, as the switching-rate is low compared to sigma-delta modulation. The structure of the system allows to reference the output amplitude directly to a DC-voltage-reference or switching a binary source directly. To reduce HF-switching noise, a feed-forward compensation-circuit is implemented. This reduces the demands to the passive output-filtering.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"515 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132719581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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