Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043406
Xiaoyan Gui, Michael M. Green
The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated through Jazz Semiconductor 0.18-µm CMOS process.
{"title":"Nonlinearities in frequency dividers","authors":"Xiaoyan Gui, Michael M. Green","doi":"10.1109/ECCTD.2011.6043406","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043406","url":null,"abstract":"The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated through Jazz Semiconductor 0.18-µm CMOS process.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128106342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043815
M. H. Amin, M. B. Abdelhalim, H. Amer
Delta-Sigma analog to digital converters are vital components for mixed-signal systems. So, testing this type of converters is extremely important. This paper studies the low-cost testing of first-order and second-order delta-sigma ADCs. Moreover; only catastrophic faults are considered such as open/short passive components and stuck-at faults in digital components. It is proven that the minimal test set consists of only two values that detect all faults in the assumed fault set. The effect of using different types of counters in the digital subcircuit is investigated and it is found that the two-value test set still detects all faults. Finally, the effect of passive component tolerances is analyzed. All the results are analytically proven and verified by simulations.
{"title":"Testing of first and second order delta-sigma converters for catastrophic faults","authors":"M. H. Amin, M. B. Abdelhalim, H. Amer","doi":"10.1109/ECCTD.2011.6043815","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043815","url":null,"abstract":"Delta-Sigma analog to digital converters are vital components for mixed-signal systems. So, testing this type of converters is extremely important. This paper studies the low-cost testing of first-order and second-order delta-sigma ADCs. Moreover; only catastrophic faults are considered such as open/short passive components and stuck-at faults in digital components. It is proven that the minimal test set consists of only two values that detect all faults in the assumed fault set. The effect of using different types of counters in the digital subcircuit is investigated and it is found that the two-value test set still detects all faults. Finally, the effect of passive component tolerances is analyzed. All the results are analytically proven and verified by simulations.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"469 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123056792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043594
Dai Zhang, C. Svensson, A. Alvandpour
Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.
{"title":"Power consumption bounds for SAR ADCs","authors":"Dai Zhang, C. Svensson, A. Alvandpour","doi":"10.1109/ECCTD.2011.6043594","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043594","url":null,"abstract":"Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043853
L. Mandache, D. Topan, M. Iordache, L. Dumitriu, I. Sirbu
The paper proposes effective solutions to include nonlinear inductors with soft ferromagnetic core in the time-domain circuit analyses. Three inductor models are developed, tested and compared. They are conceived for different degrees of accuracy related to the real devices. The models are robust and reliable due to the modeling concept that avoids numerical instabilities. An enhanced inductor model can serve to numerical analyses aiming the optimization of some constructive parameters (as the airgap length or number of turns). A SPICE implementation was performed and exemplified for different operation conditions.
{"title":"On the time-domain analysis of analog circuits containing nonlinear inductors","authors":"L. Mandache, D. Topan, M. Iordache, L. Dumitriu, I. Sirbu","doi":"10.1109/ECCTD.2011.6043853","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043853","url":null,"abstract":"The paper proposes effective solutions to include nonlinear inductors with soft ferromagnetic core in the time-domain circuit analyses. Three inductor models are developed, tested and compared. They are conceived for different degrees of accuracy related to the real devices. The models are robust and reliable due to the modeling concept that avoids numerical instabilities. An enhanced inductor model can serve to numerical analyses aiming the optimization of some constructive parameters (as the airgap length or number of turns). A SPICE implementation was performed and exemplified for different operation conditions.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126303343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043403
Elio Consoli, G. Giustolisi, G. Palumbo
In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.
{"title":"An ultra-compact MOS model in nanometer technologies","authors":"Elio Consoli, G. Giustolisi, G. Palumbo","doi":"10.1109/ECCTD.2011.6043403","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043403","url":null,"abstract":"In this paper, an ultra-compact model for nanometer MOS transistors is proposed. Starting from modified and more accurate versions of classical compact models, all the main physical effects that are predominant in nanometer technologies are included in an extremely simple way. Model effectiveness is verified through simulations in a 65-nm CMOS technology.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043300
A. Eghbali, H. Johansson
This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in all branches of the Farrow structure. The second case uses linear-phase FIR filters in every second branch. These branches have milder restrictions on the approximation error. Therefore, even with a reduced order, for these linear-phase FIR filters, the approximation error is not affected. However, the arithmetic complexity, in terms of the number of distinct multiplications, is reduced by an average of 30%. Design examples illustrate the method.
{"title":"Complexity reduction in low-delay farrow-structure-based variable fractional delay FIR filters utilizing linear-phase subfilters","authors":"A. Eghbali, H. Johansson","doi":"10.1109/ECCTD.2011.6043300","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043300","url":null,"abstract":"This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in all branches of the Farrow structure. The second case uses linear-phase FIR filters in every second branch. These branches have milder restrictions on the approximation error. Therefore, even with a reduced order, for these linear-phase FIR filters, the approximation error is not affected. However, the arithmetic complexity, in terms of the number of distinct multiplications, is reduced by an average of 30%. Design examples illustrate the method.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043311
J. M. Carrillo, M. A. Domínguez, J. F. Duque-Carrillo, G. Torelli
An OTA-C filter implementation suited to low-voltage operation is presented. An operational transconductance amplifier (OTA) based on a bulk-driven input stage with enhanced DC gain and bandwidth was designed and included in a 1.2-V tunable fully differential second-order OTA-C lowpass filter. Experimental results, obtained in standard 0.35-µm CMOS technology, showed a dynamic range around 70 dB with a total power consumption of 382 µW for a filter cutoff frequency of 3 MHz.
{"title":"1.2-V fully differential OTA-C lowpass filter based on bulk-driven MOS transistors","authors":"J. M. Carrillo, M. A. Domínguez, J. F. Duque-Carrillo, G. Torelli","doi":"10.1109/ECCTD.2011.6043311","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043311","url":null,"abstract":"An OTA-C filter implementation suited to low-voltage operation is presented. An operational transconductance amplifier (OTA) based on a bulk-driven input stage with enhanced DC gain and bandwidth was designed and included in a 1.2-V tunable fully differential second-order OTA-C lowpass filter. Experimental results, obtained in standard 0.35-µm CMOS technology, showed a dynamic range around 70 dB with a total power consumption of 382 µW for a filter cutoff frequency of 3 MHz.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043393
D. Biolek, J. Bajer, V. Biolková, Z. Kolka
A method of analogue emulation of the memristor with its prescribed charge (qM) - flux (ϕM) constitutive relation is presented. The memristor is emulated via a resistor with nonlinear current (iR) - voltage (vR) relationship, and a mutator. The purpose of the mutator is to provide a similarity transformation of the current-voltage characteristic of the resistor into the constitutive relation of the memristor according to the equations qM=kyiR, ϕM =kxvR, or ϕM=kyiR, qM=kxvR, where kx, ky are real numbers fulfilling the condition kxky>0. It is shown that there are eight versions of these mutators. One of them is selected for experimental verification.
提出了一种具有规定电荷(qM) -磁通(ϕM)本构关系的忆阻器的模拟仿真方法。该忆阻器是通过一个具有非线性电流(iR) -电压(vR)关系的电阻器和一个突变器来仿真的。变换器的目的是根据公式qM=kyiR, m =kxvR，或m =kyiR, qM=kxvR，其中kx, ky为满足条件kxky>0的实数，将电阻器的电流-电压特性相似地转换为忆阻器的本构关系。结果表明，这些突变体有8个版本。选取其中一个进行实验验证。
{"title":"Mutators for transforming nonlinear resistor into memristor","authors":"D. Biolek, J. Bajer, V. Biolková, Z. Kolka","doi":"10.1109/ECCTD.2011.6043393","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043393","url":null,"abstract":"A method of analogue emulation of the memristor with its prescribed charge (q<inf>M</inf>) - flux (ϕ<inf>M</inf>) constitutive relation is presented. The memristor is emulated via a resistor with nonlinear current (i<inf>R</inf>) - voltage (v<inf>R</inf>) relationship, and a mutator. The purpose of the mutator is to provide a similarity transformation of the current-voltage characteristic of the resistor into the constitutive relation of the memristor according to the equations q<inf>M</inf>=k<inf>y</inf>i<inf>R</inf>, ϕ<inf>M</inf> =k<inf>x</inf>v<inf>R</inf>, or ϕ<inf>M</inf>=k<inf>y</inf>i<inf>R</inf>, q<inf>M</inf>=k<inf>x</inf>v<inf>R</inf>, where k<inf>x</inf>, k<inf>y</inf> are real numbers fulfilling the condition k<inf>x</inf>k<inf>y</inf>>0. It is shown that there are eight versions of these mutators. One of them is selected for experimental verification.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134584008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043401
Elio Consoli, G. Giustolisi, G. Palumbo
In this paper, an ultra-compact I–V nanometer MOS model, suitable for the analysis of digital circuits, is first proposed. All the main physical effects are included through nine parameters and the model is shown to allow an accurate and quick estimation of DC transfer curves or SRAM noise margins.
{"title":"Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model","authors":"Elio Consoli, G. Giustolisi, G. Palumbo","doi":"10.1109/ECCTD.2011.6043401","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043401","url":null,"abstract":"In this paper, an ultra-compact I–V nanometer MOS model, suitable for the analysis of digital circuits, is first proposed. All the main physical effects are included through nine parameters and the model is shown to allow an accurate and quick estimation of DC transfer curves or SRAM noise margins.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"677 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134501625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ECCTD.2011.6043329
P. Maffezzoni, D. D’Amore, M. Santomauro
This paper describes an original experimental procedure to extract the oscillator's phase sensitivity to injected noise perturbations. The proposed method relies on measuring the width of the locking ranges over which the oscillator's response synchronizes with an injected small-amplitude signal. The extraction procedure is applied to a relaxation oscillator which exhibits a strongly nonlinear behavior.
{"title":"Extracting oscillators phase-sensitivity to noise perturbations","authors":"P. Maffezzoni, D. D’Amore, M. Santomauro","doi":"10.1109/ECCTD.2011.6043329","DOIUrl":"https://doi.org/10.1109/ECCTD.2011.6043329","url":null,"abstract":"This paper describes an original experimental procedure to extract the oscillator's phase sensitivity to injected noise perturbations. The proposed method relies on measuring the width of the locking ranges over which the oscillator's response synchronizes with an injected small-amplitude signal. The extraction procedure is applied to a relaxation oscillator which exhibits a strongly nonlinear behavior.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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