Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523645
R. Todani, A. K. Mal
Telescopic amplifiers are often preferred for their large DC gain, low power dissipation and low flicker noise. On the other side, they suffer from serious problems like poor input common mode range and output swing. In this work, a simple technique to extract improved common mode range from telescopic structure is presented. To achieve this, two telescopic amplifiers using complementary differential pairs are utilized. The proposed design incorporates a digital switching technique which allows switching between high performance and low power modes. Low power mode allows reduction in power dissipation with compromise on elevated performance parameter. The entire design is verified using UMC 180 nm CMOS technology and the simulation results are presented.
{"title":"A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range","authors":"R. Todani, A. K. Mal","doi":"10.1109/ISQED.2013.6523645","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523645","url":null,"abstract":"Telescopic amplifiers are often preferred for their large DC gain, low power dissipation and low flicker noise. On the other side, they suffer from serious problems like poor input common mode range and output swing. In this work, a simple technique to extract improved common mode range from telescopic structure is presented. To achieve this, two telescopic amplifiers using complementary differential pairs are utilized. The proposed design incorporates a digital switching technique which allows switching between high performance and low power modes. Low power mode allows reduction in power dissipation with compromise on elevated performance parameter. The entire design is verified using UMC 180 nm CMOS technology and the simulation results are presented.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"654 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523646
K. Kawakami, T. Shiro, Hironobu Yamasaki, K. Yoda, Hiroaki Fujimoto, K. Kawasaki, Yasuhiro Watanabe
We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.
{"title":"Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology","authors":"K. Kawakami, T. Shiro, Hironobu Yamasaki, K. Yoda, Hiroaki Fujimoto, K. Kawasaki, Yasuhiro Watanabe","doi":"10.1109/ISQED.2013.6523646","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523646","url":null,"abstract":"We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523639
Bahram N. Uchevler, K. Svarstad, J. Kuper, Christiaan Baaij
With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.
{"title":"System-level modelling of dynamic reconfigurable designs using functional programming abstractions","authors":"Bahram N. Uchevler, K. Svarstad, J. Kuper, Christiaan Baaij","doi":"10.1109/ISQED.2013.6523639","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523639","url":null,"abstract":"With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133178950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523687
S. Nishizawa, T. Ishihara, H. Onodera
The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.
{"title":"Analysis and comparison of XOR cell structures for low voltage circuit design","authors":"S. Nishizawa, T. Ishihara, H. Onodera","doi":"10.1109/ISQED.2013.6523687","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523687","url":null,"abstract":"The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"553 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523658
Yuko Hara-Azumi, H. Tomiyama
Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. Most literature on system-level design techniques has been conventionally tackling this issue by spatial and/or temporal modular redundancy, whose cost in circuit area and performance is large. This paper proposes a soft error-aware scheduling method in high-level synthesis (HLS), which does not rely on such expensive, conventional techniques. The reliability of the datapath circuit is determined not only by that of hardware resources to which operations and values are assigned, but also that of their active time (i.e., time during which operational results should be correct). By considering both of these factors, our proposed method schedules operations so that the reliability of HLS-generated datapath circuits can be maximized under designer-given area/latency constraints. Experimental results demonstrate the effectiveness of our method over existing methods, especially for strict area/latency constraints.
{"title":"Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation","authors":"Yuko Hara-Azumi, H. Tomiyama","doi":"10.1109/ISQED.2013.6523658","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523658","url":null,"abstract":"Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. Most literature on system-level design techniques has been conventionally tackling this issue by spatial and/or temporal modular redundancy, whose cost in circuit area and performance is large. This paper proposes a soft error-aware scheduling method in high-level synthesis (HLS), which does not rely on such expensive, conventional techniques. The reliability of the datapath circuit is determined not only by that of hardware resources to which operations and values are assigned, but also that of their active time (i.e., time during which operational results should be correct). By considering both of these factors, our proposed method schedules operations so that the reliability of HLS-generated datapath circuits can be maximized under designer-given area/latency constraints. Experimental results demonstrate the effectiveness of our method over existing methods, especially for strict area/latency constraints.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523609
M. Sharad, Deliang Fan, K. Roy
CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid analog processing units that are compact as well as low power. In this work we present a mixed-mode signal processing scheme employing “domain wall neurons” that involves energy efficient analog-mode computation upon digital data. Simulation results for 8-bit, 16-tap FIR filter show that such a design can achieve 10x lower power consumption and 16x lower area as compared to an optimized digital CMOS design at the same technology node. In such a design area saving can be traded off for enhanced power savings, depending upon the target application.
{"title":"Low power and compact mixed-mode signal processing hardware using spin-neurons","authors":"M. Sharad, Deliang Fan, K. Roy","doi":"10.1109/ISQED.2013.6523609","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523609","url":null,"abstract":"CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid analog processing units that are compact as well as low power. In this work we present a mixed-mode signal processing scheme employing “domain wall neurons” that involves energy efficient analog-mode computation upon digital data. Simulation results for 8-bit, 16-tap FIR filter show that such a design can achieve 10x lower power consumption and 16x lower area as compared to an optimized digital CMOS design at the same technology node. In such a design area saving can be traded off for enhanced power savings, depending upon the target application.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121197288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523667
Zihao Chen, Hailong Yao, Yici Cai
In triple patterning lithography (TPL), balanced feature density on each layout mask helps facilitate the following OPC process. This paper presents the first spacing uniformity-aware layout decomposition method, called SUALD, which formulates the density optimization problem in TPL based on the spacings between locally adjacent features on each colored layout mask, and hence enhances the patterning quality. Based on the new density formulation, a spacing uniformity graph is built using the Voronoi diagram. An effective heuristic triple partitioning algorithm is also proposed for TPL layout decomposition. Experimental results are very promising and show that SUALD obtains 69% and 40% improvements in average in the presented density metrics over an integer linear programming method without density control.
{"title":"SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography","authors":"Zihao Chen, Hailong Yao, Yici Cai","doi":"10.1109/ISQED.2013.6523667","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523667","url":null,"abstract":"In triple patterning lithography (TPL), balanced feature density on each layout mask helps facilitate the following OPC process. This paper presents the first spacing uniformity-aware layout decomposition method, called SUALD, which formulates the density optimization problem in TPL based on the spacings between locally adjacent features on each colored layout mask, and hence enhances the patterning quality. Based on the new density formulation, a spacing uniformity graph is built using the Voronoi diagram. An effective heuristic triple partitioning algorithm is also proposed for TPL layout decomposition. Experimental results are very promising and show that SUALD obtains 69% and 40% improvements in average in the presented density metrics over an integer linear programming method without density control.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523589
Yinhe Han, Song Jin, Jibing Qiu, Q. Xu, Xiaowei Li
Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging. The chip-level leakage changes under a set of measurement vectors are firstly formulated as an equation set. Solving this equation set can obtain leakage changes in the gates along the critical path. Then, we predict delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase. Our scheme is immune to the runtime noise and accommodates process variation by increasing measurement time overhead. Experimental results demonstrate that our scheme can effectively predict NBTI-induced circuit aging with acceptable accuracy loss.
{"title":"On predicting NBTI-induced circuit aging by isolating leakage change","authors":"Yinhe Han, Song Jin, Jibing Qiu, Q. Xu, Xiaowei Li","doi":"10.1109/ISQED.2013.6523589","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523589","url":null,"abstract":"Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging. The chip-level leakage changes under a set of measurement vectors are firstly formulated as an equation set. Solving this equation set can obtain leakage changes in the gates along the critical path. Then, we predict delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase. Our scheme is immune to the runtime noise and accommodates process variation by increasing measurement time overhead. Experimental results demonstrate that our scheme can effectively predict NBTI-induced circuit aging with acceptable accuracy loss.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523637
Jordan Bisasky, H. Homayoun, F. Yazdani, T. Mohsenin
This paper presents a programmable many-core platform containing 64 cores routed in a hierarchical network for biomedical signal processing applications. Individual core processors are based on a RISC architecture with DSP enhancement blocks. Given the number of conditional program loops in DSP applications such as FFT, additional hardware blocks are added that operate in parallel to each core processor. The two blocks calculate the FFT input addresses and determine if a conditional loop is necessary. Performing these operations in parallel to the main processor greatly reduces the time to completion for a DSP application. Each processor is implemented in 65 nm CMOS using standard cell libraries. The 64-core platform occupies 19.51 mm2 and runs at 1.18 GHz at 1 V. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis algorithm utilizes 60 processors and takes 890 ns to execute. Spectral doppler utilizes 29 processors and takes 715 ns to run.
{"title":"A 64-core platform for biomedical signal processing","authors":"Jordan Bisasky, H. Homayoun, F. Yazdani, T. Mohsenin","doi":"10.1109/ISQED.2013.6523637","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523637","url":null,"abstract":"This paper presents a programmable many-core platform containing 64 cores routed in a hierarchical network for biomedical signal processing applications. Individual core processors are based on a RISC architecture with DSP enhancement blocks. Given the number of conditional program loops in DSP applications such as FFT, additional hardware blocks are added that operate in parallel to each core processor. The two blocks calculate the FFT input addresses and determine if a conditional loop is necessary. Performing these operations in parallel to the main processor greatly reduces the time to completion for a DSP application. Each processor is implemented in 65 nm CMOS using standard cell libraries. The 64-core platform occupies 19.51 mm2 and runs at 1.18 GHz at 1 V. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis algorithm utilizes 60 processors and takes 890 ns to execute. Spectral doppler utilizes 29 processors and takes 715 ns to run.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523686
N. Testi, Yang Xu
Energy efficient and low area temperature sensors are critical for constantly monitoring the silicon temperature in high density integrated circuits. In this paper, a 0.2nJ/sample ring oscillator based temperature sensor is designed and fabricated in TSMC 65nm CMOS technology. The sensor achieves a maximum inaccuracy of ±3°C after 2-point calibration and a resolution of 0.3°C. Furthermore, a model is proposed to accurately predict the effect of the oscillator phase noise on the error of the sensor. The chip occupies only 0.01mm2.
{"title":"A 0.2nJ/sample 0.01mm2 ring oscillator based temperature sensor for on-chip thermal management","authors":"N. Testi, Yang Xu","doi":"10.1109/ISQED.2013.6523686","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523686","url":null,"abstract":"Energy efficient and low area temperature sensors are critical for constantly monitoring the silicon temperature in high density integrated circuits. In this paper, a 0.2nJ/sample ring oscillator based temperature sensor is designed and fabricated in TSMC 65nm CMOS technology. The sensor achieves a maximum inaccuracy of ±3°C after 2-point calibration and a resolution of 0.3°C. Furthermore, a model is proposed to accurately predict the effect of the oscillator phase noise on the error of the sensor. The chip occupies only 0.01mm2.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129539840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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