Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523645
R. Todani, A. K. Mal
Telescopic amplifiers are often preferred for their large DC gain, low power dissipation and low flicker noise. On the other side, they suffer from serious problems like poor input common mode range and output swing. In this work, a simple technique to extract improved common mode range from telescopic structure is presented. To achieve this, two telescopic amplifiers using complementary differential pairs are utilized. The proposed design incorporates a digital switching technique which allows switching between high performance and low power modes. Low power mode allows reduction in power dissipation with compromise on elevated performance parameter. The entire design is verified using UMC 180 nm CMOS technology and the simulation results are presented.
{"title":"A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range","authors":"R. Todani, A. K. Mal","doi":"10.1109/ISQED.2013.6523645","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523645","url":null,"abstract":"Telescopic amplifiers are often preferred for their large DC gain, low power dissipation and low flicker noise. On the other side, they suffer from serious problems like poor input common mode range and output swing. In this work, a simple technique to extract improved common mode range from telescopic structure is presented. To achieve this, two telescopic amplifiers using complementary differential pairs are utilized. The proposed design incorporates a digital switching technique which allows switching between high performance and low power modes. Low power mode allows reduction in power dissipation with compromise on elevated performance parameter. The entire design is verified using UMC 180 nm CMOS technology and the simulation results are presented.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"654 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523663
Takashi Imagawa, Hiroshi Tsutsui, H. Ochi, Takashi Sato
In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.
{"title":"High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA","authors":"Takashi Imagawa, Hiroshi Tsutsui, H. Ochi, Takashi Sato","doi":"10.1109/ISQED.2013.6523663","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523663","url":null,"abstract":"In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130684638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523625
Qiaosha Zou, Jing Xie, Yuan Xie
Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.
{"title":"Cost-driven 3D design optimization with metal layer reduction technique","authors":"Qiaosha Zou, Jing Xie, Yuan Xie","doi":"10.1109/ISQED.2013.6523625","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523625","url":null,"abstract":"Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523626
Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang
Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.
时钟树合成(Clock Tree Synthesis, CTS)主要包括两个步骤:1)时钟树拓扑生成和2)缓冲与嵌入。由于缺乏有效的TSV模型，以往的3D集成电路CTS大多忽略了TSV规划在第一步的作用。本文研究了三维集成电路中tsv感知时钟树拓扑的生成，解决了以往工作忽略的两个主要问题:1)分配tsv的密度分布;2)构造时钟树拓扑时，tsv引起的寄生和耦合效应。实验结果表明，在拓扑生成步骤中考虑tsv对三维时钟网络的影响可以满足制造限制，使设计人员能够在功耗、总导线长度和tsv总数之间取得权衡。实验结果表明，与传统的基于ngg的方法相比，在总长度(TSV等效总长度与水平导线长度之和)变化不大的情况下，TSV数量和功耗分别减少89.6%和40.16%。此外，实验还验证了采用本文提出的三维CTS方法对三维时钟树中tsv - tsv耦合效应的抑制作用。
{"title":"TSV-aware topology generation for 3D Clock Tree Synthesis","authors":"Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang","doi":"10.1109/ISQED.2013.6523626","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523626","url":null,"abstract":"Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523646
K. Kawakami, T. Shiro, Hironobu Yamasaki, K. Yoda, Hiroaki Fujimoto, K. Kawasaki, Yasuhiro Watanabe
We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.
{"title":"Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology","authors":"K. Kawakami, T. Shiro, Hironobu Yamasaki, K. Yoda, Hiroaki Fujimoto, K. Kawasaki, Yasuhiro Watanabe","doi":"10.1109/ISQED.2013.6523646","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523646","url":null,"abstract":"We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction for the micro controller unit (MCU) compared to the conventional low power (LP) process. Measurement result also shows the DDC process improves 56.5 % and 15.0 % of operating frequency, 200 mV and 50 mV of supply voltage margin, or 23.8 % and 19.0 % of power reduction for the MCU and 320 KB SRAM, respectively, even if the Vth of the LP process is adjusted to that of the DDC process. The paper has also discussed the optimal voltage control method, which is suitable for the various applications of sensor network processors.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523637
Jordan Bisasky, H. Homayoun, F. Yazdani, T. Mohsenin
This paper presents a programmable many-core platform containing 64 cores routed in a hierarchical network for biomedical signal processing applications. Individual core processors are based on a RISC architecture with DSP enhancement blocks. Given the number of conditional program loops in DSP applications such as FFT, additional hardware blocks are added that operate in parallel to each core processor. The two blocks calculate the FFT input addresses and determine if a conditional loop is necessary. Performing these operations in parallel to the main processor greatly reduces the time to completion for a DSP application. Each processor is implemented in 65 nm CMOS using standard cell libraries. The 64-core platform occupies 19.51 mm2 and runs at 1.18 GHz at 1 V. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis algorithm utilizes 60 processors and takes 890 ns to execute. Spectral doppler utilizes 29 processors and takes 715 ns to run.
{"title":"A 64-core platform for biomedical signal processing","authors":"Jordan Bisasky, H. Homayoun, F. Yazdani, T. Mohsenin","doi":"10.1109/ISQED.2013.6523637","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523637","url":null,"abstract":"This paper presents a programmable many-core platform containing 64 cores routed in a hierarchical network for biomedical signal processing applications. Individual core processors are based on a RISC architecture with DSP enhancement blocks. Given the number of conditional program loops in DSP applications such as FFT, additional hardware blocks are added that operate in parallel to each core processor. The two blocks calculate the FFT input addresses and determine if a conditional loop is necessary. Performing these operations in parallel to the main processor greatly reduces the time to completion for a DSP application. Each processor is implemented in 65 nm CMOS using standard cell libraries. The 64-core platform occupies 19.51 mm2 and runs at 1.18 GHz at 1 V. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis algorithm utilizes 60 processors and takes 890 ns to execute. Spectral doppler utilizes 29 processors and takes 715 ns to run.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523589
Yinhe Han, Song Jin, Jibing Qiu, Q. Xu, Xiaowei Li
Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging. The chip-level leakage changes under a set of measurement vectors are firstly formulated as an equation set. Solving this equation set can obtain leakage changes in the gates along the critical path. Then, we predict delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase. Our scheme is immune to the runtime noise and accommodates process variation by increasing measurement time overhead. Experimental results demonstrate that our scheme can effectively predict NBTI-induced circuit aging with acceptable accuracy loss.
{"title":"On predicting NBTI-induced circuit aging by isolating leakage change","authors":"Yinhe Han, Song Jin, Jibing Qiu, Q. Xu, Xiaowei Li","doi":"10.1109/ISQED.2013.6523589","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523589","url":null,"abstract":"Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the isolated leakage change in critical path from full-chip leakage measurement result to predict NBTI-induced circuit aging. The chip-level leakage changes under a set of measurement vectors are firstly formulated as an equation set. Solving this equation set can obtain leakage changes in the gates along the critical path. Then, we predict delay degradation on arbitrary critical path based on the correlation between leakage change and delay increase. Our scheme is immune to the runtime noise and accommodates process variation by increasing measurement time overhead. Experimental results demonstrate that our scheme can effectively predict NBTI-induced circuit aging with acceptable accuracy loss.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523686
N. Testi, Yang Xu
Energy efficient and low area temperature sensors are critical for constantly monitoring the silicon temperature in high density integrated circuits. In this paper, a 0.2nJ/sample ring oscillator based temperature sensor is designed and fabricated in TSMC 65nm CMOS technology. The sensor achieves a maximum inaccuracy of ±3°C after 2-point calibration and a resolution of 0.3°C. Furthermore, a model is proposed to accurately predict the effect of the oscillator phase noise on the error of the sensor. The chip occupies only 0.01mm2.
{"title":"A 0.2nJ/sample 0.01mm2 ring oscillator based temperature sensor for on-chip thermal management","authors":"N. Testi, Yang Xu","doi":"10.1109/ISQED.2013.6523686","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523686","url":null,"abstract":"Energy efficient and low area temperature sensors are critical for constantly monitoring the silicon temperature in high density integrated circuits. In this paper, a 0.2nJ/sample ring oscillator based temperature sensor is designed and fabricated in TSMC 65nm CMOS technology. The sensor achieves a maximum inaccuracy of ±3°C after 2-point calibration and a resolution of 0.3°C. Furthermore, a model is proposed to accurately predict the effect of the oscillator phase noise on the error of the sensor. The chip occupies only 0.01mm2.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129539840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523609
M. Sharad, Deliang Fan, K. Roy
CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid analog processing units that are compact as well as low power. In this work we present a mixed-mode signal processing scheme employing “domain wall neurons” that involves energy efficient analog-mode computation upon digital data. Simulation results for 8-bit, 16-tap FIR filter show that such a design can achieve 10x lower power consumption and 16x lower area as compared to an optimized digital CMOS design at the same technology node. In such a design area saving can be traded off for enhanced power savings, depending upon the target application.
{"title":"Low power and compact mixed-mode signal processing hardware using spin-neurons","authors":"M. Sharad, Deliang Fan, K. Roy","doi":"10.1109/ISQED.2013.6523609","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523609","url":null,"abstract":"CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid analog processing units that are compact as well as low power. In this work we present a mixed-mode signal processing scheme employing “domain wall neurons” that involves energy efficient analog-mode computation upon digital data. Simulation results for 8-bit, 16-tap FIR filter show that such a design can achieve 10x lower power consumption and 16x lower area as compared to an optimized digital CMOS design at the same technology node. In such a design area saving can be traded off for enhanced power savings, depending upon the target application.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121197288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523667
Zihao Chen, Hailong Yao, Yici Cai
In triple patterning lithography (TPL), balanced feature density on each layout mask helps facilitate the following OPC process. This paper presents the first spacing uniformity-aware layout decomposition method, called SUALD, which formulates the density optimization problem in TPL based on the spacings between locally adjacent features on each colored layout mask, and hence enhances the patterning quality. Based on the new density formulation, a spacing uniformity graph is built using the Voronoi diagram. An effective heuristic triple partitioning algorithm is also proposed for TPL layout decomposition. Experimental results are very promising and show that SUALD obtains 69% and 40% improvements in average in the presented density metrics over an integer linear programming method without density control.
{"title":"SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography","authors":"Zihao Chen, Hailong Yao, Yici Cai","doi":"10.1109/ISQED.2013.6523667","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523667","url":null,"abstract":"In triple patterning lithography (TPL), balanced feature density on each layout mask helps facilitate the following OPC process. This paper presents the first spacing uniformity-aware layout decomposition method, called SUALD, which formulates the density optimization problem in TPL based on the spacings between locally adjacent features on each colored layout mask, and hence enhances the patterning quality. Based on the new density formulation, a spacing uniformity graph is built using the Voronoi diagram. An effective heuristic triple partitioning algorithm is also proposed for TPL layout decomposition. Experimental results are very promising and show that SUALD obtains 69% and 40% improvements in average in the presented density metrics over an integer linear programming method without density control.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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