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Effect-cause intra-cell diagnosis at transistor level 晶体管水平的因果细胞内诊断
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523652
Zhenzhou Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray
Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the “Effect-Cause” approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.
逻辑诊断是在有缺陷的电路中隔离观察到的错误的可能来源的过程,以便进行物理故障分析以确定此类错误的根本原因。因此,有效准确的逻辑诊断对于加快物理失效分析过程,最终提高成品率至关重要。为了提高缺陷定位的准确性,本文提出了一种基于“因果法”的细胞内诊断方法。提出的方法是基于关键路径跟踪,这里应用在晶体管级。它可以精确定位观察到的错误的根本原因。实验结果表明了该方法的有效性。
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引用次数: 12
Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector 用电压整流器代替功率检测器的6gbps连续时间自适应均衡器的设计
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523640
K. Srinivasan, J. Rosenfeld
Two types of voltage rectifiers, CMOS based and diode based, are compared for potential application in an adaptive equalizer feedback loop. The CMOS rectifier, however, works only at lower frequencies and is limited by the maximum rectification frequency. Instead, voltage rectification in an adaptive equalizer is demonstrated by simulation using an ideal Schottky diode. Prior work done by other researchers on this topic, use a power detector, instead of a voltage rectifier. This paper shows that a voltage rectifier, instead of a power detector, can also be used in the adaptive equalizer topology discussed.
比较了基于CMOS和基于二极管的两种电压整流器在自适应均衡器反馈回路中的潜在应用。然而,CMOS整流器只能在较低的频率下工作,并且受到最大整流频率的限制。相反,电压整流在自适应均衡器是通过模拟使用理想肖特基二极管证明。其他研究人员在此主题上所做的先前工作使用功率检测器,而不是电压整流器。本文表明,在讨论的自适应均衡器拓扑中,也可以使用电压整流器代替功率检测器。
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引用次数: 0
Multi-trap RTN parameter extraction based on Bayesian inference 基于贝叶斯推理的多陷阱RTN参数提取
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523672
H. Awano, Hiroshi Tsutsui, H. Ochi, Takashi Sato
This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.
提出了一种新的估计随机电报噪声统计参数的分析方法。RTN的特征是载流子捕获和发射的时间常数,以及相应的阈值电压的变化。由于陷阱活动被投射到阈值电压上,每个陷阱的时间常数和振幅的分离是一个不适定问题。该方法采用统计方法,能够反映RTN的物理生成过程,解决了这一问题。利用统计机器学习社区开发的Gibbs采样算法,将测量的阈值电压序列分解为每个陷阱的时间常数和幅度。我们还证明,该方法估计时间常数的精度比使用隐马尔可夫模型的现有工作提高了约2.1倍,有助于提高可靠性感知电路仿真的精度。
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引用次数: 10
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA 面向资源受限CGRA的选择性TMR高速dfg级SEU漏洞分析
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523663
Takashi Imagawa, Hiroshi Tsutsui, H. Ochi, Takashi Sato
In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.
本文研究了一种针对单事件干扰(SEU)实现低成本选择性三模冗余(selective TMR)的方法。该方法使我们能够最大限度地减少在资源受限的粗粒度可重构体系结构(CGRA)上实现的目标应用电路的脆弱性。该方法的关键是利用评估函数确定目标应用的数据流图(DFG)中的脆弱节点。由于节点故障对主输出的影响不仅取决于节点本身,还取决于节点的风扇和扇出,因此本文提出了一种增强的评估函数,反映节点风扇和扇出的运行情况。本文还改进了评价函数中权重向量的推导方法,将节点脆弱性的线性分布改为指数分布。为了得到一个通用的权重向量,我们建议求解从多个样本应用中获得的串联线性方程,而不是对应用的权重向量进行平均。该方法利用广义逆矩阵求解方程,在不到10秒的时间内提取出选择性TMR的合理优先级,比穷举搜索最优解需要15小时以上的时间要快得多。本文还比较了在评估函数中使用的特征的贡献,这将对设计可靠感知的CGRA体系结构和综合工具有一定的指导意义。
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引用次数: 5
Cost-driven 3D design optimization with metal layer reduction technique 成本驱动的3D设计优化与金属层减少技术
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523625
Qiaosha Zou, Jing Xie, Yuan Xie
Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.
三维集成电路(3D IC)是一个很有前途的解决方案,以继续性能缩放。然而,3D集成电路的制造成本可能是采用这种新兴技术的主要问题。在本文中,我们研究了基于tsv和基于中间体的3D集成电路的成本含义,观察到许多2D设计中的长金属互连被3D设计中的tsv所取代,因此可以减少满足布线要求的金属层数,从而节省3D集成电路的成本。基于我们的成本模型,我们提出了一个成本驱动的3D设计空间优化流程,通过优化硅面积和金属层数之间的成本权衡,平衡设计面积和金属层需求。通过成本驱动的设计优化流程,与基线设计相比,基于tsv的3D设计可以节省19%的成本,基于interpoer的3D设计可以节省26%的成本。
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引用次数: 6
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors 异构三维集成:一种优化芯片多处理器效率/成本的方案
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523582
S. Priyadarshi, N. Choudhary, Brandon H. Dwiel, Ankita Upreti, E. Rotenberg, W. R. Davis, P. Franzon
Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dies, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6× and 1.5× higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also present a sensitivity analysis by sweeping the defect density ratio. The analysis reveals the defect density break-even points, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking significant points in the maturing of the technology.
处理器设计向新技术过渡的时机是一个令人激动的权衡。一方面,尽早进行转换可以提供显著的竞争优势,因为可以将改进的设计尽早推向市场。另一方面,激进的策略可能被证明是无利可图的,因为一项技术的制造产量很低,还没有时间成熟。我们建议利用两种互补的异构形式来利用芯片多处理器(CMP)的不成熟技术。首先,3D集成促进了一种技术合金。CMP分为两个模具,一个用旧技术制造,另一个用新技术制造。这种合金从新技术中获益,同时降低了成本。其次,为了弥补老技术核心的低效率,我们利用应用程序和微架构的异质性:在老技术核心上调度从技术扩展中获得较少收益的应用程序,并且这些核心被返回以优化这类应用程序。在45nm和65nm之间的缺陷密度比为200时,与2D和3D均质实现相比,Hetero2 3D的效率/成本分别提高了3.6倍和1.5倍,效率仅下降6.5%。我们还提出了通过扫描缺陷密度比的灵敏度分析。分析揭示了缺陷密度的收支平衡点,在45nm的均匀2D和3D设计中,可以实现与Hetero2 3D相同的效率/成本,这标志着该技术的成熟。
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引用次数: 5
Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling 用恒压电力传输线在低功率下最大限度地减少高速信号的同时开关噪声
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523689
Satyanarayana Telikepalli, M. Swaminathan, D. Keezer
Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.
在高速数字系统中,信号和电源的完整性是保证高性能的关键。随着数字系统工作频率的提高,同时开关噪声(SSN)产生的功率和地弹跳已成为这些设备性能的限制因素。SSN是由电力输送网络(PDN)中存在的寄生电感引起的,电源和地轨上的电压波动会导致噪声裕度降低,并会限制数字设备的最大频率。已经提出了一种新的PDN设计,通过用输电线路(PTL)取代电源平面结构来显著降低SSN[1]。本文提出了一种新的电力传输方案,称为恒压输电线路(CV-PTL),它可以显著降低开关噪声,同时降低功耗。这个概念已经通过理论、模拟和测量得到了证明。
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引用次数: 5
TSV-aware topology generation for 3D Clock Tree Synthesis 三维时钟树合成的tsv感知拓扑生成
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523626
Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang
Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.
时钟树合成(Clock Tree Synthesis, CTS)主要包括两个步骤:1)时钟树拓扑生成和2)缓冲与嵌入。由于缺乏有效的TSV模型,以往的3D集成电路CTS大多忽略了TSV规划在第一步的作用。本文研究了三维集成电路中tsv感知时钟树拓扑的生成,解决了以往工作忽略的两个主要问题:1)分配tsv的密度分布;2)构造时钟树拓扑时,tsv引起的寄生和耦合效应。实验结果表明,在拓扑生成步骤中考虑tsv对三维时钟网络的影响可以满足制造限制,使设计人员能够在功耗、总导线长度和tsv总数之间取得权衡。实验结果表明,与传统的基于ngg的方法相比,在总长度(TSV等效总长度与水平导线长度之和)变化不大的情况下,TSV数量和功耗分别减少89.6%和40.16%。此外,实验还验证了采用本文提出的三维CTS方法对三维时钟树中tsv - tsv耦合效应的抑制作用。
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引用次数: 14
A virtualization approach for MIPS-based MPSoCs 基于mips的mpsoc的虚拟化方法
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523674
A. Aguiar, C. Moratelli, M. Sartori, Fabiano Hessel
Recently, virtualization techniques has been investigated as an interesting approach for complex embedded systems designs since they allow more secure systems, improve software design quality and reduce costs. However, the need to meet design constraints, mainly the real-time constraints, constitutes one of the biggest challenges that may prevent the wide adoption of virtualization in embedded systems. Industry designers and researchers believe that the use of hardware support to virtualization is a possible way of improving the system's performance and meeting its real-time constraints. In this paper we present our virtualization-aware architecture intended for MIPS processors with support to real-time applications. In our proposed approach no changes are needed in the Guest OS since we implement a full virtualization scheme. Real-time constraints are achieved by mixing the full virtualization technique with hardware support along with bare-metal application usage. Details of our virtualization platform are presented and discussed in the paper. Results demonstrate the effectiveness of our approach considering the hardware impact in terms of area, the software performance overhead, and the operating system port to allow its execution in a virtualized environment.
最近,虚拟化技术作为复杂嵌入式系统设计的一种有趣的方法被研究,因为它们允许更安全的系统,提高软件设计质量并降低成本。然而,需要满足设计约束,主要是实时约束,构成了可能阻碍虚拟化在嵌入式系统中广泛采用的最大挑战之一。工业设计师和研究人员认为,使用硬件支持虚拟化是提高系统性能和满足其实时限制的一种可能方法。在本文中,我们提出了用于支持实时应用程序的MIPS处理器的虚拟化感知架构。在我们建议的方法中,由于我们实现了一个完整的虚拟化方案,因此不需要对来宾操作系统进行任何更改。实时约束是通过将完全虚拟化技术与硬件支持以及裸机应用程序的使用相结合来实现的。本文对我们的虚拟化平台进行了详细的介绍和讨论。结果表明,考虑到硬件对面积的影响、软件性能开销和允许在虚拟化环境中执行的操作系统端口,我们的方法是有效的。
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引用次数: 2
A CMOS high dimming ratio power-LED driver with a preloading inductor current method 一种带预载电感电流法的CMOS高调光比功率led驱动器
Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523688
K. Yoon, Keon Lee
This paper presents a high dimming ratio LED driver for automotive lighting applications which require avoiding EMI radiation. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed circuit to achieve the fast transient response time during the LED load switching. The proposed circuit receives the input voltage of 12V and generates the output voltage of 30V with the load current of 350mA. The chip is implemented with 0.35um BCDMOS process, and the die area is 2.35 × 2.35 mm2. Measurement results illustrate that the proposed LED drive system features the minimum rising time as small as 240ns and the corresponding dimming ratio becomes 2000:1 at the dimming frequency of 1KHz. The maximum power conversion efficiency of the chip is measured to be 94.82%.
本文提出了一种高调光比的LED驱动器,用于需要避免电磁干扰辐射的汽车照明。为了实现高调光比的LED驱动,在电路的功率级提出了预加载电感电流方法,以实现LED负载切换时的快速瞬态响应时间。本设计电路接收12V输入电压,产生30V输出电压,负载电流350mA。该芯片采用0.35um的BCDMOS工艺实现,芯片面积为2.35 × 2.35 mm2。测量结果表明,在调光频率为1KHz时,所提出的LED驱动系统的最小上升时间小至240ns,相应的调光比为2000:1。该芯片的最大功率转换效率为94.82%。
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引用次数: 3
期刊
International Symposium on Quality Electronic Design (ISQED)
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