Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523640
K. Srinivasan, J. Rosenfeld
Two types of voltage rectifiers, CMOS based and diode based, are compared for potential application in an adaptive equalizer feedback loop. The CMOS rectifier, however, works only at lower frequencies and is limited by the maximum rectification frequency. Instead, voltage rectification in an adaptive equalizer is demonstrated by simulation using an ideal Schottky diode. Prior work done by other researchers on this topic, use a power detector, instead of a voltage rectifier. This paper shows that a voltage rectifier, instead of a power detector, can also be used in the adaptive equalizer topology discussed.
{"title":"Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector","authors":"K. Srinivasan, J. Rosenfeld","doi":"10.1109/ISQED.2013.6523640","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523640","url":null,"abstract":"Two types of voltage rectifiers, CMOS based and diode based, are compared for potential application in an adaptive equalizer feedback loop. The CMOS rectifier, however, works only at lower frequencies and is limited by the maximum rectification frequency. Instead, voltage rectification in an adaptive equalizer is demonstrated by simulation using an ideal Schottky diode. Prior work done by other researchers on this topic, use a power detector, instead of a voltage rectifier. This paper shows that a voltage rectifier, instead of a power detector, can also be used in the adaptive equalizer topology discussed.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523672
H. Awano, Hiroshi Tsutsui, H. Ochi, Takashi Sato
This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.
{"title":"Multi-trap RTN parameter extraction based on Bayesian inference","authors":"H. Awano, Hiroshi Tsutsui, H. Ochi, Takashi Sato","doi":"10.1109/ISQED.2013.6523672","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523672","url":null,"abstract":"This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523689
Satyanarayana Telikepalli, M. Swaminathan, D. Keezer
Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.
{"title":"Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling","authors":"Satyanarayana Telikepalli, M. Swaminathan, D. Keezer","doi":"10.1109/ISQED.2013.6523689","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523689","url":null,"abstract":"Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523665
Dheepakkumaran Jayaraman, S. Tragoudas
In this paper we present a novel algorithm to identify infeasible paths in the behavioral code. The proposed approach initially partitions the behavioral code into segments. At each code segment it stores feasible paths implicitly. It also stores collections of input assignments which are derived using selected statements in the code segment. The method requires state-of-the-art data structures to store feasible paths and the required functions. Experimental results demonstrate the scalability of the proposed method.
{"title":"Performance validation through implicit removal of infeasible paths of the behavioral description","authors":"Dheepakkumaran Jayaraman, S. Tragoudas","doi":"10.1109/ISQED.2013.6523665","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523665","url":null,"abstract":"In this paper we present a novel algorithm to identify infeasible paths in the behavioral code. The proposed approach initially partitions the behavioral code into segments. At each code segment it stores feasible paths implicitly. It also stores collections of input assignments which are derived using selected statements in the code segment. The method requires state-of-the-art data structures to store feasible paths and the required functions. Experimental results demonstrate the scalability of the proposed method.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123512113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523616
J. Shin, N. Dutt, F. Kurdahi
As we enter the deep submicron era, transistors are increasingly added to chips, causing the chips to become hotter in a non-uniform manner. This is due to different processing tasks in different parts of the chips. This thermal gradient also causes a great number of problems such as the reduction in reliability of chips and interconnects due to electromigration, and system performance degradation because of increased delay and lowered clock frequencies. Since these thermal issues exist, interconnect routing, especially global routing, should be performed to consider the temperature distribution of substrates and the actual delay of interconnects. In this paper, we propose a global routing method based on image processing and computer vision techniques in which the probability of chip failure due to interconnect failure is reduced, and performance degradation from increased delay is also prevented. We observed that our method reduced the number of grids in hot regions by up to 50 % when compared with a conventional router, while maintaining the delay of interconnects as small as possible.
{"title":"Vision-inspired global routing for enhanced performance and reliability","authors":"J. Shin, N. Dutt, F. Kurdahi","doi":"10.1109/ISQED.2013.6523616","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523616","url":null,"abstract":"As we enter the deep submicron era, transistors are increasingly added to chips, causing the chips to become hotter in a non-uniform manner. This is due to different processing tasks in different parts of the chips. This thermal gradient also causes a great number of problems such as the reduction in reliability of chips and interconnects due to electromigration, and system performance degradation because of increased delay and lowered clock frequencies. Since these thermal issues exist, interconnect routing, especially global routing, should be performed to consider the temperature distribution of substrates and the actual delay of interconnects. In this paper, we propose a global routing method based on image processing and computer vision techniques in which the probability of chip failure due to interconnect failure is reduced, and performance degradation from increased delay is also prevented. We observed that our method reduced the number of grids in hot regions by up to 50 % when compared with a conventional router, while maintaining the delay of interconnects as small as possible.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523652
Zhenzhou Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray
Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the “Effect-Cause” approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.
{"title":"Effect-cause intra-cell diagnosis at transistor level","authors":"Zhenzhou Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray","doi":"10.1109/ISQED.2013.6523652","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523652","url":null,"abstract":"Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the “Effect-Cause” approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121328506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523688
K. Yoon, Keon Lee
This paper presents a high dimming ratio LED driver for automotive lighting applications which require avoiding EMI radiation. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed circuit to achieve the fast transient response time during the LED load switching. The proposed circuit receives the input voltage of 12V and generates the output voltage of 30V with the load current of 350mA. The chip is implemented with 0.35um BCDMOS process, and the die area is 2.35 × 2.35 mm2. Measurement results illustrate that the proposed LED drive system features the minimum rising time as small as 240ns and the corresponding dimming ratio becomes 2000:1 at the dimming frequency of 1KHz. The maximum power conversion efficiency of the chip is measured to be 94.82%.
{"title":"A CMOS high dimming ratio power-LED driver with a preloading inductor current method","authors":"K. Yoon, Keon Lee","doi":"10.1109/ISQED.2013.6523688","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523688","url":null,"abstract":"This paper presents a high dimming ratio LED driver for automotive lighting applications which require avoiding EMI radiation. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed circuit to achieve the fast transient response time during the LED load switching. The proposed circuit receives the input voltage of 12V and generates the output voltage of 30V with the load current of 350mA. The chip is implemented with 0.35um BCDMOS process, and the die area is 2.35 × 2.35 mm2. Measurement results illustrate that the proposed LED drive system features the minimum rising time as small as 240ns and the corresponding dimming ratio becomes 2000:1 at the dimming frequency of 1KHz. The maximum power conversion efficiency of the chip is measured to be 94.82%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132700516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523687
S. Nishizawa, T. Ishihara, H. Onodera
The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.
{"title":"Analysis and comparison of XOR cell structures for low voltage circuit design","authors":"S. Nishizawa, T. Ishihara, H. Onodera","doi":"10.1109/ISQED.2013.6523687","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523687","url":null,"abstract":"The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the dual pass transistor XOR has a better performance than the complementary CMOS XOR in 0.6V operation, while the complementary CMOS XOR has a better performance in 1.2 V operation. More specifically, the area and the power consumption of a benchmark circuit composed of the dual pass transistor XOR can be reduced by 24% and 35%, respectively, compared to those of the same circuit composed of the complementary CMOS XOR in 0.6V operation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"553 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523639
Bahram N. Uchevler, K. Svarstad, J. Kuper, Christiaan Baaij
With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.
{"title":"System-level modelling of dynamic reconfigurable designs using functional programming abstractions","authors":"Bahram N. Uchevler, K. Svarstad, J. Kuper, Christiaan Baaij","doi":"10.1109/ISQED.2013.6523639","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523639","url":null,"abstract":"With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133178950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523658
Yuko Hara-Azumi, H. Tomiyama
Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. Most literature on system-level design techniques has been conventionally tackling this issue by spatial and/or temporal modular redundancy, whose cost in circuit area and performance is large. This paper proposes a soft error-aware scheduling method in high-level synthesis (HLS), which does not rely on such expensive, conventional techniques. The reliability of the datapath circuit is determined not only by that of hardware resources to which operations and values are assigned, but also that of their active time (i.e., time during which operational results should be correct). By considering both of these factors, our proposed method schedules operations so that the reliability of HLS-generated datapath circuits can be maximized under designer-given area/latency constraints. Experimental results demonstrate the effectiveness of our method over existing methods, especially for strict area/latency constraints.
{"title":"Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation","authors":"Yuko Hara-Azumi, H. Tomiyama","doi":"10.1109/ISQED.2013.6523658","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523658","url":null,"abstract":"Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today's LSI design. Most literature on system-level design techniques has been conventionally tackling this issue by spatial and/or temporal modular redundancy, whose cost in circuit area and performance is large. This paper proposes a soft error-aware scheduling method in high-level synthesis (HLS), which does not rely on such expensive, conventional techniques. The reliability of the datapath circuit is determined not only by that of hardware resources to which operations and values are assigned, but also that of their active time (i.e., time during which operational results should be correct). By considering both of these factors, our proposed method schedules operations so that the reliability of HLS-generated datapath circuits can be maximized under designer-given area/latency constraints. Experimental results demonstrate the effectiveness of our method over existing methods, especially for strict area/latency constraints.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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