Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523652
Zhenzhou Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray
Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the “Effect-Cause” approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.
{"title":"Effect-cause intra-cell diagnosis at transistor level","authors":"Zhenzhou Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray","doi":"10.1109/ISQED.2013.6523652","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523652","url":null,"abstract":"Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the “Effect-Cause” approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a precise localization of the root cause of observed errors. Experimental results show the efficiency of our approach.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121328506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523640
K. Srinivasan, J. Rosenfeld
Two types of voltage rectifiers, CMOS based and diode based, are compared for potential application in an adaptive equalizer feedback loop. The CMOS rectifier, however, works only at lower frequencies and is limited by the maximum rectification frequency. Instead, voltage rectification in an adaptive equalizer is demonstrated by simulation using an ideal Schottky diode. Prior work done by other researchers on this topic, use a power detector, instead of a voltage rectifier. This paper shows that a voltage rectifier, instead of a power detector, can also be used in the adaptive equalizer topology discussed.
{"title":"Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector","authors":"K. Srinivasan, J. Rosenfeld","doi":"10.1109/ISQED.2013.6523640","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523640","url":null,"abstract":"Two types of voltage rectifiers, CMOS based and diode based, are compared for potential application in an adaptive equalizer feedback loop. The CMOS rectifier, however, works only at lower frequencies and is limited by the maximum rectification frequency. Instead, voltage rectification in an adaptive equalizer is demonstrated by simulation using an ideal Schottky diode. Prior work done by other researchers on this topic, use a power detector, instead of a voltage rectifier. This paper shows that a voltage rectifier, instead of a power detector, can also be used in the adaptive equalizer topology discussed.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523672
H. Awano, Hiroshi Tsutsui, H. Ochi, Takashi Sato
This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.
{"title":"Multi-trap RTN parameter extraction based on Bayesian inference","authors":"H. Awano, Hiroshi Tsutsui, H. Ochi, Takashi Sato","doi":"10.1109/ISQED.2013.6523672","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523672","url":null,"abstract":"This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523663
Takashi Imagawa, Hiroshi Tsutsui, H. Ochi, Takashi Sato
In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.
{"title":"High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA","authors":"Takashi Imagawa, Hiroshi Tsutsui, H. Ochi, Takashi Sato","doi":"10.1109/ISQED.2013.6523663","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523663","url":null,"abstract":"In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130684638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523625
Qiaosha Zou, Jing Xie, Yuan Xie
Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.
{"title":"Cost-driven 3D design optimization with metal layer reduction technique","authors":"Qiaosha Zou, Jing Xie, Yuan Xie","doi":"10.1109/ISQED.2013.6523625","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523625","url":null,"abstract":"Three-dimensional integrated circuit (3D IC) is a promising solution to continue the performance scaling. However, the fabrication cost for 3D ICs can be a major concern for the adoption of this emerging technology. In this paper, we study the cost implication for both TSV-based and interposer-based 3D ICs, with the observation that many long metal interconnects in 2D designs are replaced by TSVs in 3D designs, and therefore the number of metal layers to satisfy routing requirements can be reduced, resulting in cost saving in 3D ICs. Based on our cost model, we propose a cost-driven 3D design space optimization flow that balances the design area and metal layer requirement, by optimizing the cost tradeoffs between silicon area and the number of metal layers. With the cost-driven design optimization flow, we can achieve cost saving up to 19% for TSV-based 3D designs, and 26% for interposer-based 3D designs, respectively, compared to the baseline designs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523582
S. Priyadarshi, N. Choudhary, Brandon H. Dwiel, Ankita Upreti, E. Rotenberg, W. R. Davis, P. Franzon
Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dies, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6× and 1.5× higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also present a sensitivity analysis by sweeping the defect density ratio. The analysis reveals the defect density break-even points, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking significant points in the maturing of the technology.
{"title":"Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors","authors":"S. Priyadarshi, N. Choudhary, Brandon H. Dwiel, Ankita Upreti, E. Rotenberg, W. R. Davis, P. Franzon","doi":"10.1109/ISQED.2013.6523582","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523582","url":null,"abstract":"Timing the transition of a processor design to a new technology poses a provocative tradeoff. On the one hand, transitioning as early as possible offers a significant competitive advantage, by bringing improved designs to market early. On the other hand, an aggressive strategy may prove to be unprofitable, due to the low manufacturing yield of a technology that has not had time to mature. We propose exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP). First, 3D integration facilitates a technology alloy. The CMP is split across two dies, one fabricated in the old technology and the other in the new technology. The alloy derives benefit from the new technology while limiting cost exposure. Second, to compensate for lower efficiency of old-technology cores, we exploit application and microarchitectural heterogeneity: applications which gain less from technology scaling are scheduled on old-technology cores, moreover, these cores are retuned to optimize this class of application. For a defect density ratio of 200 between 45nm and 65nm, Hetero2 3D gives 3.6× and 1.5× higher efficiency/cost compared to 2D and 3D homogeneous implementations, respectively, with only 6.5% degradation in efficiency. We also present a sensitivity analysis by sweeping the defect density ratio. The analysis reveals the defect density break-even points, where homogeneous 2D and 3D designs in 45nm achieve the same efficiency/cost as Hetero2 3D, marking significant points in the maturing of the technology.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128967079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523689
Satyanarayana Telikepalli, M. Swaminathan, D. Keezer
Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.
{"title":"Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling","authors":"Satyanarayana Telikepalli, M. Swaminathan, D. Keezer","doi":"10.1109/ISQED.2013.6523689","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523689","url":null,"abstract":"Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523626
Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang
Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.
时钟树合成(Clock Tree Synthesis, CTS)主要包括两个步骤:1)时钟树拓扑生成和2)缓冲与嵌入。由于缺乏有效的TSV模型，以往的3D集成电路CTS大多忽略了TSV规划在第一步的作用。本文研究了三维集成电路中tsv感知时钟树拓扑的生成，解决了以往工作忽略的两个主要问题:1)分配tsv的密度分布;2)构造时钟树拓扑时，tsv引起的寄生和耦合效应。实验结果表明，在拓扑生成步骤中考虑tsv对三维时钟网络的影响可以满足制造限制，使设计人员能够在功耗、总导线长度和tsv总数之间取得权衡。实验结果表明，与传统的基于ngg的方法相比，在总长度(TSV等效总长度与水平导线长度之和)变化不大的情况下，TSV数量和功耗分别减少89.6%和40.16%。此外，实验还验证了采用本文提出的三维CTS方法对三维时钟树中tsv - tsv耦合效应的抑制作用。
{"title":"TSV-aware topology generation for 3D Clock Tree Synthesis","authors":"Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang","doi":"10.1109/ISQED.2013.6523626","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523626","url":null,"abstract":"Clock Tree Synthesis (CTS) mainly consists of two steps: 1) clock tree topology generation and 2) buffering and embedding. Due to the lack of the efficient model of TSVs, most previous CTS of 3D ICs ignore the effect of TSV planning in the first step. In this paper, we study the TSV-aware clock tree topology generation for 3D ICs by solving two major issues that the previous work has neglected: 1) the density distribution of allocated TSVs; 2) the parasitic and coupling effects induced by TSVs in constructing the topology of clock tree. The experimental results show that considering the impact of TSVs on 3D clock network in the topology generation step can meet the manufacture limitations and enable the designers to obtain the tradeoff among power consumption, the total wire length and the total number of TSVs. The experimental results show that TSVs number and power consumption can be reduced by up to 89.6%and 40.16% respectively with little variation of the total wirelength (the sum of total TSV equivalent wirelength and horizontal wire length) compared to the traditional NNG-based method. Besides, the mitigation of TSV-to-TSV coupling effect in 3D clock tree by implementing the proposed 3D CTS method is demonstrated in our experiment.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523674
A. Aguiar, C. Moratelli, M. Sartori, Fabiano Hessel
Recently, virtualization techniques has been investigated as an interesting approach for complex embedded systems designs since they allow more secure systems, improve software design quality and reduce costs. However, the need to meet design constraints, mainly the real-time constraints, constitutes one of the biggest challenges that may prevent the wide adoption of virtualization in embedded systems. Industry designers and researchers believe that the use of hardware support to virtualization is a possible way of improving the system's performance and meeting its real-time constraints. In this paper we present our virtualization-aware architecture intended for MIPS processors with support to real-time applications. In our proposed approach no changes are needed in the Guest OS since we implement a full virtualization scheme. Real-time constraints are achieved by mixing the full virtualization technique with hardware support along with bare-metal application usage. Details of our virtualization platform are presented and discussed in the paper. Results demonstrate the effectiveness of our approach considering the hardware impact in terms of area, the software performance overhead, and the operating system port to allow its execution in a virtualized environment.
{"title":"A virtualization approach for MIPS-based MPSoCs","authors":"A. Aguiar, C. Moratelli, M. Sartori, Fabiano Hessel","doi":"10.1109/ISQED.2013.6523674","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523674","url":null,"abstract":"Recently, virtualization techniques has been investigated as an interesting approach for complex embedded systems designs since they allow more secure systems, improve software design quality and reduce costs. However, the need to meet design constraints, mainly the real-time constraints, constitutes one of the biggest challenges that may prevent the wide adoption of virtualization in embedded systems. Industry designers and researchers believe that the use of hardware support to virtualization is a possible way of improving the system's performance and meeting its real-time constraints. In this paper we present our virtualization-aware architecture intended for MIPS processors with support to real-time applications. In our proposed approach no changes are needed in the Guest OS since we implement a full virtualization scheme. Real-time constraints are achieved by mixing the full virtualization technique with hardware support along with bare-metal application usage. Details of our virtualization platform are presented and discussed in the paper. Results demonstrate the effectiveness of our approach considering the hardware impact in terms of area, the software performance overhead, and the operating system port to allow its execution in a virtualized environment.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124554221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523688
K. Yoon, Keon Lee
This paper presents a high dimming ratio LED driver for automotive lighting applications which require avoiding EMI radiation. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed circuit to achieve the fast transient response time during the LED load switching. The proposed circuit receives the input voltage of 12V and generates the output voltage of 30V with the load current of 350mA. The chip is implemented with 0.35um BCDMOS process, and the die area is 2.35 × 2.35 mm2. Measurement results illustrate that the proposed LED drive system features the minimum rising time as small as 240ns and the corresponding dimming ratio becomes 2000:1 at the dimming frequency of 1KHz. The maximum power conversion efficiency of the chip is measured to be 94.82%.
{"title":"A CMOS high dimming ratio power-LED driver with a preloading inductor current method","authors":"K. Yoon, Keon Lee","doi":"10.1109/ISQED.2013.6523688","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523688","url":null,"abstract":"This paper presents a high dimming ratio LED driver for automotive lighting applications which require avoiding EMI radiation. In order to accomplish a high dimming ratio LED driver, the preloading inductor current methodology is proposed for the power stage of the proposed circuit to achieve the fast transient response time during the LED load switching. The proposed circuit receives the input voltage of 12V and generates the output voltage of 30V with the load current of 350mA. The chip is implemented with 0.35um BCDMOS process, and the die area is 2.35 × 2.35 mm2. Measurement results illustrate that the proposed LED drive system features the minimum rising time as small as 240ns and the corresponding dimming ratio becomes 2000:1 at the dimming frequency of 1KHz. The maximum power conversion efficiency of the chip is measured to be 94.82%.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132700516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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