Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523604
T. Yu, Martin D. F. Wong
In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy to decide which pads are moved to the new locations. After each movement of the pads, a static IR-drop analysis is performed. We develop multigrid accelerated modified Simulated Annealing method (MG_SA) and compare it with the proposed method on a set of test cases. Experimental results show that the proposed method outperforms MG_SA with similar or less IR-drop values and much less runtime.
{"title":"A novel and efficient method for power pad placement optimization","authors":"T. Yu, Martin D. F. Wong","doi":"10.1109/ISQED.2013.6523604","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523604","url":null,"abstract":"In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy to decide which pads are moved to the new locations. After each movement of the pads, a static IR-drop analysis is performed. We develop multigrid accelerated modified Simulated Annealing method (MG_SA) and compare it with the proposed method on a set of test cases. Experimental results show that the proposed method outperforms MG_SA with similar or less IR-drop values and much less runtime.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115593759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523666
Richard Lee, Karim Abdel-Khalek, S. Abdi, Frederic Risacher
This paper describes a methodology for developing abstract and executable system-level model in SystemC of real-time embedded software, targeted to an RTOS. We design a RTOS emulation layer, called RESC, on top of the SystemC kernel. The application software is linked against the emulation layer to create an executable model of the software. The model can be integrated into system level HW-SW models which can be used for fast, accurate and early system validation. We first identify key real-time software constructs such as task-level concurrency, priorities, timers, pulses, and message-passing communication. We, then, define equivalent abstractions of the constructs in RESC on top of the SystemC library. We validated our models using industrial-size examples such as MP3 decoder and Vocoder. The experimental results show that our models are very accurate (<; 1% error) and significantly faster (up to 11X) than real-time software execution on target platform.
{"title":"Early system level modeling of real-time applications on embedded platforms","authors":"Richard Lee, Karim Abdel-Khalek, S. Abdi, Frederic Risacher","doi":"10.1109/ISQED.2013.6523666","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523666","url":null,"abstract":"This paper describes a methodology for developing abstract and executable system-level model in SystemC of real-time embedded software, targeted to an RTOS. We design a RTOS emulation layer, called RESC, on top of the SystemC kernel. The application software is linked against the emulation layer to create an executable model of the software. The model can be integrated into system level HW-SW models which can be used for fast, accurate and early system validation. We first identify key real-time software constructs such as task-level concurrency, priorities, timers, pulses, and message-passing communication. We, then, define equivalent abstractions of the constructs in RESC on top of the SystemC library. We validated our models using industrial-size examples such as MP3 decoder and Vocoder. The experimental results show that our models are very accurate (<; 1% error) and significantly faster (up to 11X) than real-time software execution on target platform.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523643
D. Ghai, S. Mohanty, G. Thakral
The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R2. Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.
{"title":"Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study","authors":"D. Ghai, S. Mohanty, G. Thakral","doi":"10.1109/ISQED.2013.6523643","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523643","url":null,"abstract":"The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R2. Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523596
C. O'Sullivan, P. Levine, S. Garg
We propose a new test array architecture-vertically-addressed test structures (VATS)-to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity. A test chip featuring eight VATS arrays (>15,000 active devices) has been designed and fabricated in a two-tier, 130-nm 3D IC technology. Simulation results highlight the advantages of the proposed VATS architecture compared to conventional 2D test arrays.We also propose a radial filtering scheme to discriminate between process variations and the impact of TSV-induced stress in 3D ICs.
{"title":"Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements","authors":"C. O'Sullivan, P. Levine, S. Garg","doi":"10.1109/ISQED.2013.6523596","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523596","url":null,"abstract":"We propose a new test array architecture-vertically-addressed test structures (VATS)-to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity. A test chip featuring eight VATS arrays (>15,000 active devices) has been designed and fabricated in a two-tier, 130-nm 3D IC technology. Simulation results highlight the advantages of the proposed VATS architecture compared to conventional 2D test arrays.We also propose a radial filtering scheme to discriminate between process variations and the impact of TSV-induced stress in 3D ICs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127187652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523588
Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang
Ternary content addressable memory (TCAM), which can store 0, 1 and X in its cells, is widely used to store routing tables in network routers. Meanwhile, NBTI (Negative Bias Temperature Instability) and PBTI (Positive Biased Temperature Instability), which increase Vth and degrade transistor switching speed, have become major reliability challenges. In this paper, we propose a novel TCAM architecture to reduce BTI degradation using a bit-flipping technique. This novel TCAM architecture ensures the correctness of read, write and search operations. We also analyze the signal probabilities of TCAM cells, and demonstrate that the bit-flipping technique can balance signal probabilities. By using the bit-flipping technique, 76.40% of the data cells under investigation were found to have signal probabilities close to 50%, which is 62.80% higher than the original architecture. In addition, 92.60% of the mask cells had signal probabilities close to 50%, which is 91.20% higher than the original architecture. When considering the overhead of the bit-flipping technique, the best flipping frequency is once a day.
{"title":"Impacts of NBTI and PBTI effects on ternary CAM","authors":"Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang","doi":"10.1109/ISQED.2013.6523588","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523588","url":null,"abstract":"Ternary content addressable memory (TCAM), which can store 0, 1 and X in its cells, is widely used to store routing tables in network routers. Meanwhile, NBTI (Negative Bias Temperature Instability) and PBTI (Positive Biased Temperature Instability), which increase Vth and degrade transistor switching speed, have become major reliability challenges. In this paper, we propose a novel TCAM architecture to reduce BTI degradation using a bit-flipping technique. This novel TCAM architecture ensures the correctness of read, write and search operations. We also analyze the signal probabilities of TCAM cells, and demonstrate that the bit-flipping technique can balance signal probabilities. By using the bit-flipping technique, 76.40% of the data cells under investigation were found to have signal probabilities close to 50%, which is 62.80% higher than the original architecture. In addition, 92.60% of the mask cells had signal probabilities close to 50%, which is 91.20% higher than the original architecture. When considering the overhead of the bit-flipping technique, the best flipping frequency is once a day.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125758334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523628
Chih-han Hsu, S. Ruan, Ying-Jung Chen, Tsang-Chi Kan
Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also cause unexpected performance loss. In this paper, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability is. However, it also implies a larger area. Therefore, we develop a methodology to manipulate thermal-aware floorplan with the tradeoff among the number of STSVs, reliability, and area of a chip. Moreover, we manage our manipulated floorplan with precise thermal model for TTSVs insertion at via channel. Experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, thereby improving reliability. Furthermore, temperature can be maintained around 80°C with minimal TTSVs after inserting TTSVs.
{"title":"Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning","authors":"Chih-han Hsu, S. Ruan, Ying-Jung Chen, Tsang-Chi Kan","doi":"10.1109/ISQED.2013.6523628","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523628","url":null,"abstract":"Vertical integration of layers in a 3D IC exacerbates thermal problem especially for reliability degradation. Low reliability can not only damage the whole circuits but also cause unexpected performance loss. In this paper, we conduct the SA engine with rectangle-STSVs and double-STSVs for improving reliability. The earlier research indicates that the more STSVs a chip has, the better the reliability is. However, it also implies a larger area. Therefore, we develop a methodology to manipulate thermal-aware floorplan with the tradeoff among the number of STSVs, reliability, and area of a chip. Moreover, we manage our manipulated floorplan with precise thermal model for TTSVs insertion at via channel. Experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, thereby improving reliability. Furthermore, temperature can be maintained around 80°C with minimal TTSVs after inserting TTSVs.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523612
Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K. Takeda, M. Takamiya, T. Sakurai
This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSV's) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured using 90nm CMOS technology with TSV's and a silicon interposer. A chip inductor and chip capacitors for the buck converter are mounted directly on the top die. The reduction of the IR drop to less than 1/4 is verified through experiments.
{"title":"Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme","authors":"Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K. Takeda, M. Takamiya, T. Sakurai","doi":"10.1109/ISQED.2013.6523612","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523612","url":null,"abstract":"This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSV's) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured using 90nm CMOS technology with TSV's and a silicon interposer. A chip inductor and chip capacitors for the buck converter are mounted directly on the top die. The reduction of the IR drop to less than 1/4 is verified through experiments.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130809819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523587
J. Wan, H. Kerkhoff
A compact NBTI model is presented by directly solving the reaction-diffusion (RD) equations in a simple way. The new model can handle arbitrary stress conditions without solving time-consuming equations and is hence very suitable for analog/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of aging into account. The simulation speed has increased at least thousands times. The performance of the model is validated by both RD theoretical solutions as well as silicon results.
{"title":"An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations","authors":"J. Wan, H. Kerkhoff","doi":"10.1109/ISQED.2013.6523587","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523587","url":null,"abstract":"A compact NBTI model is presented by directly solving the reaction-diffusion (RD) equations in a simple way. The new model can handle arbitrary stress conditions without solving time-consuming equations and is hence very suitable for analog/mixed-signal NBTI simulations in SPICE-like environments. The model has been implemented in Cadence ADE with Verilog-A and also takes the stochastic effect of aging into account. The simulation speed has increased at least thousands times. The performance of the model is validated by both RD theoretical solutions as well as silicon results.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128959245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523665
Dheepakkumaran Jayaraman, S. Tragoudas
In this paper we present a novel algorithm to identify infeasible paths in the behavioral code. The proposed approach initially partitions the behavioral code into segments. At each code segment it stores feasible paths implicitly. It also stores collections of input assignments which are derived using selected statements in the code segment. The method requires state-of-the-art data structures to store feasible paths and the required functions. Experimental results demonstrate the scalability of the proposed method.
{"title":"Performance validation through implicit removal of infeasible paths of the behavioral description","authors":"Dheepakkumaran Jayaraman, S. Tragoudas","doi":"10.1109/ISQED.2013.6523665","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523665","url":null,"abstract":"In this paper we present a novel algorithm to identify infeasible paths in the behavioral code. The proposed approach initially partitions the behavioral code into segments. At each code segment it stores feasible paths implicitly. It also stores collections of input assignments which are derived using selected statements in the code segment. The method requires state-of-the-art data structures to store feasible paths and the required functions. Experimental results demonstrate the scalability of the proposed method.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123512113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-04DOI: 10.1109/ISQED.2013.6523616
J. Shin, N. Dutt, F. Kurdahi
As we enter the deep submicron era, transistors are increasingly added to chips, causing the chips to become hotter in a non-uniform manner. This is due to different processing tasks in different parts of the chips. This thermal gradient also causes a great number of problems such as the reduction in reliability of chips and interconnects due to electromigration, and system performance degradation because of increased delay and lowered clock frequencies. Since these thermal issues exist, interconnect routing, especially global routing, should be performed to consider the temperature distribution of substrates and the actual delay of interconnects. In this paper, we propose a global routing method based on image processing and computer vision techniques in which the probability of chip failure due to interconnect failure is reduced, and performance degradation from increased delay is also prevented. We observed that our method reduced the number of grids in hot regions by up to 50 % when compared with a conventional router, while maintaining the delay of interconnects as small as possible.
{"title":"Vision-inspired global routing for enhanced performance and reliability","authors":"J. Shin, N. Dutt, F. Kurdahi","doi":"10.1109/ISQED.2013.6523616","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523616","url":null,"abstract":"As we enter the deep submicron era, transistors are increasingly added to chips, causing the chips to become hotter in a non-uniform manner. This is due to different processing tasks in different parts of the chips. This thermal gradient also causes a great number of problems such as the reduction in reliability of chips and interconnects due to electromigration, and system performance degradation because of increased delay and lowered clock frequencies. Since these thermal issues exist, interconnect routing, especially global routing, should be performed to consider the temperature distribution of substrates and the actual delay of interconnects. In this paper, we propose a global routing method based on image processing and computer vision techniques in which the probability of chip failure due to interconnect failure is reduced, and performance degradation from increased delay is also prevented. We observed that our method reduced the number of grids in hot regions by up to 50 % when compared with a conventional router, while maintaining the delay of interconnects as small as possible.","PeriodicalId":127115,"journal":{"name":"International Symposium on Quality Electronic Design (ISQED)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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