Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159801
Mahin Esmaeilzadeh, Mohamed Ali, Ahmad Hassan, Y. Audet, M. Sawan
This paper presents a low-power large-bandwidth time-domain comparator. The proposed structure is constructed by two voltage-controlled oscillators (VCO) with enhanced linearity and a proposed glitch free and dead-zone free phase frequency detector (PFD). This novel VCO-based comparator is intended for monitoring and readout circuits in industrial sensor interfaces. The presented comparator has been implemented in a $0.35 mu m$ standard CMOS process under $3.3 V$ supply voltage. This high accuracy comparator achieves $50 mu V$ resolution and is able to operate at a frequency up to 400 MHz. The average power consumption of proposed design is $50.1 mu W$, while occupying a silicon area of $0.004 mm^{2}$.
提出了一种低功耗大带宽时域比较器。该结构由两个具有增强线性度的压控振荡器(VCO)和一个无故障和无死区相位频率检测器(PFD)组成。这种新颖的基于vco的比较器用于工业传感器接口中的监控和读出电路。该比较器在3.3 V电源电压下，采用0.35 μ m标准CMOS工艺实现。这种高精度比较器达到$50 mu V$的分辨率，并且能够在高达400mhz的频率下工作。所提设计的平均功耗为$50.1 mu W$，而占用的硅面积为$0.004 mm^{2}$。
{"title":"Low-Power High-Accuracy VCO-Based Comparator for Sensor Interface Applications","authors":"Mahin Esmaeilzadeh, Mohamed Ali, Ahmad Hassan, Y. Audet, M. Sawan","doi":"10.1109/newcas49341.2020.9159801","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159801","url":null,"abstract":"This paper presents a low-power large-bandwidth time-domain comparator. The proposed structure is constructed by two voltage-controlled oscillators (VCO) with enhanced linearity and a proposed glitch free and dead-zone free phase frequency detector (PFD). This novel VCO-based comparator is intended for monitoring and readout circuits in industrial sensor interfaces. The presented comparator has been implemented in a $0.35 mu m$ standard CMOS process under $3.3 V$ supply voltage. This high accuracy comparator achieves $50 mu V$ resolution and is able to operate at a frequency up to 400 MHz. The average power consumption of proposed design is $50.1 mu W$, while occupying a silicon area of $0.004 mm^{2}$.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159841
Issa Alaji, T. C. Mouvand, Mohamad El-Chaar, A. A. L. Souza, F. Podevin, S. Bourdel
In the framework of circuits for 5G, this paper presents an innovative power efficient method to design cascaded distributed amplifiers. Validation is achieved with a 55-nm CMOS technology by ST -Microelectronics developed for the mm-wave range. Several rules are specified for analysis and design of an optimum structure, making the part between the number of trans conductances to be distributed and the number of distributed stages to be cascaded. Attention is also paid to the trade-off between power consumption and tunability. The Cadence Virtuoso tool is used to simulate the design which shows a targeted gain of 20 dB±0.8 dB over a bandwidth of 120 GHz with a power consumption of 174mW and an estimated area of 0.3 mm2.
{"title":"Cascaded tunable distributed amplifiers for serial optical links: Some design rules","authors":"Issa Alaji, T. C. Mouvand, Mohamad El-Chaar, A. A. L. Souza, F. Podevin, S. Bourdel","doi":"10.1109/newcas49341.2020.9159841","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159841","url":null,"abstract":"In the framework of circuits for 5G, this paper presents an innovative power efficient method to design cascaded distributed amplifiers. Validation is achieved with a 55-nm CMOS technology by ST -Microelectronics developed for the mm-wave range. Several rules are specified for analysis and design of an optimum structure, making the part between the number of trans conductances to be distributed and the number of distributed stages to be cascaded. Attention is also paid to the trade-off between power consumption and tunability. The Cadence Virtuoso tool is used to simulate the design which shows a targeted gain of 20 dB±0.8 dB over a bandwidth of 120 GHz with a power consumption of 174mW and an estimated area of 0.3 mm2.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114089297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159800
A. Ginés, G. Léger, E. Peralías
This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT -based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.
{"title":"Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL","authors":"A. Ginés, G. Léger, E. Peralías","doi":"10.1109/newcas49341.2020.9159800","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159800","url":null,"abstract":"This paper presents a digital non-linear calibration technique for Pipeline ADCs using a novel Look-up Table (LUT) approach. Due to redundancy, the signal paths (and hence, the errors in Pipeline ADCs) are not unique for a given input level. This effect limits the performance of conventional LUT -based calibration methods using the output code of the ADC as single address in the error code LUT memory. To overcome this drawback, this work uses an estimation of true redundant INL (Integral Non-Linearity), based on the standardized histogram method. The technique resolves the presence of multiple error codes for a single input level incorporating the most significant redundant subcodes in the memory address. The advantages of the method are shown by realistic behavioral simulations and by a 0.8Vpp 11-bit 60Msps Pipeline ADC silicon demonstrator in a 130nm CMOS process.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131389576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159760
H. Sadreazami, Dipayan Mitra, M. Bolic, S. Rajan
Falling down is one of the main reasons for hospitalization among the elderly. Constant monitoring of such vulnerable older adults and timely detection of fall incidents may significantly improve healthcare services. This paper presents a radar-based fall detection method using compressed features of the radar signals. The compressed features are obtained by using determinisitc row and column sensing. The time-frequency analysis is first performed on the radar time series and resulting spectrogram is projected onto a binary image representation. The binary images are then compressed using a 2D deterministic sensing technique by preserving the aspect ratio of the images in the compressed domain. The performance of the proposed method is evaluated using several classifiers such as support vector machine, nearest neighbors, linear discriminant analysis and decision tree. It is shown that the proposed compressive sensing based method can improve fall versus non-fall activities recognition, as evidenced by high classification metrics for low compression ratios.
{"title":"Compressed Domain Contactless Fall Incident Detection using UWB Radar Signals","authors":"H. Sadreazami, Dipayan Mitra, M. Bolic, S. Rajan","doi":"10.1109/newcas49341.2020.9159760","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159760","url":null,"abstract":"Falling down is one of the main reasons for hospitalization among the elderly. Constant monitoring of such vulnerable older adults and timely detection of fall incidents may significantly improve healthcare services. This paper presents a radar-based fall detection method using compressed features of the radar signals. The compressed features are obtained by using determinisitc row and column sensing. The time-frequency analysis is first performed on the radar time series and resulting spectrogram is projected onto a binary image representation. The binary images are then compressed using a 2D deterministic sensing technique by preserving the aspect ratio of the images in the compressed domain. The performance of the proposed method is evaluated using several classifiers such as support vector machine, nearest neighbors, linear discriminant analysis and decision tree. It is shown that the proposed compressive sensing based method can improve fall versus non-fall activities recognition, as evidenced by high classification metrics for low compression ratios.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134538314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159816
Laryssa L. O. Costa, José E. G. Medeiros, J. A. A. D. Andrade, S. Haddad
This paper presents a nonlinear quantization technique applied in a multibit sigma-delta $Sigmatriangle$ modulator. The technique is based on the unscented transform and utilizes a flash topology to modeling the quantizer of the modulator. To verify the proposed methodology a 4-bit, first-order and second-order $Sigmatriangle$ modulators were modeled and simulated. Simulation results confirm the validity of the technique and in this case has been shown that significant improvements can be achieved on SINAD compared with the linear multibit modulators.
{"title":"Nonlinear Quantization Technique for Multibit Sigma-Delta Modulators","authors":"Laryssa L. O. Costa, José E. G. Medeiros, J. A. A. D. Andrade, S. Haddad","doi":"10.1109/newcas49341.2020.9159816","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159816","url":null,"abstract":"This paper presents a nonlinear quantization technique applied in a multibit sigma-delta $Sigmatriangle$ modulator. The technique is based on the unscented transform and utilizes a flash topology to modeling the quantizer of the modulator. To verify the proposed methodology a 4-bit, first-order and second-order $Sigmatriangle$ modulators were modeled and simulated. Simulation results confirm the validity of the technique and in this case has been shown that significant improvements can be achieved on SINAD compared with the linear multibit modulators.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133658029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159827
M. Roudjane, M. Khalil, Hajer Abed, A. Miled, Y. Messaddeq
In the near future wearable sensors when integrated into garments will have a significant impact on the future of digital health care. A new wireless T-shirt based on non-invasive network sensors was developed and tested recently as a scanner for real time breath detection of mainly male gender volunteers. The sensor is made of flexible glass fiber antenna emitting at 2.45 GHz and connected to a Bluetooth transmitter. The scanner is a network of six sensors integrated into a stretchable textile and placed in a well defined position on the thorax and on the abdomen. The breathing signal is extracted from the received signal strength indicator (RSSI) signal emitted from the sensors array and detected by a base station. In this work, we tested the feasibility assessment for breath monitoring of five female gender volunteers of different age and physical morphology in standing positions using the designed male-shape T-shirt. As a result, the wearable scanner detected successfully the breathing rates of the female volunteers with a frequency varying from 0.27 Hz to 0.40 Hz.
{"title":"Wearable Scanner Platform Based on Fiber Sensor Array for Real Time Breath Detection","authors":"M. Roudjane, M. Khalil, Hajer Abed, A. Miled, Y. Messaddeq","doi":"10.1109/newcas49341.2020.9159827","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159827","url":null,"abstract":"In the near future wearable sensors when integrated into garments will have a significant impact on the future of digital health care. A new wireless T-shirt based on non-invasive network sensors was developed and tested recently as a scanner for real time breath detection of mainly male gender volunteers. The sensor is made of flexible glass fiber antenna emitting at 2.45 GHz and connected to a Bluetooth transmitter. The scanner is a network of six sensors integrated into a stretchable textile and placed in a well defined position on the thorax and on the abdomen. The breathing signal is extracted from the received signal strength indicator (RSSI) signal emitted from the sensors array and detected by a base station. In this work, we tested the feasibility assessment for breath monitoring of five female gender volunteers of different age and physical morphology in standing positions using the designed male-shape T-shirt. As a result, the wearable scanner detected successfully the breathing rates of the female volunteers with a frequency varying from 0.27 Hz to 0.40 Hz.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159773
Pei Yang, W. Mao, Jun Lin, Zhongfeng Wang
Nowadays, Generative Adversarial Network (GAN) has been developed rapidly and has found variety of applications. Convolutional (CONV) and deconvolutional (DeCONV) layers are typical components of GANs. There existe a few researches on acceleration of deconvolution implementations. However, the previous works on accelerating DeCONV layers generally incur several issues, such as resource under-utilization, large memory requirements, and complex data access. In this paper, we propose an efficient method, namely fast transformation algorithm, to accelerate DeCONV layers. The algorithm improves the computational efficiency significantly and solves the problems of resource under-utilization and large memory requirements. Based on the algorithm, a reconfigurable computing core (RCC) for GANs is developed, which can support both convolutions and deconvolutions. Additionally, a reconfigurable architecture based on RCC is proposed to support both CONV and DeCONV layers. Moreover, a typical generative neural network, CycleGAN, is used to verify our design. The experimental results show that our design, when performing deconvolutions and convolutions in CycleGAN, can reach 352.50 GOPS under 200MHz working frequency on Intel Arria 10SX. In brief, the proposed design outperforms existing works significantly, particularly in terms of hardware efficiency.
{"title":"A Computation-Efficient Solution for Acceleration of Generative Adversarial Network","authors":"Pei Yang, W. Mao, Jun Lin, Zhongfeng Wang","doi":"10.1109/newcas49341.2020.9159773","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159773","url":null,"abstract":"Nowadays, Generative Adversarial Network (GAN) has been developed rapidly and has found variety of applications. Convolutional (CONV) and deconvolutional (DeCONV) layers are typical components of GANs. There existe a few researches on acceleration of deconvolution implementations. However, the previous works on accelerating DeCONV layers generally incur several issues, such as resource under-utilization, large memory requirements, and complex data access. In this paper, we propose an efficient method, namely fast transformation algorithm, to accelerate DeCONV layers. The algorithm improves the computational efficiency significantly and solves the problems of resource under-utilization and large memory requirements. Based on the algorithm, a reconfigurable computing core (RCC) for GANs is developed, which can support both convolutions and deconvolutions. Additionally, a reconfigurable architecture based on RCC is proposed to support both CONV and DeCONV layers. Moreover, a typical generative neural network, CycleGAN, is used to verify our design. The experimental results show that our design, when performing deconvolutions and convolutions in CycleGAN, can reach 352.50 GOPS under 200MHz working frequency on Intel Arria 10SX. In brief, the proposed design outperforms existing works significantly, particularly in terms of hardware efficiency.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159819
Mathieu Hugoud, W. Uhring, J. Kammerer, J. Schell
The burst imaging concept is a specific imaging method than allows achieving a pixel rate of about 1 Tera pixel per second. This huge data rate can be reached by storing the video frames within the sensor, thus circumventing the bottleneck of the input/output of the sensor. Consequently, a frame rate of several Mega frames per second (Mfps) can be obtained and the use of a fast pixel front end is mandatory. In this paper, a pixel front able to operate at a frame rate of 100 Mfps is proposed. Based on a current mirroring integration approach, it offers a high dynamic range feature compatible with the record of the very fast moving object without blurring effect. The feature is carried out by mirroring in parallel the photocurrent into several integration capacitances. The pixel consumption is as low as 12 μW for one single gain branch at 10 Mfps and 118μW at a frame rate of 100 Mpfs.
{"title":"A High Dynamic Range High Speed Pixel Operating at 100 Million Frames Per Second","authors":"Mathieu Hugoud, W. Uhring, J. Kammerer, J. Schell","doi":"10.1109/newcas49341.2020.9159819","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159819","url":null,"abstract":"The burst imaging concept is a specific imaging method than allows achieving a pixel rate of about 1 Tera pixel per second. This huge data rate can be reached by storing the video frames within the sensor, thus circumventing the bottleneck of the input/output of the sensor. Consequently, a frame rate of several Mega frames per second (Mfps) can be obtained and the use of a fast pixel front end is mandatory. In this paper, a pixel front able to operate at a frame rate of 100 Mfps is proposed. Based on a current mirroring integration approach, it offers a high dynamic range feature compatible with the record of the very fast moving object without blurring effect. The feature is carried out by mirroring in parallel the photocurrent into several integration capacitances. The pixel consumption is as low as 12 μW for one single gain branch at 10 Mfps and 118μW at a frame rate of 100 Mpfs.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124261036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/newcas49341.2020.9159791
Vitor V. Bandeira, Mateus Fogaça, E. Monteiro, Isadora Oliveira, M. Woo, R. Reis
I/O pin assignment is a crucial task in the floorplanning stage of IC implementation. However, this task has not received much attention in the physical design automation literature. Notably, floorplanning is a highly manual stage of the design flow. Nevertheless, it is known that the impact of I/O pin assignment in total routed wirelength (WL) is in the order of 5%. In advanced nodes, density, power and timing become very crucial and WL impacts of 5% are highly significant. We are therefore motivated to revisit the I/O pin assignment problem in this work. We present a fast and scalable Hungarian matching-based heuristic for I/O pin assignment. We present background scalability studies and a divide-and-conquer strategy that significantly reduces runtime without harm to the quality of results. Our algorithm converges in fewer iterations than previous works and presents superior performance according to criteria from the literature.
{"title":"Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching","authors":"Vitor V. Bandeira, Mateus Fogaça, E. Monteiro, Isadora Oliveira, M. Woo, R. Reis","doi":"10.1109/newcas49341.2020.9159791","DOIUrl":"https://doi.org/10.1109/newcas49341.2020.9159791","url":null,"abstract":"I/O pin assignment is a crucial task in the floorplanning stage of IC implementation. However, this task has not received much attention in the physical design automation literature. Notably, floorplanning is a highly manual stage of the design flow. Nevertheless, it is known that the impact of I/O pin assignment in total routed wirelength (WL) is in the order of 5%. In advanced nodes, density, power and timing become very crucial and WL impacts of 5% are highly significant. We are therefore motivated to revisit the I/O pin assignment problem in this work. We present a fast and scalable Hungarian matching-based heuristic for I/O pin assignment. We present background scalability studies and a divide-and-conquer strategy that significantly reduces runtime without harm to the quality of results. Our algorithm converges in fewer iterations than previous works and presents superior performance according to criteria from the literature.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123613795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NEWCAS49341.2020.9159759
E. Bharucha, B. Gosselin, F. Lellouche
This paper describes a new patch oximeter architecture that automatically selects the best sampling site within a patch array of sensors. This array allows for non-obtrusive chronic care. Sensor triads composed of 2 emitters and a photoreceptor are laid out on a surface that, with the aid of a microcontroller, automatically selects the best signal amplitude domain available on the skin. The data is slated for use with oxygen therapy and ventilators. We show, not only that we can extract pulse, oximetric data with clinical value, but also improved longevity of such devices, making the design practical in a variety of clinical settings.
{"title":"A Long-Lifetime, Low-Cost Self-Tuning Patch Oximeter for Ventilation Therapy","authors":"E. Bharucha, B. Gosselin, F. Lellouche","doi":"10.1109/NEWCAS49341.2020.9159759","DOIUrl":"https://doi.org/10.1109/NEWCAS49341.2020.9159759","url":null,"abstract":"This paper describes a new patch oximeter architecture that automatically selects the best sampling site within a patch array of sensors. This array allows for non-obtrusive chronic care. Sensor triads composed of 2 emitters and a photoreceptor are laid out on a surface that, with the aid of a microcontroller, automatically selects the best signal amplitude domain available on the skin. The data is slated for use with oxygen therapy and ventilators. We show, not only that we can extract pulse, oximetric data with clinical value, but also improved longevity of such devices, making the design practical in a variety of clinical settings.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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