Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380745
M. Hussin, N. A. Rashid, R. Keating
This paper describes the effect of Ti deposition/anneal and supplementary BF2 implant/anneal on a 0.35 mum silicon CMOS process using contact silicided P+ source- drain. Thicker Ti and higher Ti/TiN annealing temperature are also required for the smaller contact sizes to get adequate P+ contact resistance. The supplementary BF2 implant with dose of 3E14 cm-2 and energy 20KeV helped to reduce and stabilize the contact resistance down to 150 Ohm/hole for the 0.4 mum P+ contact. The Boron profile at the TiSi2/p+ interface were investigated by 2D ATHENA process simulation. The peak Boron doping level at TiSi2/p+ interface significantly influenced the contact resistivity. Various contact chain test structures, with different contact sizes, plus single Kelvin structures were used in this investigation.
本文介绍了Ti沉积/退火和补充BF2植入/退火对接触硅化P+源漏0.35 μ m硅CMOS工艺的影响。为了获得足够的P+接触电阻，还需要更厚的Ti和更高的Ti/TiN退火温度。补充BF2植入物的剂量为3E14 cm-2，能量为20KeV，有助于降低和稳定0.4 μ m P+接触电阻至150欧姆/孔。采用二维ATHENA工艺模拟研究了TiSi2/p+界面硼的分布。TiSi2/p+界面处硼掺杂峰值对接触电阻率有显著影响。本研究采用了不同接触尺寸的接触链测试结构和单开尔文结构。
{"title":"Effects of High Dose BF2+ Implant on the Improvement of P+ Contact Resistance","authors":"M. Hussin, N. A. Rashid, R. Keating","doi":"10.1109/SMELEC.2006.380745","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380745","url":null,"abstract":"This paper describes the effect of Ti deposition/anneal and supplementary BF2 implant/anneal on a 0.35 mum silicon CMOS process using contact silicided P+ source- drain. Thicker Ti and higher Ti/TiN annealing temperature are also required for the smaller contact sizes to get adequate P+ contact resistance. The supplementary BF2 implant with dose of 3E14 cm-2 and energy 20KeV helped to reduce and stabilize the contact resistance down to 150 Ohm/hole for the 0.4 mum P+ contact. The Boron profile at the TiSi2/p+ interface were investigated by 2D ATHENA process simulation. The peak Boron doping level at TiSi2/p+ interface significantly influenced the contact resistivity. Various contact chain test structures, with different contact sizes, plus single Kelvin structures were used in this investigation.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380751
C. Senthilpari, K. Diwakar, C. Prabhu
The proposed 4 bit subtracter circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520 MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50 nm analysis, the proposed circuit is found to dissipate less power (~0.46 muW) and possess less overall area of order of 423 mum2. The propagation delay is 9.5206 times 10-12 sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.
采用互补通型晶体管逻辑(CPL)的位片方法设计了4位减法电路，适用于快速移位等应用;DSP数据处理装置环路中的乘法器/加法器。该电路可以高速执行实时计算任务。所设计的电路能有效地实时滤波100- 520mhz采样率的信号。利用microwind III VLSI CAD工具设计的亚微米区域电路，从传播延迟、功耗、功耗和面积等方面进行了分析。在50 nm的分析中，发现该电路的功耗更低(~0.46 muW)，总面积更小，约为423 mum2。在DSP体系结构中，时间和面积是保证算术和逻辑运算高效执行的关键因素。我们提出的电路是增强的，完整的指令周期，通过9.0 GHz的速度，高于报告的结果。
{"title":"Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit","authors":"C. Senthilpari, K. Diwakar, C. Prabhu","doi":"10.1109/SMELEC.2006.380751","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380751","url":null,"abstract":"The proposed 4 bit subtracter circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520 MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50 nm analysis, the proposed circuit is found to dissipate less power (~0.46 muW) and possess less overall area of order of 423 mum2. The propagation delay is 9.5206 times 10-12 sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114815372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381025
T. Aziz, M. Salleh, M. Umar, M. Yahaya
Polymer light-emitting diode with ITO/PHF/Al structure has been fabricated, where PHF is poly (4,4'-diphenylene diphenylvinylene). The original device has turn-on voltage at 18.0 V. A reduction of turn-on voltage of this device is achieved by using the nanocomposites layer consisting of PHF and SiO2 nanoparticles as an emitting layer in a single structured ITO/nanocomposite/Al polymer light emitting diode. The SiO2: PHF was prepared by mixing 1.0 ml of PHF with 0.05 ml of SiO2 colloidal solution. It was found that the spin-coated nanocomposites has reduced the OLED turn-on voltage to 9.0 V.
制备了ITO/PHF/Al结构的聚合物发光二极管，其中PHF为聚(4,4′-二苯基乙烯)。原始设备的导通电压为18.0 V。在单结构ITO/纳米复合材料/Al聚合物发光二极管中，采用由PHF和SiO2纳米颗粒组成的纳米复合材料层作为发射层，实现了器件导通电压的降低。将1.0 ml PHF与0.05 ml SiO2胶体溶液混合制备SiO2: PHF。结果表明，自旋涂层纳米复合材料使OLED的导通电压降至9.0 V。
{"title":"Reduction of Turn-On Voltage in a Single Layer Structured Organic Light-Emitting Diode using Nanocomposites SiO2:PHF","authors":"T. Aziz, M. Salleh, M. Umar, M. Yahaya","doi":"10.1109/SMELEC.2006.381025","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381025","url":null,"abstract":"Polymer light-emitting diode with ITO/PHF/Al structure has been fabricated, where PHF is poly (4,4'-diphenylene diphenylvinylene). The original device has turn-on voltage at 18.0 V. A reduction of turn-on voltage of this device is achieved by using the nanocomposites layer consisting of PHF and SiO2 nanoparticles as an emitting layer in a single structured ITO/nanocomposite/Al polymer light emitting diode. The SiO2: PHF was prepared by mixing 1.0 ml of PHF with 0.05 ml of SiO2 colloidal solution. It was found that the spin-coated nanocomposites has reduced the OLED turn-on voltage to 9.0 V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380701
D. K. Pal, K. Sabri, M.T.L. Kee, Song Jin Yeong, Park Hyun Suck
A process has been developed to cover wide range I/O operation voltage (1.8V to 3.3V) without changing the 3.3V I/O library at author's organization to meet the market demand by optimization of 3.3V process. The main emphasis is given on to improve the Idsat current from the baseline and maintain the Ioff comparable as 3.3V process. This process passed all device level reliability test. This process is used to fabricate wide range I/O operation voltage device at author's organization.
{"title":"I/O Process Optimization to Cover Wide Range Operation Voltage","authors":"D. K. Pal, K. Sabri, M.T.L. Kee, Song Jin Yeong, Park Hyun Suck","doi":"10.1109/SMELEC.2006.380701","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380701","url":null,"abstract":"A process has been developed to cover wide range I/O operation voltage (1.8V to 3.3V) without changing the 3.3V I/O library at author's organization to meet the market demand by optimization of 3.3V process. The main emphasis is given on to improve the Idsat current from the baseline and maintain the Ioff comparable as 3.3V process. This process passed all device level reliability test. This process is used to fabricate wide range I/O operation voltage device at author's organization.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123993424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381034
M. K. Othman, M. M. Salleh, A. Mat
This paper reports the various structures and performances improvements using different hole transporting layer in OLED based on DPVBi as emitter. Here the indium tin oxide (ITO) used as an anode, copper pthalocyanine (CuPc) as the hole injecting layer, PEDOT:PSS and poly-9- vinylcarbozole (PVK) as hole transporting layer, 4,4'-bis(2,2'diphenilvinyl)-1,1' -biphenyl (DPVBi) as the blue emitting layer and aluminum (Al) as the cathode. The CuPc and DPVBi were prepared by thermal evaporation while the PEDOT:PSS and PVK films were prepared using spin coating technique. The effect of inserting additional layer of CuPc, PVK and PEDOT:PSS between anode and the emitting layers was analyzed through the current-voltage (IV) curves and the electroluminescence spectra. The additional layer structure was found to increase the maximum luminance compared to that one of single layer device. The used of PVK as hole transporting layer has improved the diode properties of the device and able to prevent the device from short circuits. The optimized DPVBi layer thickness was observed at 56 nm and the insertion of 10 nm CuPc hole injecting layer show the device reduce it turn on voltage from 7.0 V to 6.5 V.
{"title":"Organic Light Emitting Diode (OLED) Using Different Hole Transport and Injecting Layers","authors":"M. K. Othman, M. M. Salleh, A. Mat","doi":"10.1109/SMELEC.2006.381034","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381034","url":null,"abstract":"This paper reports the various structures and performances improvements using different hole transporting layer in OLED based on DPVBi as emitter. Here the indium tin oxide (ITO) used as an anode, copper pthalocyanine (CuPc) as the hole injecting layer, PEDOT:PSS and poly-9- vinylcarbozole (PVK) as hole transporting layer, 4,4'-bis(2,2'diphenilvinyl)-1,1' -biphenyl (DPVBi) as the blue emitting layer and aluminum (Al) as the cathode. The CuPc and DPVBi were prepared by thermal evaporation while the PEDOT:PSS and PVK films were prepared using spin coating technique. The effect of inserting additional layer of CuPc, PVK and PEDOT:PSS between anode and the emitting layers was analyzed through the current-voltage (IV) curves and the electroluminescence spectra. The additional layer structure was found to increase the maximum luminance compared to that one of single layer device. The used of PVK as hole transporting layer has improved the diode properties of the device and able to prevent the device from short circuits. The optimized DPVBi layer thickness was observed at 56 nm and the insertion of 10 nm CuPc hole injecting layer show the device reduce it turn on voltage from 7.0 V to 6.5 V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381104
S. Aljunid, F. Hasson, M.D.A. Samad, M. Abdullah, M. Othman, S. Shaari
A new detection scheme, namely AND subtraction technique is proposed and presented in this paper. The theory is being elaborated and experimental results have been done by comparing double-weight (DW) code against the existing code, Hadamard. In this paper we have proved that AND subtraction technique gives better bit error rates (BER) performance than Complementary subtraction technique against the received power level.
{"title":"Performance of OCDMA Systems Using AND Subtraction Technique","authors":"S. Aljunid, F. Hasson, M.D.A. Samad, M. Abdullah, M. Othman, S. Shaari","doi":"10.1109/SMELEC.2006.381104","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381104","url":null,"abstract":"A new detection scheme, namely AND subtraction technique is proposed and presented in this paper. The theory is being elaborated and experimental results have been done by comparing double-weight (DW) code against the existing code, Hadamard. In this paper we have proved that AND subtraction technique gives better bit error rates (BER) performance than Complementary subtraction technique against the received power level.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380723
S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao
Silicon-on-insulator (SOI) is a sandwich structure consisting of a thin insulating layer, such as silicon dioxide or glass sandwiching between a thin layer of silicon (T-Si) and the silicon substrate. The incorporation of the insulating layer between the T-Si and the silicon substrate has greatly changed the front-end process of microelectronic devices and thus the approach of failure analysis would be different compared to that of bulk technology. In this paper, approaches to analyze the single bit failure and pair bit failure in memory failure of SOI wafers would be presented.
{"title":"Failure Analysis Approach in Memory Failure of SOI Devices","authors":"S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao","doi":"10.1109/SMELEC.2006.380723","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380723","url":null,"abstract":"Silicon-on-insulator (SOI) is a sandwich structure consisting of a thin insulating layer, such as silicon dioxide or glass sandwiching between a thin layer of silicon (T-Si) and the silicon substrate. The incorporation of the insulating layer between the T-Si and the silicon substrate has greatly changed the front-end process of microelectronic devices and thus the approach of failure analysis would be different compared to that of bulk technology. In this paper, approaches to analyze the single bit failure and pair bit failure in memory failure of SOI wafers would be presented.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129315645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381029
J. Johari, B. Majlis
This paper presents a general approach to the problem of modeling diaphragm micropumps. This study utilized the finite element method to optimize the deflection of a bilaminar circular plate which consist of a single piezoelectric disc as an actuator and bonded to an elastic diaphragm of certain dimensions. Optimum actuator dimensions were fixed for a determined diaphragm dimensions.
{"title":"Analysis of a Bilaminar Circular Piezoelectric Actuator for Micropumps","authors":"J. Johari, B. Majlis","doi":"10.1109/SMELEC.2006.381029","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381029","url":null,"abstract":"This paper presents a general approach to the problem of modeling diaphragm micropumps. This study utilized the finite element method to optimize the deflection of a bilaminar circular plate which consist of a single piezoelectric disc as an actuator and bonded to an elastic diaphragm of certain dimensions. Optimum actuator dimensions were fixed for a determined diaphragm dimensions.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124526373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380779
Y. Ali, A. Narsale, O. Sidek, A. R. Damle, B. Arora
Single crystal n-GaAs substrates have been implanted at room temperature with 100 MeV 28Si ions to a dose of 1times1018 ions/m2. The electrical behaviour of these samples has been investigated after implantation and annealing to 850degC by current voltage (I-V) measurements. The I-V curves show series of complex behaviours with annealing treatments. To understand this complex behaviour, Resistance measurements of these samples using I-V measurements were carried out in the temperature range 100-300 K, which indicate that the as implanted sample and samples annealed to 350degC are dominated by a variable range hoping conduction mechanism, where as for the samples annealed at 450degC and 550degC the electrical conduction is due to hopping between the neighboring defect sites. The electrical transport for the sample annealed at 650degC seems to be dominated by carriers in the extended states. At annealing temperature higher than 650degC, the I-V characteristics are insensitive to measurement temperatures which indicates that the backward diode like structure after 850degC annealing is due to the activation of Si ions and formation of n+ region at the mean ion range and the existence of defect complex p+-type conductivity immediately above that region.
{"title":"Electrical Characteristics of 100 MeV 28Si implantation in GaAs","authors":"Y. Ali, A. Narsale, O. Sidek, A. R. Damle, B. Arora","doi":"10.1109/SMELEC.2006.380779","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380779","url":null,"abstract":"Single crystal n-GaAs substrates have been implanted at room temperature with 100 MeV 28Si ions to a dose of 1times1018 ions/m2. The electrical behaviour of these samples has been investigated after implantation and annealing to 850degC by current voltage (I-V) measurements. The I-V curves show series of complex behaviours with annealing treatments. To understand this complex behaviour, Resistance measurements of these samples using I-V measurements were carried out in the temperature range 100-300 K, which indicate that the as implanted sample and samples annealed to 350degC are dominated by a variable range hoping conduction mechanism, where as for the samples annealed at 450degC and 550degC the electrical conduction is due to hopping between the neighboring defect sites. The electrical transport for the sample annealed at 650degC seems to be dominated by carriers in the extended states. At annealing temperature higher than 650degC, the I-V characteristics are insensitive to measurement temperatures which indicates that the backward diode like structure after 850degC annealing is due to the activation of Si ions and formation of n+ region at the mean ion range and the existence of defect complex p+-type conductivity immediately above that region.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125012444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381084
M.S.K. Anuar, A. M. Sharizal, S. Mitani, Y. M. Razman, A. Mat, P. Choudhury
The paper deals with the development of Ni/Au/Ge/Au ohmic contacts for the fabrication of VCSELs to be operated in the 980 nm of the electromagnetic (EM) spectrum. The VCSEL structures are grown by the process of molecular beam epitaxy (MBE) whereas the contacts are deposited by electron beam evaporator. The n-contact metallization has been performed along with RTA before as well as after the fabrication of the VCSEL structure, and the effect of RTA treatment on the grown VCSEL has been studied in the different cases.
{"title":"Effect of Rapid Thermal Annealing (RTA) on n-Contact of 980 nm Oxide VCSEL","authors":"M.S.K. Anuar, A. M. Sharizal, S. Mitani, Y. M. Razman, A. Mat, P. Choudhury","doi":"10.1109/SMELEC.2006.381084","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381084","url":null,"abstract":"The paper deals with the development of Ni/Au/Ge/Au ohmic contacts for the fabrication of VCSELs to be operated in the 980 nm of the electromagnetic (EM) spectrum. The VCSEL structures are grown by the process of molecular beam epitaxy (MBE) whereas the contacts are deposited by electron beam evaporator. The n-contact metallization has been performed along with RTA before as well as after the fabrication of the VCSEL structure, and the effect of RTA treatment on the grown VCSEL has been studied in the different cases.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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