Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381060
M.S. Selamat, B. Majlis
Operating a library involves in keeping track large number of resources such as books and magazines. Radio Frequency Identification (RFID) technology has been promoted in recent years as an alternative technology in improving asset management in a library. The RFID tags were applied to replace bar code and magnetic stripe functions as identification and anti-theft detection. This paper is written based on an actual implementation of RFID tagging system in a library one of local university in Malaysia. It focuses on three main challenges during the implementation which relates to system integration, parallel operation with existing system, and procedure changes. In conclusion, implementing RFID tag in a library faced many challenges; however the library could harness the technology advantages in improving its operation.
{"title":"Challenges in Implementing RFID Tag in a Conventional Library","authors":"M.S. Selamat, B. Majlis","doi":"10.1109/SMELEC.2006.381060","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381060","url":null,"abstract":"Operating a library involves in keeping track large number of resources such as books and magazines. Radio Frequency Identification (RFID) technology has been promoted in recent years as an alternative technology in improving asset management in a library. The RFID tags were applied to replace bar code and magnetic stripe functions as identification and anti-theft detection. This paper is written based on an actual implementation of RFID tagging system in a library one of local university in Malaysia. It focuses on three main challenges during the implementation which relates to system integration, parallel operation with existing system, and procedure changes. In conclusion, implementing RFID tag in a library faced many challenges; however the library could harness the technology advantages in improving its operation.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380791
A. El-Abd, M. Aziz, A.A. Shalby, S. Khamis
Most theoretical I-V models appeared in the literature for AlGaN/GaN HEMTs fail to exactly fit the experimental data and a large deviation is reported, especially at large gate bias. Because the exact nature of the AlGaN/GaN hetrostructure is not fully described, we assume that there is a new phenomena in the device which causes this deviation. Here we compute this phenomena mathematically for doped and undoped devices using a new method. The model results will be useful in CAD programs to extract more accurate I-V characteristics for the AlGaN/GaN hetrostructure on sapphire substrate.
{"title":"New I-V Model For AlGaN/GaN HEMT At Large Gate Bias","authors":"A. El-Abd, M. Aziz, A.A. Shalby, S. Khamis","doi":"10.1109/SMELEC.2006.380791","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380791","url":null,"abstract":"Most theoretical I-V models appeared in the literature for AlGaN/GaN HEMTs fail to exactly fit the experimental data and a large deviation is reported, especially at large gate bias. Because the exact nature of the AlGaN/GaN hetrostructure is not fully described, we assume that there is a new phenomena in the device which causes this deviation. Here we compute this phenomena mathematically for doped and undoped devices using a new method. The model results will be useful in CAD programs to extract more accurate I-V characteristics for the AlGaN/GaN hetrostructure on sapphire substrate.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381046
N. H. Yusoff, M.M. Salleha, M. Yahaya, M. Awang
This paper explores the possibility using nanostructure thin film of TiO2 nanoparticles coated with porphyrin dye based on fluorescence technique to grade agarwood oil. The sensing material was prepared using synthesized of TiO2 nanoparticles colloid is in a sol-gel form. Then the nanoparticles were coated with dye, Iron (III) meso tetraphenyl porphine chloride. The coated nanoparticles were deposited on quartz substrate using self- assembly through dip coating technique. The sensing properties of the thin film toward five grades of agarwood oil were studied using luminescence spectrometer. It was found that the thin film produced different emission spectra peaks for different grades of agarwood oil. Hence the thin film potentially be use as sensing material for grading agarwood oil and others nature product for the future.
{"title":"The Use of Photoluminescence Spectra of TiO2 Nanoparticles Coated With Porphyrin Dye Thin Film for Grading Agarwood Oil","authors":"N. H. Yusoff, M.M. Salleha, M. Yahaya, M. Awang","doi":"10.1109/SMELEC.2006.381046","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381046","url":null,"abstract":"This paper explores the possibility using nanostructure thin film of TiO2 nanoparticles coated with porphyrin dye based on fluorescence technique to grade agarwood oil. The sensing material was prepared using synthesized of TiO2 nanoparticles colloid is in a sol-gel form. Then the nanoparticles were coated with dye, Iron (III) meso tetraphenyl porphine chloride. The coated nanoparticles were deposited on quartz substrate using self- assembly through dip coating technique. The sensing properties of the thin film toward five grades of agarwood oil were studied using luminescence spectrometer. It was found that the thin film produced different emission spectra peaks for different grades of agarwood oil. Hence the thin film potentially be use as sensing material for grading agarwood oil and others nature product for the future.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381005
D. Nagel
Semiconductor and other materials with dimensions on the scale of micrometers or nanometers are being made into chemical and biological sensors. Besides being small, such devices are highly capable, low power and relatively inexpensive. They have many applications in personal health and safety, and for control of industrial processes.
{"title":"Micro-Scale Structures and Nano-Scale Materials for Chemical and Biological Sensors","authors":"D. Nagel","doi":"10.1109/SMELEC.2006.381005","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381005","url":null,"abstract":"Semiconductor and other materials with dimensions on the scale of micrometers or nanometers are being made into chemical and biological sensors. Besides being small, such devices are highly capable, low power and relatively inexpensive. They have many applications in personal health and safety, and for control of industrial processes.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133638058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381020
M.F. Islam, M.A.M. Ali
In the testing environment, test patterns are generated using techniques such as exhaustive, pseudo-random, deterministic and weighted random testing. Using deterministic testing technique, huge amount of memory space and lengthy testing time are required to generate and store large number of test patterns. On the other hand, pseudo-random technique reduces the number of test patterns but cannot achieve complete fault coverage. Hence primitive polynomial linear feedback shift register (LFSR) based pseudo-random and deterministic techniques have recently been proposed to be used simultaneously. This has been referred to as the mixed-mode approach. This paper introduces the adaptation of the mixed-mode test technique for MEMS testing.
{"title":"On the use of a Mixed-Mode Approach For MEMS Testing","authors":"M.F. Islam, M.A.M. Ali","doi":"10.1109/SMELEC.2006.381020","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381020","url":null,"abstract":"In the testing environment, test patterns are generated using techniques such as exhaustive, pseudo-random, deterministic and weighted random testing. Using deterministic testing technique, huge amount of memory space and lengthy testing time are required to generate and store large number of test patterns. On the other hand, pseudo-random technique reduces the number of test patterns but cannot achieve complete fault coverage. Hence primitive polynomial linear feedback shift register (LFSR) based pseudo-random and deterministic techniques have recently been proposed to be used simultaneously. This has been referred to as the mixed-mode approach. This paper introduces the adaptation of the mixed-mode test technique for MEMS testing.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380742
M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi
In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.
{"title":"A Novel Method to Design Interstage Matching Network in the Smith Chart","authors":"M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi","doi":"10.1109/SMELEC.2006.380742","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380742","url":null,"abstract":"In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115204197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381040
F. Lina Ayatollahi, B. Majlis
There has been some work in recent years to produce MEMS speakers. Geometries have included diaphragm structures, cantilever beams, and thermally actuated domes. The diaphragm skeleton is built out of the metal and glass layers of the CMOS chip, greatly reducing the layering ad patterning required, compared to other MEMS designs. "Brute multiplicity" is useful to circumvent the poor linearity of the individual elements; the number of elements determines the distortion of the total sound produced, not the quality of the transducer. The objective of this research focused on design a new way to produce the sound in rang of human hearing using micro speaker (on MEMS scale) and study concerned about possibility of MEMS speaker fabrication.
{"title":"Design and Modeling of Micromachined Condenser MEMS Loudspeaker using Permanent Magnet Neodymium-Iron-Boron (Nd-Fe-B)","authors":"F. Lina Ayatollahi, B. Majlis","doi":"10.1109/SMELEC.2006.381040","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381040","url":null,"abstract":"There has been some work in recent years to produce MEMS speakers. Geometries have included diaphragm structures, cantilever beams, and thermally actuated domes. The diaphragm skeleton is built out of the metal and glass layers of the CMOS chip, greatly reducing the layering ad patterning required, compared to other MEMS designs. \"Brute multiplicity\" is useful to circumvent the poor linearity of the individual elements; the number of elements determines the distortion of the total sound produced, not the quality of the transducer. The objective of this research focused on design a new way to produce the sound in rang of human hearing using micro speaker (on MEMS scale) and study concerned about possibility of MEMS speaker fabrication.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116806450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380745
M. Hussin, N. A. Rashid, R. Keating
This paper describes the effect of Ti deposition/anneal and supplementary BF2 implant/anneal on a 0.35 mum silicon CMOS process using contact silicided P+ source- drain. Thicker Ti and higher Ti/TiN annealing temperature are also required for the smaller contact sizes to get adequate P+ contact resistance. The supplementary BF2 implant with dose of 3E14 cm-2 and energy 20KeV helped to reduce and stabilize the contact resistance down to 150 Ohm/hole for the 0.4 mum P+ contact. The Boron profile at the TiSi2/p+ interface were investigated by 2D ATHENA process simulation. The peak Boron doping level at TiSi2/p+ interface significantly influenced the contact resistivity. Various contact chain test structures, with different contact sizes, plus single Kelvin structures were used in this investigation.
本文介绍了Ti沉积/退火和补充BF2植入/退火对接触硅化P+源漏0.35 μ m硅CMOS工艺的影响。为了获得足够的P+接触电阻，还需要更厚的Ti和更高的Ti/TiN退火温度。补充BF2植入物的剂量为3E14 cm-2，能量为20KeV，有助于降低和稳定0.4 μ m P+接触电阻至150欧姆/孔。采用二维ATHENA工艺模拟研究了TiSi2/p+界面硼的分布。TiSi2/p+界面处硼掺杂峰值对接触电阻率有显著影响。本研究采用了不同接触尺寸的接触链测试结构和单开尔文结构。
{"title":"Effects of High Dose BF2+ Implant on the Improvement of P+ Contact Resistance","authors":"M. Hussin, N. A. Rashid, R. Keating","doi":"10.1109/SMELEC.2006.380745","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380745","url":null,"abstract":"This paper describes the effect of Ti deposition/anneal and supplementary BF2 implant/anneal on a 0.35 mum silicon CMOS process using contact silicided P+ source- drain. Thicker Ti and higher Ti/TiN annealing temperature are also required for the smaller contact sizes to get adequate P+ contact resistance. The supplementary BF2 implant with dose of 3E14 cm-2 and energy 20KeV helped to reduce and stabilize the contact resistance down to 150 Ohm/hole for the 0.4 mum P+ contact. The Boron profile at the TiSi2/p+ interface were investigated by 2D ATHENA process simulation. The peak Boron doping level at TiSi2/p+ interface significantly influenced the contact resistivity. Various contact chain test structures, with different contact sizes, plus single Kelvin structures were used in this investigation.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114743486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380751
C. Senthilpari, K. Diwakar, C. Prabhu
The proposed 4 bit subtracter circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520 MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50 nm analysis, the proposed circuit is found to dissipate less power (~0.46 muW) and possess less overall area of order of 423 mum2. The propagation delay is 9.5206 times 10-12 sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.
采用互补通型晶体管逻辑(CPL)的位片方法设计了4位减法电路，适用于快速移位等应用;DSP数据处理装置环路中的乘法器/加法器。该电路可以高速执行实时计算任务。所设计的电路能有效地实时滤波100- 520mhz采样率的信号。利用microwind III VLSI CAD工具设计的亚微米区域电路，从传播延迟、功耗、功耗和面积等方面进行了分析。在50 nm的分析中，发现该电路的功耗更低(~0.46 muW)，总面积更小，约为423 mum2。在DSP体系结构中，时间和面积是保证算术和逻辑运算高效执行的关键因素。我们提出的电路是增强的，完整的指令周期，通过9.0 GHz的速度，高于报告的结果。
{"title":"Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit","authors":"C. Senthilpari, K. Diwakar, C. Prabhu","doi":"10.1109/SMELEC.2006.380751","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380751","url":null,"abstract":"The proposed 4 bit subtracter circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520 MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50 nm analysis, the proposed circuit is found to dissipate less power (~0.46 muW) and possess less overall area of order of 423 mum2. The propagation delay is 9.5206 times 10-12 sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114815372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381110
H. Lee, Yo-Han Kim, E. Kang, M. Sung
In this paper, we propose a new structure that improves the on-state voltage drop along with the switching speed in insulated gate bipolar transistors(IGBTs), which is widely applied in high voltage semiconductors. The proposed structure is unique that the collector area is divided by SiO2 regions, whereas in existing IGBTs, the collector has a planar P+ structure. The process and device simulation results show remarkably improved on-state and switching characteristics. The current and electric field distributions indicate that the segmented collector structure increases the electric field near the SiO2 edge which leads to an increase in electron current and finally a decrease in on-state voltage drop to 30% ~ 40%. Also, since the area of the P+ region decreases compared to existing structures, the hole injection decreases which leads to an improved switching speed to 30%.
{"title":"Design and Analysis of Insulate Gate Bipolar Transistor (IGBT) with P+/SiO2 Collector Structure Applicable to High Voltage to 1700 V","authors":"H. Lee, Yo-Han Kim, E. Kang, M. Sung","doi":"10.1109/SMELEC.2006.381110","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381110","url":null,"abstract":"In this paper, we propose a new structure that improves the on-state voltage drop along with the switching speed in insulated gate bipolar transistors(IGBTs), which is widely applied in high voltage semiconductors. The proposed structure is unique that the collector area is divided by SiO2 regions, whereas in existing IGBTs, the collector has a planar P+ structure. The process and device simulation results show remarkably improved on-state and switching characteristics. The current and electric field distributions indicate that the segmented collector structure increases the electric field near the SiO2 edge which leads to an increase in electron current and finally a decrease in on-state voltage drop to 30% ~ 40%. Also, since the area of the P+ region decreases compared to existing structures, the hole injection decreases which leads to an improved switching speed to 30%.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121384592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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