Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381010
A. A. Hamzah, B. Y. Majlis, I. Ahmad
Platinum membrane with silicon nitride layer is fabricated and analyzed. The membrane, which is designed for MEMS microphone application, is fabricated using sputter platinum and CVD silicon nitride. Membranes with sandwich layer of platinum-nitride-platinum with thickness of 6.35 mum are successfully fabricated. Deflection of the fabricated membrane corresponding to given pressure is measured using Tencor surface profiler. It is observed that deflection at its center is proportional to applied pressure for pressure between 20 Pa to 200 Pa. Average center deflection for applied pressure of 200 Pa is measured to be 0.41 mum. The fabricated platinum membrane is deemed suitable for MEMS microphone application due to its linear deflection response in acoustic pressure range.
{"title":"Fabrication of Platinum Membrane on Silicon for MEMS Microphone","authors":"A. A. Hamzah, B. Y. Majlis, I. Ahmad","doi":"10.1109/SMELEC.2006.381010","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381010","url":null,"abstract":"Platinum membrane with silicon nitride layer is fabricated and analyzed. The membrane, which is designed for MEMS microphone application, is fabricated using sputter platinum and CVD silicon nitride. Membranes with sandwich layer of platinum-nitride-platinum with thickness of 6.35 mum are successfully fabricated. Deflection of the fabricated membrane corresponding to given pressure is measured using Tencor surface profiler. It is observed that deflection at its center is proportional to applied pressure for pressure between 20 Pa to 200 Pa. Average center deflection for applied pressure of 200 Pa is measured to be 0.41 mum. The fabricated platinum membrane is deemed suitable for MEMS microphone application due to its linear deflection response in acoustic pressure range.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380706
L. S. Chuah, Z. Hassan, F. Yam, H. Abu Hassan
In this study, we have investigated the structural characteristics of nanoporous InN prepared by photoelectrochemical (PEC) wet etching. The PEC process which uses various 0.2, 0.5 and 1.0 wt% aqueous potassium hydroxide (KOH) solution utilizes photogenerated electron-hole pairs to enhance oxidation and reduction reactions taking place in an electrochemical cell. For etching condition using 0.2 wt% KOH solution (sample B), surface became relatively rough, however no pore was found. SEM images show that average pore size for sample C (0.5 wt% KOH solution) and sample D (1.0 wt% KOH solution) was around 30 to 60 nm. However, from our analysis of porous InN prepared by varying the etching condition, the non uniform etch rate across the sample surface is limited by diffusion processes. From the X-ray diffraction scan, porous samples show a broadening of the full width at half maximum with respect to the as-grown InN epilayer. On the other hand, the peak shift for InN (0002) and GaN (0002) diffraction planes was inconsistent. This can be explained by the relatively smaller statistical size distribution of the pores.
{"title":"Nanoporous InN Films Synthesized using Photoelectrochemical (PEC) Wet Etching","authors":"L. S. Chuah, Z. Hassan, F. Yam, H. Abu Hassan","doi":"10.1109/SMELEC.2006.380706","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380706","url":null,"abstract":"In this study, we have investigated the structural characteristics of nanoporous InN prepared by photoelectrochemical (PEC) wet etching. The PEC process which uses various 0.2, 0.5 and 1.0 wt% aqueous potassium hydroxide (KOH) solution utilizes photogenerated electron-hole pairs to enhance oxidation and reduction reactions taking place in an electrochemical cell. For etching condition using 0.2 wt% KOH solution (sample B), surface became relatively rough, however no pore was found. SEM images show that average pore size for sample C (0.5 wt% KOH solution) and sample D (1.0 wt% KOH solution) was around 30 to 60 nm. However, from our analysis of porous InN prepared by varying the etching condition, the non uniform etch rate across the sample surface is limited by diffusion processes. From the X-ray diffraction scan, porous samples show a broadening of the full width at half maximum with respect to the as-grown InN epilayer. On the other hand, the peak shift for InN (0002) and GaN (0002) diffraction planes was inconsistent. This can be explained by the relatively smaller statistical size distribution of the pores.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131159840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380682
H. Hashim, M. K. Othman, M. N. Osman, A. Dolah, M. Yahya
This paper report effects of variation spacing of mesa isolation on pHEMT substrate in order get an optimum isolated area. The multilayer pHEMT substrate was used as a substrate and wet etching techniques have been applied to form the islands. The citric mixture used is C2H8O7:H2O2:H2O with ratio of 4:1:1. The mesa spacing used in this study was varies at 570, 792 and 835 mum. The etch time for each spacing was fixed at 3 minutes. The electrical effect of mesa isolation spacing was characterized through current-voltage curve. It was found that the 570 mum mesa spacing shows optimum current value for mesa isolation. This indicated that 570 mum mesa spacing etch with citric acid mixture of 4:1:1 ratio for 3 minutes etch time can produce optimum current for application of pHEMT device.
{"title":"Effect of Mesa Spacing on the Electrical Properties of Mesa Isolation in High Electron Mobility Transistor Structures","authors":"H. Hashim, M. K. Othman, M. N. Osman, A. Dolah, M. Yahya","doi":"10.1109/SMELEC.2006.380682","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380682","url":null,"abstract":"This paper report effects of variation spacing of mesa isolation on pHEMT substrate in order get an optimum isolated area. The multilayer pHEMT substrate was used as a substrate and wet etching techniques have been applied to form the islands. The citric mixture used is C2H8O7:H2O2:H2O with ratio of 4:1:1. The mesa spacing used in this study was varies at 570, 792 and 835 mum. The etch time for each spacing was fixed at 3 minutes. The electrical effect of mesa isolation spacing was characterized through current-voltage curve. It was found that the 570 mum mesa spacing shows optimum current value for mesa isolation. This indicated that 570 mum mesa spacing etch with citric acid mixture of 4:1:1 ratio for 3 minutes etch time can produce optimum current for application of pHEMT device.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380747
R. Musa, Y. Yusoff, T. Yew, M. Ahmad
This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.
介绍了一种基于0.35 um CMOS技术的高速、高增益、低功耗全差分运算放大器的设计与仿真。该运放设计用于100mw 10位50 MS/s流水线模数转换器的采样保持级。该运放采用了单级折叠级联码的拓扑结构和增益提升技术。仿真运算放大器的直流增益为95dB，单位增益带宽为412 MHz，相位裕度为75度。稳定时间为7.5 ns，输入电压为3V时，运算放大器功耗为12.8 mW。
{"title":"Design of Single-Stage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter","authors":"R. Musa, Y. Yusoff, T. Yew, M. Ahmad","doi":"10.1109/SMELEC.2006.380747","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380747","url":null,"abstract":"This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127784479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380798
W.R.W. Ahmad, A. Kordesch, I. Ahmad, P. Yew
In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130 nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5 um to 0.34 um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data.
{"title":"TCAD Simulation of STI Stress Effect on Active Length for 130nm Technology","authors":"W.R.W. Ahmad, A. Kordesch, I. Ahmad, P. Yew","doi":"10.1109/SMELEC.2006.380798","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380798","url":null,"abstract":"In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130 nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5 um to 0.34 um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381029
J. Johari, B. Majlis
This paper presents a general approach to the problem of modeling diaphragm micropumps. This study utilized the finite element method to optimize the deflection of a bilaminar circular plate which consist of a single piezoelectric disc as an actuator and bonded to an elastic diaphragm of certain dimensions. Optimum actuator dimensions were fixed for a determined diaphragm dimensions.
{"title":"Analysis of a Bilaminar Circular Piezoelectric Actuator for Micropumps","authors":"J. Johari, B. Majlis","doi":"10.1109/SMELEC.2006.381029","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381029","url":null,"abstract":"This paper presents a general approach to the problem of modeling diaphragm micropumps. This study utilized the finite element method to optimize the deflection of a bilaminar circular plate which consist of a single piezoelectric disc as an actuator and bonded to an elastic diaphragm of certain dimensions. Optimum actuator dimensions were fixed for a determined diaphragm dimensions.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124526373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381025
T. Aziz, M. Salleh, M. Umar, M. Yahaya
Polymer light-emitting diode with ITO/PHF/Al structure has been fabricated, where PHF is poly (4,4'-diphenylene diphenylvinylene). The original device has turn-on voltage at 18.0 V. A reduction of turn-on voltage of this device is achieved by using the nanocomposites layer consisting of PHF and SiO2 nanoparticles as an emitting layer in a single structured ITO/nanocomposite/Al polymer light emitting diode. The SiO2: PHF was prepared by mixing 1.0 ml of PHF with 0.05 ml of SiO2 colloidal solution. It was found that the spin-coated nanocomposites has reduced the OLED turn-on voltage to 9.0 V.
制备了ITO/PHF/Al结构的聚合物发光二极管，其中PHF为聚(4,4′-二苯基乙烯)。原始设备的导通电压为18.0 V。在单结构ITO/纳米复合材料/Al聚合物发光二极管中，采用由PHF和SiO2纳米颗粒组成的纳米复合材料层作为发射层，实现了器件导通电压的降低。将1.0 ml PHF与0.05 ml SiO2胶体溶液混合制备SiO2: PHF。结果表明，自旋涂层纳米复合材料使OLED的导通电压降至9.0 V。
{"title":"Reduction of Turn-On Voltage in a Single Layer Structured Organic Light-Emitting Diode using Nanocomposites SiO2:PHF","authors":"T. Aziz, M. Salleh, M. Umar, M. Yahaya","doi":"10.1109/SMELEC.2006.381025","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381025","url":null,"abstract":"Polymer light-emitting diode with ITO/PHF/Al structure has been fabricated, where PHF is poly (4,4'-diphenylene diphenylvinylene). The original device has turn-on voltage at 18.0 V. A reduction of turn-on voltage of this device is achieved by using the nanocomposites layer consisting of PHF and SiO2 nanoparticles as an emitting layer in a single structured ITO/nanocomposite/Al polymer light emitting diode. The SiO2: PHF was prepared by mixing 1.0 ml of PHF with 0.05 ml of SiO2 colloidal solution. It was found that the spin-coated nanocomposites has reduced the OLED turn-on voltage to 9.0 V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381034
M. K. Othman, M. M. Salleh, A. Mat
This paper reports the various structures and performances improvements using different hole transporting layer in OLED based on DPVBi as emitter. Here the indium tin oxide (ITO) used as an anode, copper pthalocyanine (CuPc) as the hole injecting layer, PEDOT:PSS and poly-9- vinylcarbozole (PVK) as hole transporting layer, 4,4'-bis(2,2'diphenilvinyl)-1,1' -biphenyl (DPVBi) as the blue emitting layer and aluminum (Al) as the cathode. The CuPc and DPVBi were prepared by thermal evaporation while the PEDOT:PSS and PVK films were prepared using spin coating technique. The effect of inserting additional layer of CuPc, PVK and PEDOT:PSS between anode and the emitting layers was analyzed through the current-voltage (IV) curves and the electroluminescence spectra. The additional layer structure was found to increase the maximum luminance compared to that one of single layer device. The used of PVK as hole transporting layer has improved the diode properties of the device and able to prevent the device from short circuits. The optimized DPVBi layer thickness was observed at 56 nm and the insertion of 10 nm CuPc hole injecting layer show the device reduce it turn on voltage from 7.0 V to 6.5 V.
{"title":"Organic Light Emitting Diode (OLED) Using Different Hole Transport and Injecting Layers","authors":"M. K. Othman, M. M. Salleh, A. Mat","doi":"10.1109/SMELEC.2006.381034","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381034","url":null,"abstract":"This paper reports the various structures and performances improvements using different hole transporting layer in OLED based on DPVBi as emitter. Here the indium tin oxide (ITO) used as an anode, copper pthalocyanine (CuPc) as the hole injecting layer, PEDOT:PSS and poly-9- vinylcarbozole (PVK) as hole transporting layer, 4,4'-bis(2,2'diphenilvinyl)-1,1' -biphenyl (DPVBi) as the blue emitting layer and aluminum (Al) as the cathode. The CuPc and DPVBi were prepared by thermal evaporation while the PEDOT:PSS and PVK films were prepared using spin coating technique. The effect of inserting additional layer of CuPc, PVK and PEDOT:PSS between anode and the emitting layers was analyzed through the current-voltage (IV) curves and the electroluminescence spectra. The additional layer structure was found to increase the maximum luminance compared to that one of single layer device. The used of PVK as hole transporting layer has improved the diode properties of the device and able to prevent the device from short circuits. The optimized DPVBi layer thickness was observed at 56 nm and the insertion of 10 nm CuPc hole injecting layer show the device reduce it turn on voltage from 7.0 V to 6.5 V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381114
Hee Kong Phoon, M. Yap, Chuan Khye Chai
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.
{"title":"A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration","authors":"Hee Kong Phoon, M. Yap, Chuan Khye Chai","doi":"10.1109/SMELEC.2006.381114","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381114","url":null,"abstract":"Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134184193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380717
M. Siswanto, M. Othman, E. Zahedi
This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace- back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.
{"title":"VLSI Implementation of 1/2 Viterbi Decoder for IEEE P802.15-3a UWB Communication","authors":"M. Siswanto, M. Othman, E. Zahedi","doi":"10.1109/SMELEC.2006.380717","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380717","url":null,"abstract":"This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace- back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134287787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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