Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381010
A. A. Hamzah, B. Y. Majlis, I. Ahmad
Platinum membrane with silicon nitride layer is fabricated and analyzed. The membrane, which is designed for MEMS microphone application, is fabricated using sputter platinum and CVD silicon nitride. Membranes with sandwich layer of platinum-nitride-platinum with thickness of 6.35 mum are successfully fabricated. Deflection of the fabricated membrane corresponding to given pressure is measured using Tencor surface profiler. It is observed that deflection at its center is proportional to applied pressure for pressure between 20 Pa to 200 Pa. Average center deflection for applied pressure of 200 Pa is measured to be 0.41 mum. The fabricated platinum membrane is deemed suitable for MEMS microphone application due to its linear deflection response in acoustic pressure range.
{"title":"Fabrication of Platinum Membrane on Silicon for MEMS Microphone","authors":"A. A. Hamzah, B. Y. Majlis, I. Ahmad","doi":"10.1109/SMELEC.2006.381010","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381010","url":null,"abstract":"Platinum membrane with silicon nitride layer is fabricated and analyzed. The membrane, which is designed for MEMS microphone application, is fabricated using sputter platinum and CVD silicon nitride. Membranes with sandwich layer of platinum-nitride-platinum with thickness of 6.35 mum are successfully fabricated. Deflection of the fabricated membrane corresponding to given pressure is measured using Tencor surface profiler. It is observed that deflection at its center is proportional to applied pressure for pressure between 20 Pa to 200 Pa. Average center deflection for applied pressure of 200 Pa is measured to be 0.41 mum. The fabricated platinum membrane is deemed suitable for MEMS microphone application due to its linear deflection response in acoustic pressure range.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380706
L. S. Chuah, Z. Hassan, F. Yam, H. Abu Hassan
In this study, we have investigated the structural characteristics of nanoporous InN prepared by photoelectrochemical (PEC) wet etching. The PEC process which uses various 0.2, 0.5 and 1.0 wt% aqueous potassium hydroxide (KOH) solution utilizes photogenerated electron-hole pairs to enhance oxidation and reduction reactions taking place in an electrochemical cell. For etching condition using 0.2 wt% KOH solution (sample B), surface became relatively rough, however no pore was found. SEM images show that average pore size for sample C (0.5 wt% KOH solution) and sample D (1.0 wt% KOH solution) was around 30 to 60 nm. However, from our analysis of porous InN prepared by varying the etching condition, the non uniform etch rate across the sample surface is limited by diffusion processes. From the X-ray diffraction scan, porous samples show a broadening of the full width at half maximum with respect to the as-grown InN epilayer. On the other hand, the peak shift for InN (0002) and GaN (0002) diffraction planes was inconsistent. This can be explained by the relatively smaller statistical size distribution of the pores.
{"title":"Nanoporous InN Films Synthesized using Photoelectrochemical (PEC) Wet Etching","authors":"L. S. Chuah, Z. Hassan, F. Yam, H. Abu Hassan","doi":"10.1109/SMELEC.2006.380706","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380706","url":null,"abstract":"In this study, we have investigated the structural characteristics of nanoporous InN prepared by photoelectrochemical (PEC) wet etching. The PEC process which uses various 0.2, 0.5 and 1.0 wt% aqueous potassium hydroxide (KOH) solution utilizes photogenerated electron-hole pairs to enhance oxidation and reduction reactions taking place in an electrochemical cell. For etching condition using 0.2 wt% KOH solution (sample B), surface became relatively rough, however no pore was found. SEM images show that average pore size for sample C (0.5 wt% KOH solution) and sample D (1.0 wt% KOH solution) was around 30 to 60 nm. However, from our analysis of porous InN prepared by varying the etching condition, the non uniform etch rate across the sample surface is limited by diffusion processes. From the X-ray diffraction scan, porous samples show a broadening of the full width at half maximum with respect to the as-grown InN epilayer. On the other hand, the peak shift for InN (0002) and GaN (0002) diffraction planes was inconsistent. This can be explained by the relatively smaller statistical size distribution of the pores.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131159840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380682
H. Hashim, M. K. Othman, M. N. Osman, A. Dolah, M. Yahya
This paper report effects of variation spacing of mesa isolation on pHEMT substrate in order get an optimum isolated area. The multilayer pHEMT substrate was used as a substrate and wet etching techniques have been applied to form the islands. The citric mixture used is C2H8O7:H2O2:H2O with ratio of 4:1:1. The mesa spacing used in this study was varies at 570, 792 and 835 mum. The etch time for each spacing was fixed at 3 minutes. The electrical effect of mesa isolation spacing was characterized through current-voltage curve. It was found that the 570 mum mesa spacing shows optimum current value for mesa isolation. This indicated that 570 mum mesa spacing etch with citric acid mixture of 4:1:1 ratio for 3 minutes etch time can produce optimum current for application of pHEMT device.
{"title":"Effect of Mesa Spacing on the Electrical Properties of Mesa Isolation in High Electron Mobility Transistor Structures","authors":"H. Hashim, M. K. Othman, M. N. Osman, A. Dolah, M. Yahya","doi":"10.1109/SMELEC.2006.380682","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380682","url":null,"abstract":"This paper report effects of variation spacing of mesa isolation on pHEMT substrate in order get an optimum isolated area. The multilayer pHEMT substrate was used as a substrate and wet etching techniques have been applied to form the islands. The citric mixture used is C2H8O7:H2O2:H2O with ratio of 4:1:1. The mesa spacing used in this study was varies at 570, 792 and 835 mum. The etch time for each spacing was fixed at 3 minutes. The electrical effect of mesa isolation spacing was characterized through current-voltage curve. It was found that the 570 mum mesa spacing shows optimum current value for mesa isolation. This indicated that 570 mum mesa spacing etch with citric acid mixture of 4:1:1 ratio for 3 minutes etch time can produce optimum current for application of pHEMT device.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131688564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380747
R. Musa, Y. Yusoff, T. Yew, M. Ahmad
This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.
介绍了一种基于0.35 um CMOS技术的高速、高增益、低功耗全差分运算放大器的设计与仿真。该运放设计用于100mw 10位50 MS/s流水线模数转换器的采样保持级。该运放采用了单级折叠级联码的拓扑结构和增益提升技术。仿真运算放大器的直流增益为95dB，单位增益带宽为412 MHz，相位裕度为75度。稳定时间为7.5 ns，输入电压为3V时，运算放大器功耗为12.8 mW。
{"title":"Design of Single-Stage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter","authors":"R. Musa, Y. Yusoff, T. Yew, M. Ahmad","doi":"10.1109/SMELEC.2006.380747","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380747","url":null,"abstract":"This paper presents the design and simulation of high speed, high gain and low power fully differential operational amplifier (op-amp) implemented in 0.35 um CMOS technology. The op-amp was designed for sample-and-hold stage of 100 mW 10-bit 50 MS/s pipelined analog-to-digital converter. A topology of single-stage folded-cascode with gain boosting technique is employed in this op-amp. The simulated op-amp achieves a DC gain of 95dB, unity gain bandwidth of 412 MHz and phase margin of 75 degrees. The settling time is 7.5 ns and the op-amp consumes power 12.8 mW with supply voltage of 3V.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127784479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380798
W.R.W. Ahmad, A. Kordesch, I. Ahmad, P. Yew
In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130 nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5 um to 0.34 um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data.
{"title":"TCAD Simulation of STI Stress Effect on Active Length for 130nm Technology","authors":"W.R.W. Ahmad, A. Kordesch, I. Ahmad, P. Yew","doi":"10.1109/SMELEC.2006.380798","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380798","url":null,"abstract":"In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130 nm Technology. When the Sa is decreasing, Sxx stress becomes more compressive for both P- and N- MOS while the Syy component becomes more tensile, causing hole mobility improvement in PMOS and electron mobility degradation in NMOS. When Sa decreases from 5 um to 0.34 um, the Idsat for NMOS is degraded 6.6% and Idsat for PMOS is increased 6%. This means narrower Sa will increases hole mobility performance in p-channel but degrade the electron mobility in n-channel. These results agree with the experimental data.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134096931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381020
M.F. Islam, M.A.M. Ali
In the testing environment, test patterns are generated using techniques such as exhaustive, pseudo-random, deterministic and weighted random testing. Using deterministic testing technique, huge amount of memory space and lengthy testing time are required to generate and store large number of test patterns. On the other hand, pseudo-random technique reduces the number of test patterns but cannot achieve complete fault coverage. Hence primitive polynomial linear feedback shift register (LFSR) based pseudo-random and deterministic techniques have recently been proposed to be used simultaneously. This has been referred to as the mixed-mode approach. This paper introduces the adaptation of the mixed-mode test technique for MEMS testing.
{"title":"On the use of a Mixed-Mode Approach For MEMS Testing","authors":"M.F. Islam, M.A.M. Ali","doi":"10.1109/SMELEC.2006.381020","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381020","url":null,"abstract":"In the testing environment, test patterns are generated using techniques such as exhaustive, pseudo-random, deterministic and weighted random testing. Using deterministic testing technique, huge amount of memory space and lengthy testing time are required to generate and store large number of test patterns. On the other hand, pseudo-random technique reduces the number of test patterns but cannot achieve complete fault coverage. Hence primitive polynomial linear feedback shift register (LFSR) based pseudo-random and deterministic techniques have recently been proposed to be used simultaneously. This has been referred to as the mixed-mode approach. This paper introduces the adaptation of the mixed-mode test technique for MEMS testing.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380742
M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi
In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.
{"title":"A Novel Method to Design Interstage Matching Network in the Smith Chart","authors":"M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi","doi":"10.1109/SMELEC.2006.380742","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380742","url":null,"abstract":"In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115204197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380796
R. Sanusi, A. Rahim, M. N. Osman, N. Kushairi, A. Rasmi, N. Muhammad, M. Yahya, A. Mat
Polymide metal-insulator-metal (MIM) overlay capacitors for use in monolithic microwave integrated circuits (MMICs) based on high electron mobility transistors (HEMTs) on gallium arsenide substrates are presented. Modeling of the capacitors was performed using a 2-dimensional electromagnetic CAD simulator to obtain Scattering (S-) parameters for different capacitor dimensions for operating frequencies from 0.05 to 8 GHz. The behaviour of the capacitor as a function of operating frequencies is studied by means of Smith chart. The capacitor is finally represented by a proposed equivalent circuit model to describe its overall behavior for planar MMIC simulations.
{"title":"Modeling of Polyimide MIM Capacitors for Applications in Planar Monolithic Microwave Integrated Circuits","authors":"R. Sanusi, A. Rahim, M. N. Osman, N. Kushairi, A. Rasmi, N. Muhammad, M. Yahya, A. Mat","doi":"10.1109/SMELEC.2006.380796","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380796","url":null,"abstract":"Polymide metal-insulator-metal (MIM) overlay capacitors for use in monolithic microwave integrated circuits (MMICs) based on high electron mobility transistors (HEMTs) on gallium arsenide substrates are presented. Modeling of the capacitors was performed using a 2-dimensional electromagnetic CAD simulator to obtain Scattering (S-) parameters for different capacitor dimensions for operating frequencies from 0.05 to 8 GHz. The behaviour of the capacitor as a function of operating frequencies is studied by means of Smith chart. The capacitor is finally represented by a proposed equivalent circuit model to describe its overall behavior for planar MMIC simulations.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115692760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380724
S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao
Front end defects are usually more intricate as compared to back end defects, and as technology scale down into deep submicron regime, failure analysis of the front end defect is becoming even more challenging due to the increase in complexity of the process. In this paper, failure analysis on three types of front- end defect has been discussed. These defects are cobalt silicide at poly sidewall causing active to poly bridging, amorphous layer under contact and broken silicide on poly line, which were observed on 90 nm SOI wafers.
{"title":"Front End Defects on Deep Submicron Devices","authors":"S. P. Neo, S. K. Loh, Z.G. Song, S.P. Zhao","doi":"10.1109/SMELEC.2006.380724","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380724","url":null,"abstract":"Front end defects are usually more intricate as compared to back end defects, and as technology scale down into deep submicron regime, failure analysis of the front end defect is becoming even more challenging due to the increase in complexity of the process. In this paper, failure analysis on three types of front- end defect has been discussed. These defects are cobalt silicide at poly sidewall causing active to poly bridging, amorphous layer under contact and broken silicide on poly line, which were observed on 90 nm SOI wafers.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114518859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381107
D. Gui, Z. X. Xing, Z. Mo, Y. Hua, S.P. Zhao
The gate oxide is the most fragile element of metal-oxide-semiconductor (MOS) transistor. Metallic contamination in the gate oxide leads to high leak current and even gate oxide breakdown. In this paper, we have investigated a failure case of NMOS gate oxide breakdown using secondary ion mass spectrometry (SIMS) because of its excellent sensitivity. The SIMS depth profiles at the test pad in the scribe line showed that the gate oxide breakdown was caused by tungsten (W) contamination. Further study indicated that W contaminated wafers during n-poly implantation by the re-deposition from the supporting disk of implanter. Based on the SIMS results, measures have been suggested to reduce the W contamination.
{"title":"SIMS Analysis of Gate Oxide Breakdown Due to Tungsten Contamination","authors":"D. Gui, Z. X. Xing, Z. Mo, Y. Hua, S.P. Zhao","doi":"10.1109/SMELEC.2006.381107","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381107","url":null,"abstract":"The gate oxide is the most fragile element of metal-oxide-semiconductor (MOS) transistor. Metallic contamination in the gate oxide leads to high leak current and even gate oxide breakdown. In this paper, we have investigated a failure case of NMOS gate oxide breakdown using secondary ion mass spectrometry (SIMS) because of its excellent sensitivity. The SIMS depth profiles at the test pad in the scribe line showed that the gate oxide breakdown was caused by tungsten (W) contamination. Further study indicated that W contaminated wafers during n-poly implantation by the re-deposition from the supporting disk of implanter. Based on the SIMS results, measures have been suggested to reduce the W contamination.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114564779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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