Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380733
M. Norman Fadhil Idham, O. Nurul Afzan, H. Soetedjo, A.R. Ahmad Ismat, I. Sabtu, Y. Mohamed Razman, A.M. Abdul Fatah
This paper presents a novel technique to obtain device characteristics of high electron mobility transistors (HEMT) structures based on the backgate contact method, thus avoiding the need for complete gate formation. The gate contact was prepared on the back side of the substrate. Measurements performed on various HEMT structures shows typical transistor characteristics. Significant changes in drain- source current as a function of backgate voltage bias was observed for different HEMT structures. Increasing the channel thickness from 8 to 26 nm shows an increase in the threshold voltage of the transistor and a noticeable variation in drain-source current. This result leads to an effective and novel technique for the determination of sample quality prior to the further fabrication process to obtain the complete device.
{"title":"Device Characteristics of HEMT Structures based on Backgate Contact Method","authors":"M. Norman Fadhil Idham, O. Nurul Afzan, H. Soetedjo, A.R. Ahmad Ismat, I. Sabtu, Y. Mohamed Razman, A.M. Abdul Fatah","doi":"10.1109/SMELEC.2006.380733","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380733","url":null,"abstract":"This paper presents a novel technique to obtain device characteristics of high electron mobility transistors (HEMT) structures based on the backgate contact method, thus avoiding the need for complete gate formation. The gate contact was prepared on the back side of the substrate. Measurements performed on various HEMT structures shows typical transistor characteristics. Significant changes in drain- source current as a function of backgate voltage bias was observed for different HEMT structures. Increasing the channel thickness from 8 to 26 nm shows an increase in the threshold voltage of the transistor and a noticeable variation in drain-source current. This result leads to an effective and novel technique for the determination of sample quality prior to the further fabrication process to obtain the complete device.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121952615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380790
N. S. Ismail, I. Ahmad, H. Husain, S. Chuah
The objective of this research is to study electrical overstress (EOS) defect at gate oxide for various pulse widths in n-channel power metal-oxide-semiconductor field effect transistor (MOSFET). Moreover, this research also intent to develop power failure model for n-channel power MOSFET according to Tasca method. Electrical overstress does not have EOS standards and quantitative EOS design objectives to tackle this problem. Square pulse testing is used in this research due to easy to generate and simple to analyze. Time-to-failure (tf) is taken for power profiles modeling by observing abrupt drop in voltage waveform seen on oscilloscope. Tasca derived the thermal model by regarded the defect area as a sphere immersed in an infinite medium at ambient temperature. Result from failure analysis on all failed units had shown that hot spot formations begin at gate runner of the die and pulse stress given on VGS has cause gate oxide breakdown. Pulse power failure model for device n-channel power MOSFET can be obtained using Tasca method.
{"title":"Pulse Power Failure Model Of Power MOSFET Due To Electrical Overstress Using Tasca Method","authors":"N. S. Ismail, I. Ahmad, H. Husain, S. Chuah","doi":"10.1109/SMELEC.2006.380790","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380790","url":null,"abstract":"The objective of this research is to study electrical overstress (EOS) defect at gate oxide for various pulse widths in n-channel power metal-oxide-semiconductor field effect transistor (MOSFET). Moreover, this research also intent to develop power failure model for n-channel power MOSFET according to Tasca method. Electrical overstress does not have EOS standards and quantitative EOS design objectives to tackle this problem. Square pulse testing is used in this research due to easy to generate and simple to analyze. Time-to-failure (tf) is taken for power profiles modeling by observing abrupt drop in voltage waveform seen on oscilloscope. Tasca derived the thermal model by regarded the defect area as a sphere immersed in an infinite medium at ambient temperature. Result from failure analysis on all failed units had shown that hot spot formations begin at gate runner of the die and pulse stress given on VGS has cause gate oxide breakdown. Pulse power failure model for device n-channel power MOSFET can be obtained using Tasca method.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381110
H. Lee, Yo-Han Kim, E. Kang, M. Sung
In this paper, we propose a new structure that improves the on-state voltage drop along with the switching speed in insulated gate bipolar transistors(IGBTs), which is widely applied in high voltage semiconductors. The proposed structure is unique that the collector area is divided by SiO2 regions, whereas in existing IGBTs, the collector has a planar P+ structure. The process and device simulation results show remarkably improved on-state and switching characteristics. The current and electric field distributions indicate that the segmented collector structure increases the electric field near the SiO2 edge which leads to an increase in electron current and finally a decrease in on-state voltage drop to 30% ~ 40%. Also, since the area of the P+ region decreases compared to existing structures, the hole injection decreases which leads to an improved switching speed to 30%.
{"title":"Design and Analysis of Insulate Gate Bipolar Transistor (IGBT) with P+/SiO2 Collector Structure Applicable to High Voltage to 1700 V","authors":"H. Lee, Yo-Han Kim, E. Kang, M. Sung","doi":"10.1109/SMELEC.2006.381110","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381110","url":null,"abstract":"In this paper, we propose a new structure that improves the on-state voltage drop along with the switching speed in insulated gate bipolar transistors(IGBTs), which is widely applied in high voltage semiconductors. The proposed structure is unique that the collector area is divided by SiO2 regions, whereas in existing IGBTs, the collector has a planar P+ structure. The process and device simulation results show remarkably improved on-state and switching characteristics. The current and electric field distributions indicate that the segmented collector structure increases the electric field near the SiO2 edge which leads to an increase in electron current and finally a decrease in on-state voltage drop to 30% ~ 40%. Also, since the area of the P+ region decreases compared to existing structures, the hole injection decreases which leads to an improved switching speed to 30%.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121384592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381005
D. Nagel
Semiconductor and other materials with dimensions on the scale of micrometers or nanometers are being made into chemical and biological sensors. Besides being small, such devices are highly capable, low power and relatively inexpensive. They have many applications in personal health and safety, and for control of industrial processes.
{"title":"Micro-Scale Structures and Nano-Scale Materials for Chemical and Biological Sensors","authors":"D. Nagel","doi":"10.1109/SMELEC.2006.381005","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381005","url":null,"abstract":"Semiconductor and other materials with dimensions on the scale of micrometers or nanometers are being made into chemical and biological sensors. Besides being small, such devices are highly capable, low power and relatively inexpensive. They have many applications in personal health and safety, and for control of industrial processes.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133638058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381024
G. Wiranto, I. Adiseno, D.P. Hermida, R. Manurung, S. Widodo, M. Siregar
The use of nanocrystalline metal oxide powders to increase the sensitivity of gas sensors has been the subject of this research. Of particular interest to our application in environmental monitoring is ln2O3 and SnO2, which are known, respectively, to have a high sensitivity to oxidising pollutant gases such as NO2 and 03, and reducing pollutant gases such as CO and NH3. Preparation of undoped nanocrystalline SnO2 and ln2O3 powders by mechanical milling via centrifugal action have been conducted. The technique used has allowed the reduction of grain sizes from 3-5 mum to below 100 nm with no contaminating carbon content, as confirmed by SEM and EDS spectra analysis. Furthermore, the FTIR spectra indicated that the SnO2 nanopowders had a strong band at 671 cm-1 and ln2O3 at 601 cm-1. The resulting nanopowders were then mixed with alpha-based terpinol to produce a thick film paste as an active material of gas sensors, and applied to an alumina platform consisting of AgPt heater and electrode tracks.
{"title":"The Gas Sensing Potential of Nanocrystalline SnO2 and In2O3 Powders Prepared by Mechanical Milling","authors":"G. Wiranto, I. Adiseno, D.P. Hermida, R. Manurung, S. Widodo, M. Siregar","doi":"10.1109/SMELEC.2006.381024","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381024","url":null,"abstract":"The use of nanocrystalline metal oxide powders to increase the sensitivity of gas sensors has been the subject of this research. Of particular interest to our application in environmental monitoring is ln<sub>2</sub>O<sub>3</sub> and SnO<sub>2</sub>, which are known, respectively, to have a high sensitivity to oxidising pollutant gases such as NO<sub>2</sub> and 03, and reducing pollutant gases such as CO and NH<sub>3</sub>. Preparation of undoped nanocrystalline SnO<sub>2</sub> and ln<sub>2</sub>O<sub>3</sub> powders by mechanical milling via centrifugal action have been conducted. The technique used has allowed the reduction of grain sizes from 3-5 mum to below 100 nm with no contaminating carbon content, as confirmed by SEM and EDS spectra analysis. Furthermore, the FTIR spectra indicated that the SnO<sub>2</sub> nanopowders had a strong band at 671 cm<sup>-1</sup> and ln<sub>2</sub>O<sub>3</sub> at 601 cm<sup>-1</sup>. The resulting nanopowders were then mixed with alpha-based terpinol to produce a thick film paste as an active material of gas sensors, and applied to an alumina platform consisting of AgPt heater and electrode tracks.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130318557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381040
F. Lina Ayatollahi, B. Majlis
There has been some work in recent years to produce MEMS speakers. Geometries have included diaphragm structures, cantilever beams, and thermally actuated domes. The diaphragm skeleton is built out of the metal and glass layers of the CMOS chip, greatly reducing the layering ad patterning required, compared to other MEMS designs. "Brute multiplicity" is useful to circumvent the poor linearity of the individual elements; the number of elements determines the distortion of the total sound produced, not the quality of the transducer. The objective of this research focused on design a new way to produce the sound in rang of human hearing using micro speaker (on MEMS scale) and study concerned about possibility of MEMS speaker fabrication.
{"title":"Design and Modeling of Micromachined Condenser MEMS Loudspeaker using Permanent Magnet Neodymium-Iron-Boron (Nd-Fe-B)","authors":"F. Lina Ayatollahi, B. Majlis","doi":"10.1109/SMELEC.2006.381040","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381040","url":null,"abstract":"There has been some work in recent years to produce MEMS speakers. Geometries have included diaphragm structures, cantilever beams, and thermally actuated domes. The diaphragm skeleton is built out of the metal and glass layers of the CMOS chip, greatly reducing the layering ad patterning required, compared to other MEMS designs. \"Brute multiplicity\" is useful to circumvent the poor linearity of the individual elements; the number of elements determines the distortion of the total sound produced, not the quality of the transducer. The objective of this research focused on design a new way to produce the sound in rang of human hearing using micro speaker (on MEMS scale) and study concerned about possibility of MEMS speaker fabrication.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116806450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380711
Houn Wai Wong, P.F. Low, V.K. Wong
Time resolved emission microscopy (TRE) is a revolutionary tool used in advanced microprocessors silicon debug. Unlike other debug tools, the interpretation of TRE data may not be straightforward and can sometimes be misleading. In this paper we show through a case study why this is true. Interpretation of TRE data should be done carefully with good knowledge on device emission physics, circuit behavior and creative fault analysis.
{"title":"Circuit Debug using Time Resolved Emission (TRE) Prober - A Case Study","authors":"Houn Wai Wong, P.F. Low, V.K. Wong","doi":"10.1109/SMELEC.2006.380711","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380711","url":null,"abstract":"Time resolved emission microscopy (TRE) is a revolutionary tool used in advanced microprocessors silicon debug. Unlike other debug tools, the interpretation of TRE data may not be straightforward and can sometimes be misleading. In this paper we show through a case study why this is true. Interpretation of TRE data should be done carefully with good knowledge on device emission physics, circuit behavior and creative fault analysis.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131085298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380791
A. El-Abd, M. Aziz, A.A. Shalby, S. Khamis
Most theoretical I-V models appeared in the literature for AlGaN/GaN HEMTs fail to exactly fit the experimental data and a large deviation is reported, especially at large gate bias. Because the exact nature of the AlGaN/GaN hetrostructure is not fully described, we assume that there is a new phenomena in the device which causes this deviation. Here we compute this phenomena mathematically for doped and undoped devices using a new method. The model results will be useful in CAD programs to extract more accurate I-V characteristics for the AlGaN/GaN hetrostructure on sapphire substrate.
{"title":"New I-V Model For AlGaN/GaN HEMT At Large Gate Bias","authors":"A. El-Abd, M. Aziz, A.A. Shalby, S. Khamis","doi":"10.1109/SMELEC.2006.380791","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380791","url":null,"abstract":"Most theoretical I-V models appeared in the literature for AlGaN/GaN HEMTs fail to exactly fit the experimental data and a large deviation is reported, especially at large gate bias. Because the exact nature of the AlGaN/GaN hetrostructure is not fully described, we assume that there is a new phenomena in the device which causes this deviation. Here we compute this phenomena mathematically for doped and undoped devices using a new method. The model results will be useful in CAD programs to extract more accurate I-V characteristics for the AlGaN/GaN hetrostructure on sapphire substrate.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380717
M. Siswanto, M. Othman, E. Zahedi
This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace- back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.
{"title":"VLSI Implementation of 1/2 Viterbi Decoder for IEEE P802.15-3a UWB Communication","authors":"M. Siswanto, M. Othman, E. Zahedi","doi":"10.1109/SMELEC.2006.380717","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380717","url":null,"abstract":"This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace- back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134287787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381114
Hee Kong Phoon, M. Yap, Chuan Khye Chai
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.
{"title":"A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration","authors":"Hee Kong Phoon, M. Yap, Chuan Khye Chai","doi":"10.1109/SMELEC.2006.381114","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381114","url":null,"abstract":"Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134184193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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