Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380734
N.F. Idham M, A.I. Ahmad Ismat, S. Rasidah, D. Asban, M. Razman Y, A.M. Abdul Fatah
Metamorphic InAlAs/InGaAs high electron mobility transistors (HEMT) has demonstrated several advantages over pseudomorphic-HEMT on GaAs and lattice matched-HEMT on InP substrate. The high Indium content of the channel (50%) lattice matched to the substrate is the key factor behind the superior metamorphic HEMT performance. Metamorphic HEMT allows a flexible range of InGaAs channel compositions from 30% to 80% (based on the applications) [1] on a compositionally graded buffer. Commercially available TCAD is used to simulate the metamorphic HEMT to study the effect of varying Indium % in the channel layer on the electrical characteristics of the device.
{"title":"Effect of Indium Content in the Channel on the Electrical Performance of Metamorphic High Electron Mobility Transistors","authors":"N.F. Idham M, A.I. Ahmad Ismat, S. Rasidah, D. Asban, M. Razman Y, A.M. Abdul Fatah","doi":"10.1109/SMELEC.2006.380734","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380734","url":null,"abstract":"Metamorphic InAlAs/InGaAs high electron mobility transistors (HEMT) has demonstrated several advantages over pseudomorphic-HEMT on GaAs and lattice matched-HEMT on InP substrate. The high Indium content of the channel (50%) lattice matched to the substrate is the key factor behind the superior metamorphic HEMT performance. Metamorphic HEMT allows a flexible range of InGaAs channel compositions from 30% to 80% (based on the applications) [1] on a compositionally graded buffer. Commercially available TCAD is used to simulate the metamorphic HEMT to study the effect of varying Indium % in the channel layer on the electrical characteristics of the device.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133921743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380704
S. Lee, H. Younan, Z. Siping, Mo Zhi-qiang
Energy-dispersive X-ray microanalysis technique has been commonly used in failure analysis. It is vital for an analyst to understand the electron penetration depth in a certain material so as to be able to select an appropriate accelerating beam voltage. In this paper, we will use the Monte Carlo electron flight simulation method to obtain the electron penetration data at the different beam acceleration voltages of 5 kV, 10 kV, 15 kV, 20 kV, 25 kV and 30 kV for the various possible elements/materials in wafer fabrication.
{"title":"Studies on Electron Penetration Versus Beam Acceleration Voltage in Energy-Dispersive X-Ray Microanalysis","authors":"S. Lee, H. Younan, Z. Siping, Mo Zhi-qiang","doi":"10.1109/SMELEC.2006.380704","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380704","url":null,"abstract":"Energy-dispersive X-ray microanalysis technique has been commonly used in failure analysis. It is vital for an analyst to understand the electron penetration depth in a certain material so as to be able to select an appropriate accelerating beam voltage. In this paper, we will use the Monte Carlo electron flight simulation method to obtain the electron penetration data at the different beam acceleration voltages of 5 kV, 10 kV, 15 kV, 20 kV, 25 kV and 30 kV for the various possible elements/materials in wafer fabrication.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380746
R. Sehgal, S. S. Rajput, S. Jamuar
A two-stage low voltage operational amplifier for operation at plusmn0.4 V is proposed. The amplifier incorporates a low voltage current mirror designed using standard floating gate MOSFETs. The proposed op amp possesses a 49 dB open-loop gain, a high bandwidth of 698 kHz, 42deg phase margin and consumes only 28.6 muW. The operation of the proposed current mirror and op amp has been confirmed by PSPICE simulations, using 0.13 mum CMOS technology.
提出了一种工作电压为+ 0.4 V的两级低电压运算放大器。放大器集成了一个使用标准浮栅mosfet设计的低压电流反射镜。所提出的运放具有49 dB开环增益，698 kHz高带宽，42度相位裕度，功耗仅为28.6 muW。采用0.13 μ m CMOS技术的PSPICE仿真证实了所提出的电流镜和运放的运行。
{"title":"A 0.8V Operational Amplifier using Floating Gate MOS Technology","authors":"R. Sehgal, S. S. Rajput, S. Jamuar","doi":"10.1109/SMELEC.2006.380746","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380746","url":null,"abstract":"A two-stage low voltage operational amplifier for operation at plusmn0.4 V is proposed. The amplifier incorporates a low voltage current mirror designed using standard floating gate MOSFETs. The proposed op amp possesses a 49 dB open-loop gain, a high bandwidth of 698 kHz, 42deg phase margin and consumes only 28.6 muW. The operation of the proposed current mirror and op amp has been confirmed by PSPICE simulations, using 0.13 mum CMOS technology.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134398904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381071
W. Wong, William K. S. Pao, D. Holliday, P. Mellor
The design of an electromagnetic levitated and actuated micromotor is presented. The micromotor is consists of a counter-circular tracks that provide stable levitation force and radial parallel tracks that produce motoring rotational torque. Using simple filamentary representation of different features of the micromotor design, analytical expressions of the electromagnetic force produced by the features are derived and are used as foundation for the micromotor design. Finite element modeling is then used to analyze the actual micromotor design layout. From both the analytical and modeling results, the effects of different design features are presented. Finally, a macro-scale demonstrator is constructed to corroborate the micromotor design.
{"title":"Design and Modeling of an Electromagnetic Levitated and Actuated Micromotor","authors":"W. Wong, William K. S. Pao, D. Holliday, P. Mellor","doi":"10.1109/SMELEC.2006.381071","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381071","url":null,"abstract":"The design of an electromagnetic levitated and actuated micromotor is presented. The micromotor is consists of a counter-circular tracks that provide stable levitation force and radial parallel tracks that produce motoring rotational torque. Using simple filamentary representation of different features of the micromotor design, analytical expressions of the electromagnetic force produced by the features are derived and are used as foundation for the micromotor design. Finite element modeling is then used to analyze the actual micromotor design layout. From both the analytical and modeling results, the effects of different design features are presented. Finally, a macro-scale demonstrator is constructed to corroborate the micromotor design.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131593219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380781
Ahyar Bakri, M.J. Manaf, K. Wahab, I. Bin Ahmad
This research characterizes line edge roughness (LER), determines which resist has lowest LER for all process variations, and investigates the effect of chromophore bulkiness on LER. Three KrF photoresists with different chromophore bulkiness were evaluated. The characteristics evaluated were depth of focus (DOF), profile and resolution, LER, exposure latitude, iso-dense bias and CD linearity. Different feature sizes were tested from 100 nm to 190 nm. From the results, it is seen that resist PI has the lowest average LER for all process conditions and variations with a 3 sigma value of 10.074. This is followed by resist P5 and P6 with a 3 sigma LER value of 12.562 and 15.468. It is concluded that high chromophore bulkiness results in high UV activation. This is seen from the LER for resist P6 that is the highest out of all the photoresist. Reducing the chromophore bulkiness will reduce LER until it reaches a saturation point where reduction will not result in any lower LER. Reducing the chromophore bulkiness further beyond the saturation point will in fact increase the LER.
{"title":"The Characterization of KrF Photoresists and the Effect of Different Chromophore Bulkiness on Line Edge Roughness (LER) for Submicron Technology","authors":"Ahyar Bakri, M.J. Manaf, K. Wahab, I. Bin Ahmad","doi":"10.1109/SMELEC.2006.380781","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380781","url":null,"abstract":"This research characterizes line edge roughness (LER), determines which resist has lowest LER for all process variations, and investigates the effect of chromophore bulkiness on LER. Three KrF photoresists with different chromophore bulkiness were evaluated. The characteristics evaluated were depth of focus (DOF), profile and resolution, LER, exposure latitude, iso-dense bias and CD linearity. Different feature sizes were tested from 100 nm to 190 nm. From the results, it is seen that resist PI has the lowest average LER for all process conditions and variations with a 3 sigma value of 10.074. This is followed by resist P5 and P6 with a 3 sigma LER value of 12.562 and 15.468. It is concluded that high chromophore bulkiness results in high UV activation. This is seen from the LER for resist P6 that is the highest out of all the photoresist. Reducing the chromophore bulkiness will reduce LER until it reaches a saturation point where reduction will not result in any lower LER. Reducing the chromophore bulkiness further beyond the saturation point will in fact increase the LER.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131131274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381083
A. Rasmi, U. Hashim, A. Awang Mat
One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with 100 nm gate length and 10 nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 times 10-9 Watt for fixed current and 3.3565 times 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation.
{"title":"Design of 100nm Single-Electron Transistor (SET) by 2D TCAD Simulation","authors":"A. Rasmi, U. Hashim, A. Awang Mat","doi":"10.1109/SMELEC.2006.381083","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381083","url":null,"abstract":"One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with 100 nm gate length and 10 nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 times 10-9 Watt for fixed current and 3.3565 times 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"41 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133477944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380783
Z. Siping, H. Younan, R. Ramesh, Li Kun
A NSOP due to Al fluoride oxide case was investigated. The NSOP problem on microchip Al bondpads was reported. SEM, EDX, TEM and Auger FA techniques were used to identify the root cause. Optical inspection did not show any abnormality, however, high magnification SEM inspection found the "white dot"-like defects. TEM and Auger analysis results showed that a thicker oxide layer on bondpads, which was about 200-300 A. After studies on failure mechanism, it was concluded that the thicker layer detected by TEM was not Al oxide layer (Al2O3), but it was Al fluoride oxide-AlxOyFz which was due to F contamination during polyimide ashing process. In this paper we will further discuss the failure mechanism proposed and explain the formation of the Al fluoride oxide-AlxOyFz. In this paper, the possible root cause and eliminating solution are also studied. After changing a new dedicated ashing process machine, the F contamination was eliminated.
{"title":"Failure Analysis of NSOP Problem Due to Al Fluoride Oxide on Microchip Al Bondpads","authors":"Z. Siping, H. Younan, R. Ramesh, Li Kun","doi":"10.1109/SMELEC.2006.380783","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380783","url":null,"abstract":"A NSOP due to Al fluoride oxide case was investigated. The NSOP problem on microchip Al bondpads was reported. SEM, EDX, TEM and Auger FA techniques were used to identify the root cause. Optical inspection did not show any abnormality, however, high magnification SEM inspection found the \"white dot\"-like defects. TEM and Auger analysis results showed that a thicker oxide layer on bondpads, which was about 200-300 A. After studies on failure mechanism, it was concluded that the thicker layer detected by TEM was not Al oxide layer (Al2O3), but it was Al fluoride oxide-AlxOyFz which was due to F contamination during polyimide ashing process. In this paper we will further discuss the failure mechanism proposed and explain the formation of the Al fluoride oxide-AlxOyFz. In this paper, the possible root cause and eliminating solution are also studied. After changing a new dedicated ashing process machine, the F contamination was eliminated.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115910769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380761
E. Sooudi, M. Soroosh
In this paper, we propose a circuit model for vertical-cavity surface-emitting laser (VCSEL). The model is based on carrier, photon, and thermal rate equations, with addition of carrier leakage current as the main source for output power rollover phenomenon. Also, presumed distribution of carriers and photons are used in rate equations, and the spatially dependent equations are converted to spatially independent rate equations. The effect of carrier diffusion, input current, and temperature in transient turn-off behavior of laser for pulsed operation are analyzed. We also study the thermo-temporal behavior of laser in pulsed operation and determine the effects of input pulse on output power.
{"title":"A Versatile HSPICE Electro-Opto-Thermal Circuit Model for Vertical-Cavity Surface-Emitting Lasers","authors":"E. Sooudi, M. Soroosh","doi":"10.1109/SMELEC.2006.380761","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380761","url":null,"abstract":"In this paper, we propose a circuit model for vertical-cavity surface-emitting laser (VCSEL). The model is based on carrier, photon, and thermal rate equations, with addition of carrier leakage current as the main source for output power rollover phenomenon. Also, presumed distribution of carriers and photons are used in rate equations, and the spatially dependent equations are converted to spatially independent rate equations. The effect of carrier diffusion, input current, and temperature in transient turn-off behavior of laser for pulsed operation are analyzed. We also study the thermo-temporal behavior of laser in pulsed operation and determine the effects of input pulse on output power.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124326960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380729
N. Kamat, Oh Chong Khiam, Zhao Si Ping
In this paper, an attempt is made to highlight a new SEM based technique that was used to detect pinholes in the as- deposited/as-grown dielectrics. The fundamental principle governing the technique is discussed. This technique is benchmarked against a well-established fault- isolation technique using the Liquid Crystal. In fact, this technique was found to supplement the Liquid Crystal technique. A case study, discussed in the paper, helps understand the usefulness of the technique especially in detecting defects on as- deposited/as-grown dielectric films.
{"title":"A SEM Based Technique To Detect Pin-holes In As-Deposited/As-Grown Dielectrics","authors":"N. Kamat, Oh Chong Khiam, Zhao Si Ping","doi":"10.1109/SMELEC.2006.380729","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380729","url":null,"abstract":"In this paper, an attempt is made to highlight a new SEM based technique that was used to detect pinholes in the as- deposited/as-grown dielectrics. The fundamental principle governing the technique is discussed. This technique is benchmarked against a well-established fault- isolation technique using the Liquid Crystal. In fact, this technique was found to supplement the Liquid Crystal technique. A case study, discussed in the paper, helps understand the usefulness of the technique especially in detecting defects on as- deposited/as-grown dielectric films.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"715 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115127228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380688
H. Zhe, A. bin A'ain, A. Kordesch
This work will explore the integration of a class-F power amplifier using CMOS technology. At 2.4 GHz, the fully integrated on-chip CMOS power amplifier can deliver 21.8 dBm output power with 43.95% efficiency. The design makes use of the C18 RF models provided by Silterra and design of spiral inductor using commercial synthesis software.
{"title":"An Integrated 2.4GHz CMOS Class F Power Amplifier","authors":"H. Zhe, A. bin A'ain, A. Kordesch","doi":"10.1109/SMELEC.2006.380688","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380688","url":null,"abstract":"This work will explore the integration of a class-F power amplifier using CMOS technology. At 2.4 GHz, the fully integrated on-chip CMOS power amplifier can deliver 21.8 dBm output power with 43.95% efficiency. The design makes use of the C18 RF models provided by Silterra and design of spiral inductor using commercial synthesis software.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123563436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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