Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532033
F. Pozzobon, D. Paci, G. Pizzo, A. Buri, S. Morin, F. Carace, A. Andreini, D. Gastaldi, E. Bertarelli, R. Lucchini, P. Vena
In this work a combined experimental/numerical approach to describe the thermo-mechanical behavior of power devices under repetitive power pulsing is presented. Stress tests have been carried out on power DMOS implemented in Smart Power BCD technology with different Back-End Of Line (BEOL) schemes, including, for the first time, full Copper. Mechanical laboratory nano-indentation tests have been used to determine constituent properties of the metal layers. Thermo-mechanical 3D FEM modeling has been used to simulate a multi-cycle thermal loading of a whole power device with its package. Results from simulation have been qualitatively compared to experimental results.
{"title":"Reliability characterization and FEM modeling of power devices under repetitive power pulsing","authors":"F. Pozzobon, D. Paci, G. Pizzo, A. Buri, S. Morin, F. Carace, A. Andreini, D. Gastaldi, E. Bertarelli, R. Lucchini, P. Vena","doi":"10.1109/IRPS.2013.6532033","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532033","url":null,"abstract":"In this work a combined experimental/numerical approach to describe the thermo-mechanical behavior of power devices under repetitive power pulsing is presented. Stress tests have been carried out on power DMOS implemented in Smart Power BCD technology with different Back-End Of Line (BEOL) schemes, including, for the first time, full Copper. Mechanical laboratory nano-indentation tests have been used to determine constituent properties of the metal layers. Thermo-mechanical 3D FEM modeling has been used to simulate a multi-cycle thermal loading of a whole power device with its package. Results from simulation have been qualitatively compared to experimental results.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532101
Dmitry Veksler, G. Bersuker, L. Vandelli, A. Padovani, L. Larcher, A. Muraviev, Bhaswar Chakrabarti, Eric M. Vogel, David Gilmer, Paul Kirsch
The random telegraph noise (RTN) related read instability in resistive random access memory (RRAM) is evaluated by employing the RTN peak-to-peak (P-p) amplitude as a figure of merit (FoM). Variation of the FoM value over multiple set/reset cycles is found to follow the log-normal distribution. P-p decreases with the reduction of the read current, which allows scaling of the RRAM operating current. The RTN effect is attributed to the mechanism of activation/deactivation of the electron traps in (in HRS) or near (in LRS) the filament that affects the current through the RRAM device.
{"title":"Random telegraph noise (RTN) in scaled RRAM devices","authors":"Dmitry Veksler, G. Bersuker, L. Vandelli, A. Padovani, L. Larcher, A. Muraviev, Bhaswar Chakrabarti, Eric M. Vogel, David Gilmer, Paul Kirsch","doi":"10.1109/IRPS.2013.6532101","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532101","url":null,"abstract":"The random telegraph noise (RTN) related read instability in resistive random access memory (RRAM) is evaluated by employing the RTN peak-to-peak (P-p) amplitude as a figure of merit (FoM). Variation of the FoM value over multiple set/reset cycles is found to follow the log-normal distribution. P-p decreases with the reduction of the read current, which allows scaling of the RRAM operating current. The RTN effect is attributed to the mechanism of activation/deactivation of the electron traps in (in HRS) or near (in LRS) the filament that affects the current through the RRAM device.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116030918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532018
A. Shluger, K. McKenna
Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. The ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge. We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behavior. These models are related to physical characterization of degradation processes in CMOS devices.
{"title":"Models of oxygen vacancy defects involved in degradation of gate dielectrics","authors":"A. Shluger, K. McKenna","doi":"10.1109/IRPS.2013.6532018","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532018","url":null,"abstract":"Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. The ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge. We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behavior. These models are related to physical characterization of degradation processes in CMOS devices.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123527673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532068
M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang
This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (ΔID/ID) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, Wfin and longer Leff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra ~16% variations in cell stability (at Vdd = 0.3V) and additional ~80mV variation in offset voltage for sense amplifiers at Vdd = 0.5V.
{"title":"Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell, and sense amplifiers","authors":"M. Fan, V. Hu, Yin-Nien Chen, P. Su, C. Chuang","doi":"10.1109/IRPS.2013.6532068","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532068","url":null,"abstract":"This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (ΔID/ID) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, Wfin and longer Leff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra ~16% variations in cell stability (at Vdd = 0.3V) and additional ~80mV variation in offset voltage for sense amplifiers at Vdd = 0.5V.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128260666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532040
F. Chen, Heng-Yuan Lee, Yu-Sheng Chen, S. Z. Rahaman, Chen-Han Tsai, K. Tsai, T. Wu, Weisu Chen, P. Gu, Yu-De Lin, S. Sheu, M. Tsai, Li-heng Lee, T. Ku, Pang-Shiu Chen
Resistive random access memory (RRAM) is a promising new non-volatile memory technology capable of operating at low power as well as high speed. Although RRAM is capable of lower energy consumption and substantially more cycles than Flash memory, comprehending and maintaining its ability to store data under stressed conditions remains the key challenge for mainstream acceptance. This in large part is due to the filamentary nature of the RRAM element at the nanoscale. A filament-based resistive memory is based on the formation of current-conducting path (filaments) from defects, e.g., oxygen vacancies. The defects often lead to trap-limited current conduction. Without proper process control or RESET algorithms, unwanted defects may be added near the filaments under device stress, further aggravating the resistance instabilities.
{"title":"Resistance instabilities in a filament-based resistive memory","authors":"F. Chen, Heng-Yuan Lee, Yu-Sheng Chen, S. Z. Rahaman, Chen-Han Tsai, K. Tsai, T. Wu, Weisu Chen, P. Gu, Yu-De Lin, S. Sheu, M. Tsai, Li-heng Lee, T. Ku, Pang-Shiu Chen","doi":"10.1109/IRPS.2013.6532040","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532040","url":null,"abstract":"Resistive random access memory (RRAM) is a promising new non-volatile memory technology capable of operating at low power as well as high speed. Although RRAM is capable of lower energy consumption and substantially more cycles than Flash memory, comprehending and maintaining its ability to store data under stressed conditions remains the key challenge for mainstream acceptance. This in large part is due to the filamentary nature of the RRAM element at the nanoscale. A filament-based resistive memory is based on the formation of current-conducting path (filaments) from defects, e.g., oxygen vacancies. The defects often lead to trap-limited current conduction. Without proper process control or RESET algorithms, unwanted defects may be added near the filaments under device stress, further aggravating the resistance instabilities.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129628677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532115
I. Chatterjee, E. Zhang, B. Bhuva, D. Fleetwood, Y. Fang, A. Oates
Ultra-small bulk FinFETs (dual-well and triple-well) from a commercial process have been exposed to total ionizing dose. The devices have varying numbers of fins and channel length. The devices show a significant increase in off-state leakage current, threshold voltage shift, transconductance and subthreshold slope degradation after irradiation to 300 krad(SiO2). The results also show a strong dependence of fin-to-fin variation and trapped charge in the STI on the radiation response of the devices.
{"title":"Length and fin number dependence of ionizing radiation-induced degradation in bulk FinFETs","authors":"I. Chatterjee, E. Zhang, B. Bhuva, D. Fleetwood, Y. Fang, A. Oates","doi":"10.1109/IRPS.2013.6532115","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532115","url":null,"abstract":"Ultra-small bulk FinFETs (dual-well and triple-well) from a commercial process have been exposed to total ionizing dose. The devices have varying numbers of fins and channel length. The devices show a significant increase in off-state leakage current, threshold voltage shift, transconductance and subthreshold slope degradation after irradiation to 300 krad(SiO2). The results also show a strong dependence of fin-to-fin variation and trapped charge in the STI on the radiation response of the devices.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531998
V. Huard, F. Cacho, L. Claramond, P. Alves, W. Dalkowski, D. Jacquet, S. Lecomte, M. Tan, B. Delemer, A. Kamoun, V. Fraisse
This paper deals with the challenge of optimizing the performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications in advanced CMOS nodes. Both the increased impact of electrical reliability degradation and an increased thermal runaway risk require a dedicated approach combining product engineering and high-level modeling approach to achieve optimal reliability guardband determination even in the case of numerous, discrete V-F operating modes and their related mission profiles.
{"title":"Advances in industrial practices for optimal performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications","authors":"V. Huard, F. Cacho, L. Claramond, P. Alves, W. Dalkowski, D. Jacquet, S. Lecomte, M. Tan, B. Delemer, A. Kamoun, V. Fraisse","doi":"10.1109/IRPS.2013.6531998","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531998","url":null,"abstract":"This paper deals with the challenge of optimizing the performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications in advanced CMOS nodes. Both the increased impact of electrical reliability degradation and an increased thermal runaway risk require a dedicated approach combining product engineering and high-level modeling approach to achieve optimal reliability guardband determination even in the case of numerous, discrete V-F operating modes and their related mission profiles.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130044905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531941
P. M. Lee
This paper provides a historical background of the first developments of compact modeling for circuit-level reliability simulation at UC Berkeley, and the subsequent implementation into the BERT reliability simulator more than 20 years ago. A brief description of the advancement in the technology since then is given, and some industrial perspectives are summarized concerning how such a tool can be used to effectively optimize product design while ensuring reliability, as well as clarifying issues which still remain in the industrial design environment.
{"title":"Compact modeling for simulation of circuit reliability: Historical and industrial perspectives","authors":"P. M. Lee","doi":"10.1109/IRPS.2013.6531941","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531941","url":null,"abstract":"This paper provides a historical background of the first developments of compact modeling for circuit-level reliability simulation at UC Berkeley, and the subsequent implementation into the BERT reliability simulator more than 20 years ago. A brief description of the advancement in the technology since then is given, and some industrial perspectives are summarized concerning how such a tool can be used to effectively optimize product design while ensuring reliability, as well as clarifying issues which still remain in the industrial design environment.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129156035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532043
T. Diokh, E. Le-Roux, S. Jeannot, M. Gros-Jean, P. Candelier, J. Nodin, V. Jousseaume, L. Perniola, H. Grampeix, T. Cabout, E. Jalaguier, M. Guillermet, B. De Salvo
In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.
{"title":"Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO2-RRAM integrated in a 65nm CMOS technology","authors":"T. Diokh, E. Le-Roux, S. Jeannot, M. Gros-Jean, P. Candelier, J. Nodin, V. Jousseaume, L. Perniola, H. Grampeix, T. Cabout, E. Jalaguier, M. Guillermet, B. De Salvo","doi":"10.1109/IRPS.2013.6532043","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532043","url":null,"abstract":"In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532117
S. Desai, S. Mukhopadhyay, N. Goel, N. Nanaware, B. Jose, K. Joshi, S. Mahapatra
A comprehensive NBTI framework using the H/H2 RD model for interface traps and 2 well model for hole traps has been proposed and used to predict DC and AC experiments. The framework is validated against experimental data from different DC stress and recovery conditions, AC frequency and duty cycle, measurement speed, and across SiON and HKMG devices having different gate insulator processes. Limitations of the alternative 2 stage model framework is discussed.
{"title":"A comprehensive AC / DC NBTI model: Stress, recovery, frequency, duty cycle and process dependence","authors":"S. Desai, S. Mukhopadhyay, N. Goel, N. Nanaware, B. Jose, K. Joshi, S. Mahapatra","doi":"10.1109/IRPS.2013.6532117","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532117","url":null,"abstract":"A comprehensive NBTI framework using the H/H2 RD model for interface traps and 2 well model for hole traps has been proposed and used to predict DC and AC experiments. The framework is validated against experimental data from different DC stress and recovery conditions, AC frequency and duty cycle, measurement speed, and across SiON and HKMG devices having different gate insulator processes. Limitations of the alternative 2 stage model framework is discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132685615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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