Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532074
S. Parthasarathy, J. Salcedo, J. Hajjar
A low-leakage, low triggering polysilicon bounded SCR design is introduced for on-chip electrostatic discharge (ESD) protection in CMOS applications. The advantages of replacing the shallow trench isolation (STI) with a polysilicon gate in the device formation are discussed. The device response to fast transients, emulating ESD CDM-type events, is discussed through VFTLP measurements. The low-leakage characteristics of the SCR clamp are also demonstrated via high temperature measurements.
{"title":"A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process","authors":"S. Parthasarathy, J. Salcedo, J. Hajjar","doi":"10.1109/IRPS.2013.6532074","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532074","url":null,"abstract":"A low-leakage, low triggering polysilicon bounded SCR design is introduced for on-chip electrostatic discharge (ESD) protection in CMOS applications. The advantages of replacing the shallow trench isolation (STI) with a polysilicon gate in the device formation are discussed. The device response to fast transients, emulating ESD CDM-type events, is discussed through VFTLP measurements. The low-leakage characteristics of the SCR clamp are also demonstrated via high temperature measurements.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130952020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532095
Seung-hwan Song, Jongyeon Kim, C. Kim
N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.
{"title":"Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells","authors":"Seung-hwan Song, Jongyeon Kim, C. Kim","doi":"10.1109/IRPS.2013.6532095","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532095","url":null,"abstract":"N-channel and P-channel single-poly embedded flash (eflash) memory cells were implemented in a standard CMOS logic process. Among the different configurations based on standard I/O devices, the N-channel cell with a PMOS-PMOS-NMOS combo and the P-channel cell with an NMOS-NMOS-PMOS combo were found to be most attractive in terms of program/erase performance, while the cell with a coupling device having P+ poly showed longer retention characteristic than the cells with a coupling device having N+ poly. Negligible program disturbance and floating gate coupling were observed in all cell types.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532027
C. Schmidt, K. Wadhwa, A. Reverdy, E. Reinders
Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an useful method for localizing electrical active defects caused by reliability-related failure mechanism. After a short introduction of the physical principle, several case studies are presented.
{"title":"Localization of electrical active defects caused by reliability-related failure mechanism by the application of Lock-in Thermography","authors":"C. Schmidt, K. Wadhwa, A. Reverdy, E. Reinders","doi":"10.1109/IRPS.2013.6532027","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532027","url":null,"abstract":"Within this paper, the method of Lock-in Thermography (LIT) is presented and introduced as an useful method for localizing electrical active defects caused by reliability-related failure mechanism. After a short introduction of the physical principle, several case studies are presented.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128857631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532049
L. Michalas, M. Koutsoureli, E. Papandreou, G. Papaioannou, S. Saada, C. Mer, R. Hugon, P. Bergonzo, A. Leuliet, P. Martins, S. Bansropun, A. Ziaei
Diamond films are considered as superior dielectric in comparison to Si3N4 for MEMS applications. The present paper provides a detail characterization study of electrical properties of undoped microcrystalline diamond films involving dc and charge/discharge transient analysis over a wide temperature range. The aim of the study is to provide a better insight on the physical mechanisms responsible for the charge injection and collection processes under different operation conditions applicable to MEMS capacitive switches.
{"title":"Electrical characterization of undoped diamond films for RF MEMS application","authors":"L. Michalas, M. Koutsoureli, E. Papandreou, G. Papaioannou, S. Saada, C. Mer, R. Hugon, P. Bergonzo, A. Leuliet, P. Martins, S. Bansropun, A. Ziaei","doi":"10.1109/IRPS.2013.6532049","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532049","url":null,"abstract":"Diamond films are considered as superior dielectric in comparison to Si3N4 for MEMS applications. The present paper provides a detail characterization study of electrical properties of undoped microcrystalline diamond films involving dc and charge/discharge transient analysis over a wide temperature range. The aim of the study is to provide a better insight on the physical mechanisms responsible for the charge injection and collection processes under different operation conditions applicable to MEMS capacitive switches.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532097
M. Zahid, R. Degraeve, L. Breuil, G. Van den bosch, J. van Houdt
Scaling of floating gate NAND flash will require switching from conventional control gate wrap-around cells to fully planar memory cells. Due to the low coupling ratio of these cells, a high work function metal on top of Si, together with a high-k Inter-Gate Dielectric (IGD) are required. In this work we study the performance and instability of high-κ IGD, in combination with or without Al2O3 in hybrid floating gate stack for future application in NAND flash memory and compare it to a single Al2O3 IGD. We use Post-Program and Erase discharge to study the program/erase transients as well as the instability. Results show that by replacing single Al2O3 IGD by a low thermal budget HfAlO or by a multilayer IGD combining low-κ / high-κ / low-κ where high-κ is HfO2 and low-κ is Al2O3 show strong improvement in term of program/erase level and instability, thus a good IGD/CG interface control.
{"title":"Instability study of high-κ Inter-Gate Dielectric stacks on hybrid floating gate flash memory","authors":"M. Zahid, R. Degraeve, L. Breuil, G. Van den bosch, J. van Houdt","doi":"10.1109/IRPS.2013.6532097","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532097","url":null,"abstract":"Scaling of floating gate NAND flash will require switching from conventional control gate wrap-around cells to fully planar memory cells. Due to the low coupling ratio of these cells, a high work function metal on top of Si, together with a high-k Inter-Gate Dielectric (IGD) are required. In this work we study the performance and instability of high-κ IGD, in combination with or without Al<sub>2</sub>O<sub>3</sub> in hybrid floating gate stack for future application in NAND flash memory and compare it to a single Al<sub>2</sub>O<sub>3</sub> IGD. We use Post-Program and Erase discharge to study the program/erase transients as well as the instability. Results show that by replacing single Al<sub>2</sub>O<sub>3</sub> IGD by a low thermal budget HfAlO or by a multilayer IGD combining low-κ / high-κ / low-κ where high-κ is HfO<sub>2</sub> and low-κ is Al<sub>2</sub>O<sub>3</sub> show strong improvement in term of program/erase level and instability, thus a good IGD/CG interface control.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126774317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532041
B. Traoré, K. Xue, E. Vianello, G. Molas, P. Blaise, B. De Salvo, A. Padovani, O. Pirrotta, L. Larcher, L. Fonseca, Y. Nishi
In this work we investigate in detail the effects of metal electrodes on the retention performances of HfOx RRAM devices. Motivated by our experimental data, we employ physics-based RRAM modeling and first-principles calculations to show that during the ON-state the concentration of oxygen interstitial (Oi) ions in the oxide depends significantly on the metal electrodes, being much larger for RRAM devices with Pt electrodes compared with Ti. The lower Oi concentration in HfOx with Ti electrodes, known as a strong oxygen getter material, results in improved retention and thermal stability. The presence of oxygen deficient conductive filaments explains the data.
{"title":"Investigation of the role of electrodes on the retention performance of HfOx based RRAM cells by experiments, atomistic simulations and device physical modeling","authors":"B. Traoré, K. Xue, E. Vianello, G. Molas, P. Blaise, B. De Salvo, A. Padovani, O. Pirrotta, L. Larcher, L. Fonseca, Y. Nishi","doi":"10.1109/IRPS.2013.6532041","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532041","url":null,"abstract":"In this work we investigate in detail the effects of metal electrodes on the retention performances of HfOx RRAM devices. Motivated by our experimental data, we employ physics-based RRAM modeling and first-principles calculations to show that during the ON-state the concentration of oxygen interstitial (Oi) ions in the oxide depends significantly on the metal electrodes, being much larger for RRAM devices with Pt electrodes compared with Ti. The lower Oi concentration in HfOx with Ti electrodes, known as a strong oxygen getter material, results in improved retention and thermal stability. The presence of oxygen deficient conductive filaments explains the data.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126529690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532107
Jae-Gyung Ahn, Ming Feng Lu, P. Yeh, J. Chang, Xin Wu, S. Pai
A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology, contributions from each block and each failure mechanism were quantitatively identified. It was shown that, at the target time-to-failure (TTF), gate dielectric (GD) TDDB takes the biggest portion of the failure rate, but the first failure comes with EM.
{"title":"Product-Level Reliability Estimator with advanced CMOS technology","authors":"Jae-Gyung Ahn, Ming Feng Lu, P. Yeh, J. Chang, Xin Wu, S. Pai","doi":"10.1109/IRPS.2013.6532107","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532107","url":null,"abstract":"A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology, contributions from each block and each failure mechanism were quantitatively identified. It was shown that, at the target time-to-failure (TTF), gate dielectric (GD) TDDB takes the biggest portion of the failure rate, but the first failure comes with EM.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126597365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531963
E. Kolawa, Yuan Chen, Mohammad Mojarradi, C. Weber, Don J. Hunter
This paper describes the technology development and infusion of a motor drive electronics assembly for Mars Curiosity Rover under space extreme environments. The technology evaluation and qualification as well as space qualification of the assembly are described and summarized. Because of the uncertainty of the technologies operating under the extreme space environments and that a high level of reliability was required for this assembly application, both component and assembly board level qualifications were performed.
{"title":"A motor drive electronics assembly for Mars Curiosity Rover: An example of assembly qualification for extreme environments","authors":"E. Kolawa, Yuan Chen, Mohammad Mojarradi, C. Weber, Don J. Hunter","doi":"10.1109/IRPS.2013.6531963","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531963","url":null,"abstract":"This paper describes the technology development and infusion of a motor drive electronics assembly for Mars Curiosity Rover under space extreme environments. The technology evaluation and qualification as well as space qualification of the assembly are described and summarized. Because of the uncertainty of the technologies operating under the extreme space environments and that a high level of reliability was required for this assembly application, both component and assembly board level qualifications were performed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122238940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532124
X. Federspiel, M. Rafik, D. Angot, F. Cacho, D. Roy
In this paper we review experiments combining several types of FET devices degradation modes, including HCI, bias and unbiased BTI. We analyze the nature and localization of defect issued from these degradation processes and derive rules governing interaction between defect generation process, drain polarization dependency on BTI degradation as well as potential BTI contribution to HCI degradation. Consequences of BTI - HCI interaction on WLR analysis as well as product operation will be discussed.
{"title":"Interaction between BTI and HCI degradation in High-K devices","authors":"X. Federspiel, M. Rafik, D. Angot, F. Cacho, D. Roy","doi":"10.1109/IRPS.2013.6532124","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532124","url":null,"abstract":"In this paper we review experiments combining several types of FET devices degradation modes, including HCI, bias and unbiased BTI. We analyze the nature and localization of defect issued from these degradation processes and derive rules governing interaction between defect generation process, drain polarization dependency on BTI degradation as well as potential BTI contribution to HCI degradation. Consequences of BTI - HCI interaction on WLR analysis as well as product operation will be discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531949
Shih-Yu Wang, Yong-Han He, Chieh-Wei He, Hao-Chan Huang, Yao-Wen Chang, T. Lu, Kuang-Chao Chen, Chih-Yuan Lu
An enhanced PMOS-triggered PMLSCR is proposed. Under the condition that both PNP and NPN BJT's are triggered simultaneously, voltage overshoot and turn-on uniformity can be further improved. From TCAD simulation, it is clear that with the help of trigger current, conduction path of SCR goes deeper and snapback voltage is reduced. By the designed power sequence, holding voltage and current of SCR devices considering self-heating effect are attained. Robust EOS immunity can be assured accordingly.
{"title":"Enhanced PMOS-triggered PMLSCR with robust EOS immunity","authors":"Shih-Yu Wang, Yong-Han He, Chieh-Wei He, Hao-Chan Huang, Yao-Wen Chang, T. Lu, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/IRPS.2013.6531949","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531949","url":null,"abstract":"An enhanced PMOS-triggered PMLSCR is proposed. Under the condition that both PNP and NPN BJT's are triggered simultaneously, voltage overshoot and turn-on uniformity can be further improved. From TCAD simulation, it is clear that with the help of trigger current, conduction path of SCR goes deeper and snapback voltage is reduced. By the designed power sequence, holding voltage and current of SCR devices considering self-heating effect are attained. Robust EOS immunity can be assured accordingly.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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