Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532070
T. Maloney, Lei Jiang, S. Poon, K. Kolluru
A feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) pulses predicts a temperature waveform and its stability given a heat source function and a thermoelectric circuit model or thermal impulse response Z(t). The pulse delivery circuit influences those conditions along with materials and layout. Z(t) can be extracted from pre-silicon modeling (e.g., finite element) or from post-silicon transmission line pulse (TLP) response, then applied to any ESD pulse conditions. For metal lines embedded in a patterned matrix of inactive metal lines at adjoining levels, pulses produce temperatures converging to a constant value, so the related time constants allow thermal impedance Z(t) to be deduced and thermal properties of the materials checked.
{"title":"Achieving electrothermal stability in interconnect metal during ESD pulses","authors":"T. Maloney, Lei Jiang, S. Poon, K. Kolluru","doi":"10.1109/IRPS.2013.6532070","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532070","url":null,"abstract":"A feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) pulses predicts a temperature waveform and its stability given a heat source function and a thermoelectric circuit model or thermal impulse response Z(t). The pulse delivery circuit influences those conditions along with materials and layout. Z(t) can be extracted from pre-silicon modeling (e.g., finite element) or from post-silicon transmission line pulse (TLP) response, then applied to any ESD pulse conditions. For metal lines embedded in a patterned matrix of inactive metal lines at adjoining levels, pulses produce temperatures converging to a constant value, so the related time constants allow thermal impedance Z(t) to be deduced and thermal properties of the materials checked.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531944
C. Yilmaz, L. Heiß, C. Werner, D. Schmitt-Landsiedel
In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔVth-shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔVth shift.
{"title":"Modeling of NBTI-recovery effects in analog CMOS circuits","authors":"C. Yilmaz, L. Heiß, C. Werner, D. Schmitt-Landsiedel","doi":"10.1109/IRPS.2013.6531944","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531944","url":null,"abstract":"In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔVth-shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔVth shift.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532063
J. Velamala, K. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Yu Cao
Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.
{"title":"Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction","authors":"J. Velamala, K. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Yu Cao","doi":"10.1109/IRPS.2013.6532063","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532063","url":null,"abstract":"Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116048410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531975
V. Huard, F. Cacho, X. Federspiel
This work provides elements to highlight the reliability challenges related to the technology scaling in the multicore era. Through main milestones including device reliability scaling models, single-core scaling model and multicore chip organization and scaling models, the reliability impact on the speedup potential of multiprocessors for a set of parallel real workloads is assessed. The main conclusion of this study is to highlight the fact that the “free lunch” for overdrive conditions is soon to be over.
{"title":"Technology scaling and reliability challenges in the multicore era","authors":"V. Huard, F. Cacho, X. Federspiel","doi":"10.1109/IRPS.2013.6531975","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531975","url":null,"abstract":"This work provides elements to highlight the reliability challenges related to the technology scaling in the multicore era. Through main milestones including device reliability scaling models, single-core scaling model and multicore chip organization and scaling models, the reliability impact on the speedup potential of multiprocessors for a set of parallel real workloads is assessed. The main conclusion of this study is to highlight the fact that the “free lunch” for overdrive conditions is soon to be over.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531965
A. Haggag, A. Barr, K. Walker, L. Winemberg
We have demonstrated that the raw failure rate from field data decreases much faster than any realistic statistical reliability model due to the artifact that we are also adding parts into the field as time passes. We have shown with a simple mathematical correction we can get real FIT that behaves as expected from realistic statistical reliability model. This methodology for hard failure rate estimation can also be applied for soft failure rate estimation using “NTF” or “No Trouble Found” field returns that are believed marginal parts. Since the next generation technology may be more sensitive to soft failures than the current generation, it is critical to get both hard and soft failure rate estimates, to allow design for reliability decisions.
{"title":"Realistic 55nm IC failure in time (FIT) estimates from automotive field returns","authors":"A. Haggag, A. Barr, K. Walker, L. Winemberg","doi":"10.1109/IRPS.2013.6531965","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531965","url":null,"abstract":"We have demonstrated that the raw failure rate from field data decreases much faster than any realistic statistical reliability model due to the artifact that we are also adding parts into the field as time passes. We have shown with a simple mathematical correction we can get real FIT that behaves as expected from realistic statistical reliability model. This methodology for hard failure rate estimation can also be applied for soft failure rate estimation using “NTF” or “No Trouble Found” field returns that are believed marginal parts. Since the next generation technology may be more sensitive to soft failures than the current generation, it is critical to get both hard and soft failure rate estimates, to allow design for reliability decisions.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116451968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531979
S. Tanakamaru, M. Doi, K. Takeuchi
The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.
{"title":"Error-prediction analyses in 1X, 2X and 3Xnm NAND flash memories for system-level reliability improvement of solid-state drives (SSDs)","authors":"S. Tanakamaru, M. Doi, K. Takeuchi","doi":"10.1109/IRPS.2013.6531979","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531979","url":null,"abstract":"The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532008
A. Subirats, X. Garros, J. Mazurier, J. El Husseini, O. Rozeau, G. Reimbold, O. Faynot, G. Ghibaudo
In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages is required to overcome this effect.
{"title":"Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies","authors":"A. Subirats, X. Garros, J. Mazurier, J. El Husseini, O. Rozeau, G. Reimbold, O. Faynot, G. Ghibaudo","doi":"10.1109/IRPS.2013.6532008","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532008","url":null,"abstract":"In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages is required to overcome this effect.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121217765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531972
L. Gerrer, S. Amoroso, P. Asenov, J. Ding, B. Cheng, F. Adamu-Lema, S. Markov, D. Reid, C. Millar, A. Asenov
In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.
{"title":"Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology","authors":"L. Gerrer, S. Amoroso, P. Asenov, J. Ding, B. Cheng, F. Adamu-Lema, S. Markov, D. Reid, C. Millar, A. Asenov","doi":"10.1109/IRPS.2013.6531972","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531972","url":null,"abstract":"In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532069
Jian-Hsing Lee, C. Kung, E. Kung, Dao-Hong Yang, J. Shih
A novel failure mechanism of the high-voltage (HV) product during the negative-current-triggered (NCT) latch-up test is found. From the failure analysis and simulation results, the failure is identified as the unexpected parasitic-bipolar transistors turn-on induced the regulator malfunction to result in the low-voltage (LV) component damage.
{"title":"The internal circuit damage of a high-voltage product during the negative-current-triggered (NCT) latch-up test","authors":"Jian-Hsing Lee, C. Kung, E. Kung, Dao-Hong Yang, J. Shih","doi":"10.1109/IRPS.2013.6532069","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532069","url":null,"abstract":"A novel failure mechanism of the high-voltage (HV) product during the negative-current-triggered (NCT) latch-up test is found. From the failure analysis and simulation results, the failure is identified as the unexpected parasitic-bipolar transistors turn-on induced the regulator malfunction to result in the low-voltage (LV) component damage.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532073
Q. Cui, J. Liou
Electrostatic discharge (ESD) protection structures in GaAs HEMT technology are commonly constructed using either stacked Schottky diode or Single-Gate clamp. Dual-gate pHEMT clamp was also recently reported for its better ESD robustness performance. This paper further develops an improved ESD protection clamp based on a novel drainless, multi-gate pHEMT in 0.5um GaAs pHEMT technology. With similar layout area, the proposed ESD protection clamp can carry much higher current handling ability (5.2-A “It2”, roughly 7.8-kV HBM ESD level) than both the conventional single-gate pHEMT clamp and recently reported dual-gate pHEMT clamp under the human body model (HBM) stress.
{"title":"Novel drain-less multi-gate pHEMT for electrostatic discharge (ESD) protection in GaAs technology","authors":"Q. Cui, J. Liou","doi":"10.1109/IRPS.2013.6532073","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532073","url":null,"abstract":"Electrostatic discharge (ESD) protection structures in GaAs HEMT technology are commonly constructed using either stacked Schottky diode or Single-Gate clamp. Dual-gate pHEMT clamp was also recently reported for its better ESD robustness performance. This paper further develops an improved ESD protection clamp based on a novel drainless, multi-gate pHEMT in 0.5um GaAs pHEMT technology. With similar layout area, the proposed ESD protection clamp can carry much higher current handling ability (5.2-A “It2”, roughly 7.8-kV HBM ESD level) than both the conventional single-gate pHEMT clamp and recently reported dual-gate pHEMT clamp under the human body model (HBM) stress.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128907414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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