Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531976
R. Joshi, R. Kanj, C. Adams, J. Warnock
Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning-of-life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.
{"title":"Making reliable memories in an unreliable world (invited)","authors":"R. Joshi, R. Kanj, C. Adams, J. Warnock","doi":"10.1109/IRPS.2013.6531976","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531976","url":null,"abstract":"Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning-of-life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"127 38","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531979
S. Tanakamaru, M. Doi, K. Takeuchi
The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.
{"title":"Error-prediction analyses in 1X, 2X and 3Xnm NAND flash memories for system-level reliability improvement of solid-state drives (SSDs)","authors":"S. Tanakamaru, M. Doi, K. Takeuchi","doi":"10.1109/IRPS.2013.6531979","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531979","url":null,"abstract":"The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531962
J. Tikkanen, N. Sumikawa, L. Wang, L. Winemberg, M. Abadir
This study analyzes parametric wafer probe test measurements from high quality SoCs for automotive market. This product is a safety critical part that must have a near zero Defective Parts per Million (DPPM) rate. In order to achieve the required quality standard, a comprehensive parametric test set is performed on each part. In very rare occasions, a part with latent defect is identified. The latency of the defect is established through failure analysis after the part is deemed failing. In this paper, we study the possibility of screening such latent defective parts during wafer sort based on its early signature shown on parametric wafer tests. In earlier works, it is shown that multivariate outlier analysis can be used for capturing the rare defective parts (or returns) for a high quality product line [1]. Using parametric wafer probe test measurements, multivariate outlier models are created and applied to preemptively predict potential returns. This paper analyzes three particular returns, starting from its failure analysis report to suggesting a statistical outlier methodology to screen this part. In this full paper, multiple returns with latent defects will be analyzed.
{"title":"Statistical outlier screening for latent defects","authors":"J. Tikkanen, N. Sumikawa, L. Wang, L. Winemberg, M. Abadir","doi":"10.1109/IRPS.2013.6531962","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531962","url":null,"abstract":"This study analyzes parametric wafer probe test measurements from high quality SoCs for automotive market. This product is a safety critical part that must have a near zero Defective Parts per Million (DPPM) rate. In order to achieve the required quality standard, a comprehensive parametric test set is performed on each part. In very rare occasions, a part with latent defect is identified. The latency of the defect is established through failure analysis after the part is deemed failing. In this paper, we study the possibility of screening such latent defective parts during wafer sort based on its early signature shown on parametric wafer tests. In earlier works, it is shown that multivariate outlier analysis can be used for capturing the rare defective parts (or returns) for a high quality product line [1]. Using parametric wafer probe test measurements, multivariate outlier models are created and applied to preemptively predict potential returns. This paper analyzes three particular returns, starting from its failure analysis report to suggesting a statistical outlier methodology to screen this part. In this full paper, multiple returns with latent defects will be analyzed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123484609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532054
T. Uemura, T. Kato, H. Matsuyama
We investigate an impact of parasitic bipolar action on 28nm sequential elements in the terrestrial environment through spallation neutron beam irradiation tests. We discuss the contribution of parasitic bipolar action to the technology trend of SER through neutron tests on Flip-Flops and SRAMs.
{"title":"Impact of parasitic bipolar action and soft-error trend in bulk CMOS at terrestrial environment","authors":"T. Uemura, T. Kato, H. Matsuyama","doi":"10.1109/IRPS.2013.6532054","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532054","url":null,"abstract":"We investigate an impact of parasitic bipolar action on 28nm sequential elements in the terrestrial environment through spallation neutron beam irradiation tests. We discuss the contribution of parasitic bipolar action to the technology trend of SER through neutron tests on Flip-Flops and SRAMs.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129958708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531959
A. Kerber, T. Nigam
Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.
{"title":"Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies","authors":"A. Kerber, T. Nigam","doi":"10.1109/IRPS.2013.6531959","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531959","url":null,"abstract":"Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124885581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532073
Q. Cui, J. Liou
Electrostatic discharge (ESD) protection structures in GaAs HEMT technology are commonly constructed using either stacked Schottky diode or Single-Gate clamp. Dual-gate pHEMT clamp was also recently reported for its better ESD robustness performance. This paper further develops an improved ESD protection clamp based on a novel drainless, multi-gate pHEMT in 0.5um GaAs pHEMT technology. With similar layout area, the proposed ESD protection clamp can carry much higher current handling ability (5.2-A “It2”, roughly 7.8-kV HBM ESD level) than both the conventional single-gate pHEMT clamp and recently reported dual-gate pHEMT clamp under the human body model (HBM) stress.
{"title":"Novel drain-less multi-gate pHEMT for electrostatic discharge (ESD) protection in GaAs technology","authors":"Q. Cui, J. Liou","doi":"10.1109/IRPS.2013.6532073","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532073","url":null,"abstract":"Electrostatic discharge (ESD) protection structures in GaAs HEMT technology are commonly constructed using either stacked Schottky diode or Single-Gate clamp. Dual-gate pHEMT clamp was also recently reported for its better ESD robustness performance. This paper further develops an improved ESD protection clamp based on a novel drainless, multi-gate pHEMT in 0.5um GaAs pHEMT technology. With similar layout area, the proposed ESD protection clamp can carry much higher current handling ability (5.2-A “It2”, roughly 7.8-kV HBM ESD level) than both the conventional single-gate pHEMT clamp and recently reported dual-gate pHEMT clamp under the human body model (HBM) stress.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128907414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532069
Jian-Hsing Lee, C. Kung, E. Kung, Dao-Hong Yang, J. Shih
A novel failure mechanism of the high-voltage (HV) product during the negative-current-triggered (NCT) latch-up test is found. From the failure analysis and simulation results, the failure is identified as the unexpected parasitic-bipolar transistors turn-on induced the regulator malfunction to result in the low-voltage (LV) component damage.
{"title":"The internal circuit damage of a high-voltage product during the negative-current-triggered (NCT) latch-up test","authors":"Jian-Hsing Lee, C. Kung, E. Kung, Dao-Hong Yang, J. Shih","doi":"10.1109/IRPS.2013.6532069","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532069","url":null,"abstract":"A novel failure mechanism of the high-voltage (HV) product during the negative-current-triggered (NCT) latch-up test is found. From the failure analysis and simulation results, the failure is identified as the unexpected parasitic-bipolar transistors turn-on induced the regulator malfunction to result in the low-voltage (LV) component damage.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532063
J. Velamala, K. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Yu Cao
Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.
{"title":"Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction","authors":"J. Velamala, K. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Yu Cao","doi":"10.1109/IRPS.2013.6532063","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532063","url":null,"abstract":"Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete Vth shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where Vdd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging; (3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116048410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532008
A. Subirats, X. Garros, J. Mazurier, J. El Husseini, O. Rozeau, G. Reimbold, O. Faynot, G. Ghibaudo
In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages is required to overcome this effect.
{"title":"Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies","authors":"A. Subirats, X. Garros, J. Mazurier, J. El Husseini, O. Rozeau, G. Reimbold, O. Faynot, G. Ghibaudo","doi":"10.1109/IRPS.2013.6532008","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532008","url":null,"abstract":"In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages is required to overcome this effect.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121217765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531972
L. Gerrer, S. Amoroso, P. Asenov, J. Ding, B. Cheng, F. Adamu-Lema, S. Markov, D. Reid, C. Millar, A. Asenov
In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.
{"title":"Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology","authors":"L. Gerrer, S. Amoroso, P. Asenov, J. Ding, B. Cheng, F. Adamu-Lema, S. Markov, D. Reid, C. Millar, A. Asenov","doi":"10.1109/IRPS.2013.6531972","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531972","url":null,"abstract":"In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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