Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532012
William R. Bottenberg
This paper describes the use of electroluminescence imaging (EL), infra-red imaging (IR), and module shading screen IV techniques to characterize individual cell performance in modules to aid in failure analysis (FA) during the reliability testing of new photovoltaic (PV) module designs. When integrated with detailed modeling into a uniform approach these methods yield a superior approach to understanding failure mechanisms that arise in modules during extended stress testing or analysis from field testing. These techniques are required to quickly assess and validate new materials and new constructions in module technology. Examples are taken from new module technologies such as monolithic module assembly (MMA) for back contact cell modules as well as the use of new materials such as electrically conductive adhesives (ECA) and new encapsulants.
{"title":"Integration of new methods for photovoltaic module reliability performance characterization","authors":"William R. Bottenberg","doi":"10.1109/IRPS.2013.6532012","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532012","url":null,"abstract":"This paper describes the use of electroluminescence imaging (EL), infra-red imaging (IR), and module shading screen IV techniques to characterize individual cell performance in modules to aid in failure analysis (FA) during the reliability testing of new photovoltaic (PV) module designs. When integrated with detailed modeling into a uniform approach these methods yield a superior approach to understanding failure mechanisms that arise in modules during extended stress testing or analysis from field testing. These techniques are required to quickly assess and validate new materials and new constructions in module technology. Examples are taken from new module technologies such as monolithic module assembly (MMA) for back contact cell modules as well as the use of new materials such as electrically conductive adhesives (ECA) and new encapsulants.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531988
F. Soci, A. Chini, G. Meneghesso, M. Meneghini, E. Zanoni
In this paper results obtained by drain current transients measurement on GaN-based high electron mobility transistors (HEMTs) are presented. It will be shown that neglecting device self-heating effects during the calculation process can lead to an underestimation of said energies and to non-overlapping Arrhenius plots, when the emission time constants are extracted at different device dissipated power levels. Thanks to the estimation of the mean channel thermal resistance, thermal effects were taken into account by correcting the measured data. Higher activation energy values have then been extracted and a reasonable overlap of the Arrhenius plots was obtained amongst measurements carried out at different dissipated powers. The experimental results are also suggesting a novel method for the extraction of device thermal resistance, which yielded similar results with respect to other experimental techniques.
{"title":"Influence of device self-heating on trap activation energy extraction","authors":"F. Soci, A. Chini, G. Meneghesso, M. Meneghini, E. Zanoni","doi":"10.1109/IRPS.2013.6531988","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531988","url":null,"abstract":"In this paper results obtained by drain current transients measurement on GaN-based high electron mobility transistors (HEMTs) are presented. It will be shown that neglecting device self-heating effects during the calculation process can lead to an underestimation of said energies and to non-overlapping Arrhenius plots, when the emission time constants are extracted at different device dissipated power levels. Thanks to the estimation of the mean channel thermal resistance, thermal effects were taken into account by correcting the measured data. Higher activation energy values have then been extracted and a reasonable overlap of the Arrhenius plots was obtained amongst measurements carried out at different dissipated powers. The experimental results are also suggesting a novel method for the extraction of device thermal resistance, which yielded similar results with respect to other experimental techniques.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129299917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532050
Sangchae Kim, S. Cunningham, J. McKillop, A. Morris
The characterization of RF MEMS capacitive switch is presented to understand dielectric charging, failure mode, and hold-down lifetime. The characterization included the understanding of beam stiction failure with respect to the voltage at minimum capacitance, VCmin, from low voltage bipolar capacitance-voltage sweep, and the acceleration effect of temperature described by Arrhenius model. The simplified 3 points VCmin method is suggested for dielectric charging detection with low cost and short test time for defective part screening and application in automated test equipment. The hold-down lifetime improved with taller standoff bumps by increasing release voltage and minimizing dielectric charging on the actuator electrode.
{"title":"Characterization of dielectric charging and reliability in capacitive RF MEMS switches","authors":"Sangchae Kim, S. Cunningham, J. McKillop, A. Morris","doi":"10.1109/IRPS.2013.6532050","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532050","url":null,"abstract":"The characterization of RF MEMS capacitive switch is presented to understand dielectric charging, failure mode, and hold-down lifetime. The characterization included the understanding of beam stiction failure with respect to the voltage at minimum capacitance, VCmin, from low voltage bipolar capacitance-voltage sweep, and the acceleration effect of temperature described by Arrhenius model. The simplified 3 points VCmin method is suggested for dielectric charging detection with low cost and short test time for defective part screening and application in automated test equipment. The hold-down lifetime improved with taller standoff bumps by increasing release voltage and minimizing dielectric charging on the actuator electrode.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114094654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532089
Min-Cheng Chen, Hsiao-Chien Chen, Ta-Hsien Lee, Yu-Hsien Lin, Jyun-Hung Shih, Bo-Wei Wang, Y. Hou, Yi-Ju Chen, Chia-Yi Lin, Chang-Hsien Lin, Y. Hsieh, C. Ho, M. Hua, J. Qiu, Tahui Wang, Fu-Liang Yang
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (Vth shift > 60 mV/10-16C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
{"title":"Estimating the detection stability of a Si nanowire sensor using an additional charging electrode","authors":"Min-Cheng Chen, Hsiao-Chien Chen, Ta-Hsien Lee, Yu-Hsien Lin, Jyun-Hung Shih, Bo-Wei Wang, Y. Hou, Yi-Ju Chen, Chia-Yi Lin, Chang-Hsien Lin, Y. Hsieh, C. Ho, M. Hua, J. Qiu, Tahui Wang, Fu-Liang Yang","doi":"10.1109/IRPS.2013.6532089","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532089","url":null,"abstract":"This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (Vth shift > 60 mV/10-16C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532062
M. Saliva, F. Cacho, D. Angot, V. Huard, M. Rafik, A. Bravaix, L. Anghel
Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown. Then a transistor-level model is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and ring oscillator frequency is discussed.
{"title":"Foundations for oxide breakdown compact modeling towards circuit-level simulations","authors":"M. Saliva, F. Cacho, D. Angot, V. Huard, M. Rafik, A. Bravaix, L. Anghel","doi":"10.1109/IRPS.2013.6532062","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532062","url":null,"abstract":"Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown. Then a transistor-level model is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and ring oscillator frequency is discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"23 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114030253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531996
W. Ng, Y. C. Ee, K. Pey, C. S. Tan
With complex process integration approaches and severe fabrication limitations caused by the introduction of new materials and diminishing process margins, there are mounting concerns over possible increased failure rate [1] at the early life cycle (e.g. <;1 year operation) of product use, known as infant mortality failures. A paradigm change in reliability qualification methodology, to aim at understanding the impact of variations on reliability [2-3], is required to ensure that reliability robustness is integrated into the design of the technology to prevent problems from surfacing during product qualification and application. By applying the improved variation control though process Design-For-Reliability (DFR) and engineering optimization methodology as described in Figure 2 and Figure 3, this work aims to establish an effective and efficient method to reduce the infant mortality failure rate of the product, through understanding critical design and process factors and determining the optimal design and process conditions to ensure reliability robustness.
{"title":"Design for reliability through engineering optimization","authors":"W. Ng, Y. C. Ee, K. Pey, C. S. Tan","doi":"10.1109/IRPS.2013.6531996","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531996","url":null,"abstract":"With complex process integration approaches and severe fabrication limitations caused by the introduction of new materials and diminishing process margins, there are mounting concerns over possible increased failure rate [1] at the early life cycle (e.g. <;1 year operation) of product use, known as infant mortality failures. A paradigm change in reliability qualification methodology, to aim at understanding the impact of variations on reliability [2-3], is required to ensure that reliability robustness is integrated into the design of the technology to prevent problems from surfacing during product qualification and application. By applying the improved variation control though process Design-For-Reliability (DFR) and engineering optimization methodology as described in Figure 2 and Figure 3, this work aims to establish an effective and efficient method to reduce the infant mortality failure rate of the product, through understanding critical design and process factors and determining the optimal design and process conditions to ensure reliability robustness.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130160873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532059
K. Maize, E. Heller, D. Dorsey, A. Shakouri
Pulsed thermoreflectance CCD imaging with submicron spatial resolution and 50 millikelvin temperature resolution is used to study fast transient heating in gallium nitride high electron mobility power transistors (GaN HEMTs) on silicon carbide substrate. Transient surface temperature distribution is measured between 50 ns and 100 μs for pulsed power to 19 W/mm. Time evolution of surface temperature for different HEMT regions is analyzed. Significant variation is observed between the thermal rise times for the gate metal, GaN channel, and drain metal. Steady state temperature rise of 68°C on the drain contact metal is reached at 100 μs at 19 W/mm. Observation of time varying thermal gradients in critical HEMT features under fast pulsed operation may help understanding of reliability and failure mechanisms in GaN power transistors.
{"title":"Fast transient thermoreflectance CCD imaging of pulsed self heating in AlGaN/GaN power transistors","authors":"K. Maize, E. Heller, D. Dorsey, A. Shakouri","doi":"10.1109/IRPS.2013.6532059","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532059","url":null,"abstract":"Pulsed thermoreflectance CCD imaging with submicron spatial resolution and 50 millikelvin temperature resolution is used to study fast transient heating in gallium nitride high electron mobility power transistors (GaN HEMTs) on silicon carbide substrate. Transient surface temperature distribution is measured between 50 ns and 100 μs for pulsed power to 19 W/mm. Time evolution of surface temperature for different HEMT regions is analyzed. Significant variation is observed between the thermal rise times for the gate metal, GaN channel, and drain metal. Steady state temperature rise of 68°C on the drain contact metal is reached at 100 μs at 19 W/mm. Observation of time varying thermal gradients in critical HEMT features under fast pulsed operation may help understanding of reliability and failure mechanisms in GaN power transistors.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532075
Chien-Fu Huang, Yi-Feng Chang, Shui-Ming Cheng, Ming-Hsiang Song
A leakage issue induced by Bias Temperature Stress (BTS) is found in a NPN-based ESD clamp. BTS (1.1*Vdd, 125C, 8hrs) can cause an accumulation of drifted ions at an/the STI interface which leads to increased leakage and eventual device failure. TCAD simulation and activation energy extraction model are used to explain the mechanism and two solutions are proposed.
{"title":"Bias Temperature Stress (BTS) induced ESD device's leakage issue and Its preventing solutions in smart power technology","authors":"Chien-Fu Huang, Yi-Feng Chang, Shui-Ming Cheng, Ming-Hsiang Song","doi":"10.1109/IRPS.2013.6532075","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532075","url":null,"abstract":"A leakage issue induced by Bias Temperature Stress (BTS) is found in a NPN-based ESD clamp. BTS (1.1*Vdd, 125C, 8hrs) can cause an accumulation of drifted ions at an/the STI interface which leads to increased leakage and eventual device failure. TCAD simulation and activation energy extraction model are used to explain the mechanism and two solutions are proposed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"430 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134089910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532082
J. Martín-Martínez, A. Crespo-Yepes, R. Rodríguez, M. Nafría, C. G. Almudever, A. Rubio
In this paper, a new device concept, called hereafter memFET, is presented. The memFET exploits in MOSFETs the reversibility property of the dielectric breakdown (BD) in some materials, so that the potential device functionality is enlarged when compared to MIS/MIM structures. The memFET can be used to implement logic functions and memory blocks into a crossbar structure, allowing the dynamic logic configuration of the crossbar, opening paths to new adaptive computing hardware and fault-tolerant systems.
{"title":"memFET: From gate dielectric breakdown to system reconfigurability","authors":"J. Martín-Martínez, A. Crespo-Yepes, R. Rodríguez, M. Nafría, C. G. Almudever, A. Rubio","doi":"10.1109/IRPS.2013.6532082","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532082","url":null,"abstract":"In this paper, a new device concept, called hereafter memFET, is presented. The memFET exploits in MOSFETs the reversibility property of the dielectric breakdown (BD) in some materials, so that the potential device functionality is enlarged when compared to MIS/MIM structures. The memFET can be used to implement logic functions and memory blocks into a crossbar structure, allowing the dynamic logic configuration of the crossbar, opening paths to new adaptive computing hardware and fault-tolerant systems.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131250079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532020
N. Raghavan, A. Padovani, X. Wu, K. Shubhakar, M. Bosman, L. Larcher, K. Pey
Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2/SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ-interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above/below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Å stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.
{"title":"The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks","authors":"N. Raghavan, A. Padovani, X. Wu, K. Shubhakar, M. Bosman, L. Larcher, K. Pey","doi":"10.1109/IRPS.2013.6532020","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532020","url":null,"abstract":"Post breakdown (BD) reliability is an important area of study in ultra-thin gate dielectrics as it has significant implications on the performance degradation, lifetime, reliability margin and power dissipation of advanced sub-22 nm transistors and circuits. A prolonged phase of post-BD can ensure we can live with the circuit with moderate performance and error-free operation, even if the soft breakdown (SBD) events occur early. While analysis of post-BD is simple and straightforward for single layer SiO2/SiON stacks, the number of possible scenarios of post-BD increases when analyzing high-κ-interfacial layer (HK-IL) based technology. This is because the sequence of BD (whether HK or IL fails first followed by the other one) and the competition between multiple SBD in one of these layers, dilative wear-out of a single SBD spot and the possibility of a successive localized BD above/below the HK/IL BD percolation spot (with or without metal filamentation) are all possible phenomena that can be classified as post-BD. The likelihood of occurrence of these various possibilities will determine the immunity of the stack to post-BD degradation. We will investigate each of these scenarios in detail in this work in order to provide a comprehensive assessment of post-BD reliability of state-of-the-art technology. Our analysis on a HK:IL = 25:12Å stack supported by electrical, physical and modeling results provides clear evidence that circuit failure at operating conditions can only be due to multiple SBD events within the IL layer and that the HK is very robust and resilient to breakdown.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115787977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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