Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531983
G. Meneghesso, A. Zanandrea, A. Stocco, I. Rossetto, C. de Santi, F. Rampazzo, M. Meneghini, E. Zanoni, Eldad Bahat Treidel, O. Hilt, P. Ivo, J. Wuerfl
We report on an extensive study of single- (SH) and double-heterostructure (DH) HEMTs based on gallium nitride, for power switching applications. The analysis is based on dc, pulsed and breakdown measurements, which were carried out on five different epitaxial structures.
{"title":"GaN-HEMTs devices with single- and double-heterostructure for power switching applications","authors":"G. Meneghesso, A. Zanandrea, A. Stocco, I. Rossetto, C. de Santi, F. Rampazzo, M. Meneghini, E. Zanoni, Eldad Bahat Treidel, O. Hilt, P. Ivo, J. Wuerfl","doi":"10.1109/IRPS.2013.6531983","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531983","url":null,"abstract":"We report on an extensive study of single- (SH) and double-heterostructure (DH) HEMTs based on gallium nitride, for power switching applications. The analysis is based on dc, pulsed and breakdown measurements, which were carried out on five different epitaxial structures.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531951
M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K. Yeap, E. Zschech
Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 mA/μm2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature towards 200°C for Cu-based interconnects. This suggests that the electromigration downstream early failure mechanism is shifting from a mix of nucleation-controlled (n = 2) and growth-controlled (n = 1) to a fully growth-controlled mode, assisted by the increased thermal stress at lower temperatures (especially at use conditions). For Cu(Mn)-based interconnects, a drop from n = 2.00±0.07 to n = 1.64±0.2 was found, indicating additional effects of a superimposed incubation time. Furthermore, at lower current densities, the Ea value seems to drop for both Cu and Cu(Mn) interconnects by a slight, but significant amount of 0.1 - 0.2eV. Implications for extrapolations of accelerated test data to use conditions are discussed. Furthermore, the scaling behavior of the early failure population at the NSD=-3 level (F~0.1%) was analyzed, spanning 90, 65, 45, 40 and 28 nm technology nodes.
{"title":"Electromigration early failure void nucleation and growth phenomena in Cu and Cu(Mn) interconnects","authors":"M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K. Yeap, E. Zschech","doi":"10.1109/IRPS.2013.6531951","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531951","url":null,"abstract":"Electromigration early failure void nucleation and growth phenomena were studied using large-scale, statistical analysis methods. A total of about 496,000 interconnects were tested over a wide current density and temperature range (j = 3.4 to 41.2 mA/μm2, T = 200 to 350°C) to analyze the detailed behavior of the current density exponent n and the activation energy Ea. The results for the critical V1M1 downstream interface indicate a reduction from n = 1.55±0.10 to n = 1.15±0.15 when lowering the temperature towards 200°C for Cu-based interconnects. This suggests that the electromigration downstream early failure mechanism is shifting from a mix of nucleation-controlled (n = 2) and growth-controlled (n = 1) to a fully growth-controlled mode, assisted by the increased thermal stress at lower temperatures (especially at use conditions). For Cu(Mn)-based interconnects, a drop from n = 2.00±0.07 to n = 1.64±0.2 was found, indicating additional effects of a superimposed incubation time. Furthermore, at lower current densities, the Ea value seems to drop for both Cu and Cu(Mn) interconnects by a slight, but significant amount of 0.1 - 0.2eV. Implications for extrapolations of accelerated test data to use conditions are discussed. Furthermore, the scaling behavior of the early failure population at the NSD=-3 level (F~0.1%) was analyzed, spanning 90, 65, 45, 40 and 28 nm technology nodes.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117007211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531966
K. Yeap, M. Gall, C. Sander, S. Niese, Z. Liao, Y. Ritz, R. Rosenkranz, U. Muhle, J. Gluch, E. Zschech, O. Aubel, A. Beyer, C. Hennesthal, M. Hauschildt, G. Talut, J. Poppe, N. Vogel, H. Engelmann, D. Stauffer, R. Major, O. Warren
This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.
{"title":"An experimental methodology for the in-situ observation of the time-dependent dielectric breakdown mechanism in Copper/low-k on-chip interconnect structures","authors":"K. Yeap, M. Gall, C. Sander, S. Niese, Z. Liao, Y. Ritz, R. Rosenkranz, U. Muhle, J. Gluch, E. Zschech, O. Aubel, A. Beyer, C. Hennesthal, M. Hauschildt, G. Talut, J. Poppe, N. Vogel, H. Engelmann, D. Stauffer, R. Major, O. Warren","doi":"10.1109/IRPS.2013.6531966","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531966","url":null,"abstract":"This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117050761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532036
C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn
This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.
{"title":"Self-heat reliability considerations on Intel's 22nm Tri-Gate technology","authors":"C. Prasad, L. Jiang, D. Singh, M. Agostinelli, C. Auth, P. Bai, T. Eiles, J. Hicks, C. Jan, K. Mistry, S. Natarajan, B. Niu, P. Packan, D. Pantuso, I. Post, S. Ramey, A. Schmitz, B. Sell, S. Suthram, J. Thomas, C. Tsai, P. Vandervoorn","doi":"10.1109/IRPS.2013.6532036","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532036","url":null,"abstract":"This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1587/TRANSELE.E98.C.298
J. Furuta, Kazutoshi Kobayashi, H. Onodera
We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.
{"title":"Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets","authors":"J. Furuta, Kazutoshi Kobayashi, H. Onodera","doi":"10.1587/TRANSELE.E98.C.298","DOIUrl":"https://doi.org/10.1587/TRANSELE.E98.C.298","url":null,"abstract":"We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123401924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532000
Baozhen Li, C. Christiansen, C. Burke, N. Hogle, D. Badami
Technology scaling has led to severe electromigration degradation for advanced interconnects. Taking full advantage of the Blech effect benefit has become more and more important for circuit design to overcome this EM performance degradation. Due to the wide range of circuit design layout variations, understanding the EM characteristics of the short lines closely related to the real circuit and chip design applications is needed. In this study, EM characteristics of a wide range of different short line structures are investigated. These structures include simple short line segments, short line segments with branches and with passive passing lines on top, and long lines with only a short portion carrying current. Implications of these results to circuit and chip design are also discussed.
{"title":"Short line electromigration characteristics and their applications for circuit design","authors":"Baozhen Li, C. Christiansen, C. Burke, N. Hogle, D. Badami","doi":"10.1109/IRPS.2013.6532000","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532000","url":null,"abstract":"Technology scaling has led to severe electromigration degradation for advanced interconnects. Taking full advantage of the Blech effect benefit has become more and more important for circuit design to overcome this EM performance degradation. Due to the wide range of circuit design layout variations, understanding the EM characteristics of the short lines closely related to the real circuit and chip design applications is needed. In this study, EM characteristics of a wide range of different short line structures are investigated. These structures include simple short line segments, short line segments with branches and with passive passing lines on top, and long lines with only a short portion carrying current. Implications of these results to circuit and chip design are also discussed.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120813579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531954
Lijuan Zhang, Ping-Chuan Wang, Xiao Hu Liu, P. McLaughlin, R. Filippi, Baozhen Li, J. Bao
Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation energy for extrusion fails was determined to be 1.13 eV, comparable to the value of 0.99 eV for the resistance shift fails. This suggests the same failure mechanism for two failure modes: Cu mass transport primarily along the Cu/cap interface. The current exponent was extracted as 1.48 and 1.36 for extrusion fails and resistance shift fails, respectively. Physical failure analysis confirmed Cu extrusion near the anode and void formation at the cathode. Samples with improved pre-clean process before the cap deposition significantly suppressed EM induced extrusions, indicating a mechanically stronger Cu/cap interface. Furthermore, effective atomic sink at the anode end appeared to reduce the compressive stress buildup during EM, as it also significantly mitigated EM induced extrusion.
{"title":"Electromigration extrusion kinetics of Cu interconnects","authors":"Lijuan Zhang, Ping-Chuan Wang, Xiao Hu Liu, P. McLaughlin, R. Filippi, Baozhen Li, J. Bao","doi":"10.1109/IRPS.2013.6531954","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531954","url":null,"abstract":"Electromigration lifetime and failure mechanism have been investigated for Cu/low-k interconnects at intermediate interconnect levels. It was observed that extrusion fails occurred mostly before resistance shift fails were detected. The activation energy for extrusion fails was determined to be 1.13 eV, comparable to the value of 0.99 eV for the resistance shift fails. This suggests the same failure mechanism for two failure modes: Cu mass transport primarily along the Cu/cap interface. The current exponent was extracted as 1.48 and 1.36 for extrusion fails and resistance shift fails, respectively. Physical failure analysis confirmed Cu extrusion near the anode and void formation at the cathode. Samples with improved pre-clean process before the cap deposition significantly suppressed EM induced extrusions, indicating a mechanically stronger Cu/cap interface. Furthermore, effective atomic sink at the anode end appeared to reduce the compressive stress buildup during EM, as it also significantly mitigated EM induced extrusion.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123684940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532016
W. McMahon, C. Tian, S. Uppal, H. Kothari, M. Jin, G. Larosa, T. Nigam, A. Kerber, B. Linder, E. Cartier, W. Lai, Y. Liu, R. Ramachandran, U. Kwon, B. Parameshwaran, S. Krishnan, V. Narayanan
We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.
我们比较了高性能块体平面20nm替代栅极技术和高性能块体平面28nm栅极首高k金属栅极(HKMG)技术的介电堆叠的固有可靠性，该技术由IBM联盟开发。可比较的N/ fet TDDB和可比较/改进的fet PBTI在类似的Tinv下是可以实现的。在20nm技术中不包含通道硅锗作为pet性能元件的选择影响了NBTI，推动了NBTI和PBTI之间的潜在权衡。在考虑可靠性/性能权衡的同时，集成这些性能元素的复杂性要求在技术定义期间对其进行选择，并适当考虑实际的产品使用条件。
{"title":"Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process","authors":"W. McMahon, C. Tian, S. Uppal, H. Kothari, M. Jin, G. Larosa, T. Nigam, A. Kerber, B. Linder, E. Cartier, W. Lai, Y. Liu, R. Ramachandran, U. Kwon, B. Parameshwaran, S. Krishnan, V. Narayanan","doi":"10.1109/IRPS.2013.6532016","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532016","url":null,"abstract":"We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126645276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532078
Z. Zhang, B. McGowan, Z. Feldmaier, J. Lloyd, T. McMullen, E. Wilcox, S. Schultz
Constant voltage electromigration testing (CV) was evaluated to be a complementary method to traditional constant current (CC) testing during electromigration (EM) qualification. It is demonstrated that the EM lifetime in copper conductors could vary depending on the details of the circuit. There is also a difference in failure distribution and possibly in failure modes as well. Furthermore, the constant voltage test was used to probe the lifetime dependency on location and for investigating redundancy. The experiments showed non negligible differences in both types of test and it is concluded that further failure analysis required for confirming and/or understanding the differences in the observations.
{"title":"Evaluation of constant voltage testing for electromigration study","authors":"Z. Zhang, B. McGowan, Z. Feldmaier, J. Lloyd, T. McMullen, E. Wilcox, S. Schultz","doi":"10.1109/IRPS.2013.6532078","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532078","url":null,"abstract":"Constant voltage electromigration testing (CV) was evaluated to be a complementary method to traditional constant current (CC) testing during electromigration (EM) qualification. It is demonstrated that the EM lifetime in copper conductors could vary depending on the details of the circuit. There is also a difference in failure distribution and possibly in failure modes as well. Furthermore, the constant voltage test was used to probe the lifetime dependency on location and for investigating redundancy. The experiments showed non negligible differences in both types of test and it is concluded that further failure analysis required for confirming and/or understanding the differences in the observations.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114624934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531994
D. Maji, P. Liao, Y. Lee, J. Shih, S. C. Chen, S. Gao, J. H. Lee, K. Wu
Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns (P+/N-well to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current (P+ to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI Si/SiO2 interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.
随着浅沟槽隔离(STI)的不断缩小，结漏正成为一个重要的可靠性问题。必须考虑这种结漏以改善SRAM Vccmin退化。SRAM电池中结漏的主要指标是失态漏电流，漏电流的外部表现为电流从对接触点(BCT)流向下拉晶体管栅极(LPD)。设计了具有井光失调的隔离测试模式(P+/ n -井到P-井)，以验证Si/STI界面损伤对结漏的影响。PW错位工艺实验表明，电应力作用后，隔离漏电流(P+ to PW)增大。然而，这种由PW错位引起的泄漏表现出较弱的温度和电压依赖性，表明STI Si/SiO2界面的陷阱辅助载流子跳变和PW错位对SRAM结可靠性至关重要。通过TCAD仿真，我们已经验证了载流子通过Si/STI界面陷阱的传输以及不良的PW错位是结漏电流增加的根本原因。HSPICE仿真结果表明，结漏通过降低SRAM读裕量(SNM)而恶化SRAM电池的稳定性，最终可能导致SRAM电池失效。
{"title":"A junction leakage mechanism and its effects on advance SRAM failure","authors":"D. Maji, P. Liao, Y. Lee, J. Shih, S. C. Chen, S. Gao, J. H. Lee, K. Wu","doi":"10.1109/IRPS.2013.6531994","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531994","url":null,"abstract":"Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns (P+/N-well to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current (P+ to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI Si/SiO2 interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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