Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531965
A. Haggag, A. Barr, K. Walker, L. Winemberg
We have demonstrated that the raw failure rate from field data decreases much faster than any realistic statistical reliability model due to the artifact that we are also adding parts into the field as time passes. We have shown with a simple mathematical correction we can get real FIT that behaves as expected from realistic statistical reliability model. This methodology for hard failure rate estimation can also be applied for soft failure rate estimation using “NTF” or “No Trouble Found” field returns that are believed marginal parts. Since the next generation technology may be more sensitive to soft failures than the current generation, it is critical to get both hard and soft failure rate estimates, to allow design for reliability decisions.
{"title":"Realistic 55nm IC failure in time (FIT) estimates from automotive field returns","authors":"A. Haggag, A. Barr, K. Walker, L. Winemberg","doi":"10.1109/IRPS.2013.6531965","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531965","url":null,"abstract":"We have demonstrated that the raw failure rate from field data decreases much faster than any realistic statistical reliability model due to the artifact that we are also adding parts into the field as time passes. We have shown with a simple mathematical correction we can get real FIT that behaves as expected from realistic statistical reliability model. This methodology for hard failure rate estimation can also be applied for soft failure rate estimation using “NTF” or “No Trouble Found” field returns that are believed marginal parts. Since the next generation technology may be more sensitive to soft failures than the current generation, it is critical to get both hard and soft failure rate estimates, to allow design for reliability decisions.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116451968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532052
J. Ahlbin, N. Hooten, M. Gadlage, J. Warner, S. Buchner, Dale McMorrow, Lloyd W. Massengill
Pulsed-laser single-event effects experiments on a 65 nm bulk CMOS integrated circuit confirms the existence of single-event pulse quenching and supports previous heavy-ion results. Strikes on pMOS transistors adjacent to each other are most susceptible to pulse quenching, with the pulsed-laser results emphasizing the proclivity of common n-well designs to pulse quenching. Correlation of the laser data with heavy-ion data shows that pulse quenching can occur below an LET of 9 MeV-cm2/mg.
{"title":"Identification of pulse quenching enhanced layouts with subbandgap laser-induced single-event effects","authors":"J. Ahlbin, N. Hooten, M. Gadlage, J. Warner, S. Buchner, Dale McMorrow, Lloyd W. Massengill","doi":"10.1109/IRPS.2013.6532052","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532052","url":null,"abstract":"Pulsed-laser single-event effects experiments on a 65 nm bulk CMOS integrated circuit confirms the existence of single-event pulse quenching and supports previous heavy-ion results. Strikes on pMOS transistors adjacent to each other are most susceptible to pulse quenching, with the pulsed-laser results emphasizing the proclivity of common n-well designs to pulse quenching. Correlation of the laser data with heavy-ion data shows that pulse quenching can occur below an LET of 9 MeV-cm2/mg.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126581082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532108
L. Artola, G. Hubert, peixiong zhao
This work presents the transient charge collection induced by energetic particles in sub-100 nm SOI FinFET technologies with the aim of estimating the SEU (Single Event Upset) and MBU (Multiple Event Upset) sensitivities. The estimates are performed with the dynamic charge transport and collection model of the MUSCA SEP3 platform and compared to TCAD simulations. The predictive platform works with a multi-scales modeling and physics-based Monte-Carlo approach and provides the device sensitivity but also investigates evolving technologies and emerging SEE mechanisms.
本文介绍了在亚100nm SOI FinFET技术中由高能粒子诱导的瞬态电荷收集，目的是估计SEU(单事件扰动)和MBU(多事件扰动)的灵敏度。利用MUSCA SEP3平台的动态电荷传输和收集模型进行了估计，并与TCAD模拟进行了比较。该预测平台采用多尺度建模和基于物理的蒙特卡罗方法，不仅提供了器件灵敏度，还研究了不断发展的技术和新兴的SEE机制。
{"title":"Modeling of radiation-induced single event transients in SOI FinFETS","authors":"L. Artola, G. Hubert, peixiong zhao","doi":"10.1109/IRPS.2013.6532108","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532108","url":null,"abstract":"This work presents the transient charge collection induced by energetic particles in sub-100 nm SOI FinFET technologies with the aim of estimating the SEU (Single Event Upset) and MBU (Multiple Event Upset) sensitivities. The estimates are performed with the dynamic charge transport and collection model of the MUSCA SEP3 platform and compared to TCAD simulations. The predictive platform works with a multi-scales modeling and physics-based Monte-Carlo approach and provides the device sensitivity but also investigates evolving technologies and emerging SEE mechanisms.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127542258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531944
C. Yilmaz, L. Heiß, C. Werner, D. Schmitt-Landsiedel
In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔVth-shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔVth shift.
{"title":"Modeling of NBTI-recovery effects in analog CMOS circuits","authors":"C. Yilmaz, L. Heiß, C. Werner, D. Schmitt-Landsiedel","doi":"10.1109/IRPS.2013.6531944","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531944","url":null,"abstract":"In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔVth-shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔVth shift.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531960
J. Ryan, J. Campbell, K. Cheung, J. Suehle, R. Southwick, A. Oates
We demonstrate a new charge pumping (CP) methodology, frequency modulated CP (FMCP), that robustly treats metrology challenges associated with high gate leakage current. By moving to an AC coupled measurement, we are able to easily resolve small CP signals despite excessively high gate leakage current backgrounds. We demonstrate the utility of FMCP as a reliability monitoring tool in highly scaled and highly leaky devices.
{"title":"Reliability monitoring for highly leaky devices","authors":"J. Ryan, J. Campbell, K. Cheung, J. Suehle, R. Southwick, A. Oates","doi":"10.1109/IRPS.2013.6531960","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531960","url":null,"abstract":"We demonstrate a new charge pumping (CP) methodology, frequency modulated CP (FMCP), that robustly treats metrology challenges associated with high gate leakage current. By moving to an AC coupled measurement, we are able to easily resolve small CP signals despite excessively high gate leakage current backgrounds. We demonstrate the utility of FMCP as a reliability monitoring tool in highly scaled and highly leaky devices.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130388368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532070
T. Maloney, Lei Jiang, S. Poon, K. Kolluru
A feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) pulses predicts a temperature waveform and its stability given a heat source function and a thermoelectric circuit model or thermal impulse response Z(t). The pulse delivery circuit influences those conditions along with materials and layout. Z(t) can be extracted from pre-silicon modeling (e.g., finite element) or from post-silicon transmission line pulse (TLP) response, then applied to any ESD pulse conditions. For metal lines embedded in a patterned matrix of inactive metal lines at adjoining levels, pulses produce temperatures converging to a constant value, so the related time constants allow thermal impedance Z(t) to be deduced and thermal properties of the materials checked.
{"title":"Achieving electrothermal stability in interconnect metal during ESD pulses","authors":"T. Maloney, Lei Jiang, S. Poon, K. Kolluru","doi":"10.1109/IRPS.2013.6532070","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532070","url":null,"abstract":"A feedback model of on-chip interconnect metal heating during electrostatic discharge (ESD) pulses predicts a temperature waveform and its stability given a heat source function and a thermoelectric circuit model or thermal impulse response Z(t). The pulse delivery circuit influences those conditions along with materials and layout. Z(t) can be extracted from pre-silicon modeling (e.g., finite element) or from post-silicon transmission line pulse (TLP) response, then applied to any ESD pulse conditions. For metal lines embedded in a patterned matrix of inactive metal lines at adjoining levels, pulses produce temperatures converging to a constant value, so the related time constants allow thermal impedance Z(t) to be deduced and thermal properties of the materials checked.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6531992
G. Just, J. Autran, S. Serre, D. Munteanu, S. Sauze, A. Régnier, J. Ogier, P. Roche, G. Gasiot
This work reports the combined characterization at mountain altitude (on the ASTEP Platform at 2552 m) and at sea-level of more than ~50 Gbit of 90 nm NOR flash memories subjected to natural radiation (atmospheric neutrons). This wafer-level experiment evidences a limited impact of the terrestrial radiation at ground level on the memory SER evaluated without ECC. Experimental values are compared to estimations obtained from Monte Carlo simulation using the TIARA-G4 code combined with a physical model for charge loss in such floating-gate devices.
{"title":"Soft errors induced by natural radiation at ground level in floating gate flash memories","authors":"G. Just, J. Autran, S. Serre, D. Munteanu, S. Sauze, A. Régnier, J. Ogier, P. Roche, G. Gasiot","doi":"10.1109/IRPS.2013.6531992","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6531992","url":null,"abstract":"This work reports the combined characterization at mountain altitude (on the ASTEP Platform at 2552 m) and at sea-level of more than ~50 Gbit of 90 nm NOR flash memories subjected to natural radiation (atmospheric neutrons). This wafer-level experiment evidences a limited impact of the terrestrial radiation at ground level on the memory SER evaluated without ECC. Experimental values are compared to estimations obtained from Monte Carlo simulation using the TIARA-G4 code combined with a physical model for charge loss in such floating-gate devices.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122425602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532103
M. De Tomasi, R. E. Vaion, L. Cola, P. Zabberoni, A. Mervic
Introduction of Error Correction Code (ECC) on new flash memory has changed the dominant failure mode: single defective bits are corrected, intrinsic behavior affects reliability performance. In this paper we focused on the relationship between traps generated by Drain Stress during program operation and soft program induced by continuous reading. Particular focus has been given on new approach to improve reliability performance.
{"title":"Drain stress influence on read disturb defectivity","authors":"M. De Tomasi, R. E. Vaion, L. Cola, P. Zabberoni, A. Mervic","doi":"10.1109/IRPS.2013.6532103","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532103","url":null,"abstract":"Introduction of Error Correction Code (ECC) on new flash memory has changed the dominant failure mode: single defective bits are corrected, intrinsic behavior affects reliability performance. In this paper we focused on the relationship between traps generated by Drain Stress during program operation and soft program induced by continuous reading. Particular focus has been given on new approach to improve reliability performance.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532079
Mankoo Lee, D. Pramanik, Y. Oh, Z. Qin, I. Avci, S. Simeonov, K. El Sayed, P. Balasingam
A physically based simulation methodology provides fast and practical EM lifetime prediction. We identified an “EM-aware” region to define the length dependence of Cu-lines under high current stress. For eventual calibration of 2× nm node Cu-lines, we analyzed the sensitivity trends of vacancy and void profiles as well as the mass transport mechanisms using a 3D TCAD tool. This includes electron flow dependency to explain line and via depletion effects for void formations under various EM stress conditions. We report a non-linearity in the length dependence on the EM failure jL product at ~9000 A/cm and a slight temperature dependence on the Blech Threshold (jL)c at ~2000 A/cm extracted at 300°C in the EM aware region.
基于物理的仿真方法提供了快速实用的电磁寿命预测。我们确定了一个“电磁感知”区域来定义高电流应力下铜线的长度依赖性。为了最终校准2× nm节点cu线，我们使用3D TCAD工具分析了空位和空洞轮廓的灵敏度趋势以及质量输运机制。这包括电子流依赖关系，以解释在各种电磁应力条件下空洞形成的线和通过损耗效应。我们报告了EM失效jL产品在~9000 a /cm时的长度依赖的非线性，以及在EM感知区域在300°c下提取的~2000 a /cm的漂白阈值(jL)c的轻微温度依赖。
{"title":"Determination of Cu-line EM Lifetime Criteria Using Physically Based TCAD simulations","authors":"Mankoo Lee, D. Pramanik, Y. Oh, Z. Qin, I. Avci, S. Simeonov, K. El Sayed, P. Balasingam","doi":"10.1109/IRPS.2013.6532079","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532079","url":null,"abstract":"A physically based simulation methodology provides fast and practical EM lifetime prediction. We identified an “EM-aware” region to define the length dependence of Cu-lines under high current stress. For eventual calibration of 2× nm node Cu-lines, we analyzed the sensitivity trends of vacancy and void profiles as well as the mass transport mechanisms using a 3D TCAD tool. This includes electron flow dependency to explain line and via depletion effects for void formations under various EM stress conditions. We report a non-linearity in the length dependence on the EM failure jL product at ~9000 A/cm and a slight temperature dependence on the Blech Threshold (jL)c at ~2000 A/cm extracted at 300°C in the EM aware region.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114109595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-14DOI: 10.1109/IRPS.2013.6532004
Min Chen, H. Kufluoglu, J. Carulli, V. Reddy
BTI induced aging degradation threatens circuit reliability through circuit performance degradation. This degradation is strongly workload dependent and can result in unbalanced signal edge degradation as asymmetric aging. Three ring oscillator based asymmetric aging sensitive sensors are demonstrated in a 28nm low power/poly SiON CMOS technology. These sensors are shown to be capable of providing an adequate circuit guard band to account for signal edge degradation due to NBTI. A novel DVS workload centric monitor embedded with asymmetric aging sensitive sensors is proposed for aging and power trade-off assessment. The measured data indicates that signal edge degradation has a linear dependency on workload ratio. The impact of the dynamic voltage scaling workload profile on aging and power is experimentally studied with this aging monitor and allows the assessment assists to the modeling of aging margin relaxation.
{"title":"Aging sensors for workload centric guardbanding in dynamic voltage scaling applications","authors":"Min Chen, H. Kufluoglu, J. Carulli, V. Reddy","doi":"10.1109/IRPS.2013.6532004","DOIUrl":"https://doi.org/10.1109/IRPS.2013.6532004","url":null,"abstract":"BTI induced aging degradation threatens circuit reliability through circuit performance degradation. This degradation is strongly workload dependent and can result in unbalanced signal edge degradation as asymmetric aging. Three ring oscillator based asymmetric aging sensitive sensors are demonstrated in a 28nm low power/poly SiON CMOS technology. These sensors are shown to be capable of providing an adequate circuit guard band to account for signal edge degradation due to NBTI. A novel DVS workload centric monitor embedded with asymmetric aging sensitive sensors is proposed for aging and power trade-off assessment. The measured data indicates that signal edge degradation has a linear dependency on workload ratio. The impact of the dynamic voltage scaling workload profile on aging and power is experimentally studied with this aging monitor and allows the assessment assists to the modeling of aging margin relaxation.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114869657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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