Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816781
Xiongjie Zhang, Yang Jiang, M. Law, Pui-in Mak, R. Martins
This paper presents a first mathematical model for estimating the output spectrum spurs of dual-path hybrid (DPH) DC-DC converters and proposes a $DeltaSigma-$modulation control technique to reduce harmonic spikes. The proposed model is hand-calculation friendly and can ensure reasonable accuracy. It features the prediction of the output spectrum spurs that can compromise the noise characteristic of the converters. We also propose a spur reduction method using a 2–2 MASH $DeltaSigma-$modulator to replace the conventional pulse-width modulation control, realizing a $4^{text{t}text{h}}$ order noise shaping function for better noise and limit-cycle spike suppression with relaxed stability issue. Simulation results show that the $DeltaSigma-$modulation controlled DPH converter achieves a spectrum spike reduction of 17. 6dB and 15.2 dB in low- and high-frequency conditions, respectively, compared with PWM control.
{"title":"Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters","authors":"Xiongjie Zhang, Yang Jiang, M. Law, Pui-in Mak, R. Martins","doi":"10.1109/prime55000.2022.9816781","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816781","url":null,"abstract":"This paper presents a first mathematical model for estimating the output spectrum spurs of dual-path hybrid (DPH) DC-DC converters and proposes a $DeltaSigma-$modulation control technique to reduce harmonic spikes. The proposed model is hand-calculation friendly and can ensure reasonable accuracy. It features the prediction of the output spectrum spurs that can compromise the noise characteristic of the converters. We also propose a spur reduction method using a 2–2 MASH $DeltaSigma-$modulator to replace the conventional pulse-width modulation control, realizing a $4^{text{t}text{h}}$ order noise shaping function for better noise and limit-cycle spike suppression with relaxed stability issue. Simulation results show that the $DeltaSigma-$modulation controlled DPH converter achieves a spectrum spike reduction of 17. 6dB and 15.2 dB in low- and high-frequency conditions, respectively, compared with PWM control.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122785320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816760
M. M. Abdevand, D. Livornesi, A. E. Vergani, P. Malcovati, E. Bonizzoni
A resistive sensor is conventionally biased by a voltage divider or a Wheatstone bridge. Applying a precise bias on a low-resistance sensor with these conventional approaches, however, necessarily requires calibration of the components, which is time-consuming and costly for mass production. In this paper, we propose an analog front-end circuit for low-resistance sensors, based on a closed-loop bias circuit with high-impedance output, which does not require any calibration. In addition, after a comprehensive analysis of the bias noise, we introduce a noise canceling technique, which allows more than 25 dB reduction of the bias noise in the complete interface circuit, even in the presence of gain mismatches as large as 5%.
{"title":"Interface Circuit for Low-Resistance Sensors Based on Noise Cancelling Technique","authors":"M. M. Abdevand, D. Livornesi, A. E. Vergani, P. Malcovati, E. Bonizzoni","doi":"10.1109/prime55000.2022.9816760","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816760","url":null,"abstract":"A resistive sensor is conventionally biased by a voltage divider or a Wheatstone bridge. Applying a precise bias on a low-resistance sensor with these conventional approaches, however, necessarily requires calibration of the components, which is time-consuming and costly for mass production. In this paper, we propose an analog front-end circuit for low-resistance sensors, based on a closed-loop bias circuit with high-impedance output, which does not require any calibration. In addition, after a comprehensive analysis of the bias noise, we introduce a noise canceling technique, which allows more than 25 dB reduction of the bias noise in the complete interface circuit, even in the presence of gain mismatches as large as 5%.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131952868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816834
Paolo Melillo, Alessandro Dago, A. Gasparini, S. Levantino, M. Ghioni
Time-based control is a valid alternative to conventional voltage-mode since it operates with CMOS-level signals while adding no quantization error. This control methodology is especially suitable for voltage regulation in portable applications, where area and power consumption are key parameters. In boost converters powering LED displays, a very fast response to disturbances in the line voltage is required, though the typical right-half-plane (RHP) zero in their control-output transfer function tends to cause large overshoots and long settling times. To solve this issue, we propose a novel feedforward technique, which can be easily combined to the time-based control. The technique is based on adding the band-pass-filtered line voltage to the controller input, to speed up the duty-cycle variation. To assess the effectiveness of this method, theoretical analysis and simulation results are proposed.
{"title":"A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters","authors":"Paolo Melillo, Alessandro Dago, A. Gasparini, S. Levantino, M. Ghioni","doi":"10.1109/prime55000.2022.9816834","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816834","url":null,"abstract":"Time-based control is a valid alternative to conventional voltage-mode since it operates with CMOS-level signals while adding no quantization error. This control methodology is especially suitable for voltage regulation in portable applications, where area and power consumption are key parameters. In boost converters powering LED displays, a very fast response to disturbances in the line voltage is required, though the typical right-half-plane (RHP) zero in their control-output transfer function tends to cause large overshoots and long settling times. To solve this issue, we propose a novel feedforward technique, which can be easily combined to the time-based control. The technique is based on adding the band-pass-filtered line voltage to the controller input, to speed up the duty-cycle variation. To assess the effectiveness of this method, theoretical analysis and simulation results are proposed.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116624374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816746
{"title":"PRIME 2022 Cover Page","authors":"","doi":"10.1109/prime55000.2022.9816746","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816746","url":null,"abstract":"","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127605772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816774
Franz Marcus Schüffny, S. Höppner, S. Zeinolabedin, R. George, C. Mayr
The increase of recording channels in modern electrode-based neural recording systems is limited by considerations of power. Emerging CMOS technologies like 22 nm FDSOI promise to open new perspectives in overcoming power constraints due to their particular energy efficiency in digital circuit integration, they however also pose a challenge for the analogue front-end stages of such systems, especially with respect to signal noise. This paper addresses the design of low noise amplifiers (LNA), the most critical component with respect to power and noise, in this technology and application. Moreover, a trade-off between igs-shot noise and flicker noise is described, which leads to the design of the LNA’s operational amplifier, minimising noise for a given current. Capacitor types vary in leakage and hence in noise. We therefore simulated and analysed different types and sizes of DC-decoupling capacitors for an estimation of the minimum-area requirement of the LNA. Notably, the described design approaches the minimum input-referred noise possible for a given current and input capacitor in this technology.
{"title":"How to design an input stage for neural recording system in 22 nm FDSOI","authors":"Franz Marcus Schüffny, S. Höppner, S. Zeinolabedin, R. George, C. Mayr","doi":"10.1109/prime55000.2022.9816774","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816774","url":null,"abstract":"The increase of recording channels in modern electrode-based neural recording systems is limited by considerations of power. Emerging CMOS technologies like 22 nm FDSOI promise to open new perspectives in overcoming power constraints due to their particular energy efficiency in digital circuit integration, they however also pose a challenge for the analogue front-end stages of such systems, especially with respect to signal noise. This paper addresses the design of low noise amplifiers (LNA), the most critical component with respect to power and noise, in this technology and application. Moreover, a trade-off between igs-shot noise and flicker noise is described, which leads to the design of the LNA’s operational amplifier, minimising noise for a given current. Capacitor types vary in leakage and hence in noise. We therefore simulated and analysed different types and sizes of DC-decoupling capacitors for an estimation of the minimum-area requirement of the LNA. Notably, the described design approaches the minimum input-referred noise possible for a given current and input capacitor in this technology.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816775
Bing Xue, Mark Zwolinski
Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.
{"title":"Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors","authors":"Bing Xue, Mark Zwolinski","doi":"10.1109/prime55000.2022.9816775","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816775","url":null,"abstract":"Reliability is a major concern in many embedded systems. Redundancy-based methods are widely used against Single Event Upsets, causing significant temporal and spatial overhead. The traditional method to evaluate the reliability of a system is fault injection. However, it is practically impossible to test all faults for a complex design due to intractable simulation times. In this paper, we propose using formal methods to evaluate hardware reliability in the presence of soft errors. The proposed method can exhaustively search the entire state space and the whole fault list in a reasonable time. The method is applied to assess the vulnerability of all registers in a RISC-V Ibex core.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816785
Xun Chen, M. Wei, R. Negra
This paper presents a fully-differential bootstrapped Gilbert-cell-based frequency doubler designed in a 130-nm SiGe process to provide an output frequency of 220 GHz. At this frequency, an underlying asymmetrical layout of the switching quad leads to several problems such as output amplitude difference, phase difference deviating from 180°, and conversion gain (CG) degradation. An imbalance analysis is therefore carried out to understand the critical layout routings. The results show that the imbalance at the collectors of the transistors has the most severe impact on the differential output amplitudes and phases. On the other hand, imbalance at the base influences the CG mostly. Based on these findings, a frequency doubler was designed in the SiGe SG13G2 technology. The proposed frequency doubler achieves a maximum output power of -5.8dBm and a 1-dB bandwidth of 25 GHz from 202.5 GHz to 227.5 GHz with 91 mW of dc power consumption in the full EM post layout simulation.
{"title":"Influence of Amplitude and Phase Imbalance on a Y-band Bootstrapped Frequency Doubler using 130-nm SiGe Technology","authors":"Xun Chen, M. Wei, R. Negra","doi":"10.1109/prime55000.2022.9816785","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816785","url":null,"abstract":"This paper presents a fully-differential bootstrapped Gilbert-cell-based frequency doubler designed in a 130-nm SiGe process to provide an output frequency of 220 GHz. At this frequency, an underlying asymmetrical layout of the switching quad leads to several problems such as output amplitude difference, phase difference deviating from 180°, and conversion gain (CG) degradation. An imbalance analysis is therefore carried out to understand the critical layout routings. The results show that the imbalance at the collectors of the transistors has the most severe impact on the differential output amplitudes and phases. On the other hand, imbalance at the base influences the CG mostly. Based on these findings, a frequency doubler was designed in the SiGe SG13G2 technology. The proposed frequency doubler achieves a maximum output power of -5.8dBm and a 1-dB bandwidth of 25 GHz from 202.5 GHz to 227.5 GHz with 91 mW of dc power consumption in the full EM post layout simulation.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114797663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816829
Guillermo Díez-Señorans, M. Garcia-Bosque, C. Sánchez-Azqueta, S. Celma
In this paper we analyze the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA due to differences in detailed routing at LUT level. The different PUF configurations for a given set of ring oscillators are generated using programmable delay lines on the cells realizing the inverters, while only one LUT input is used for the propagation of the oscillations along the ring. This architecture is suitable for implementation in FPGA, so the experiments have been conducted on Xilinx’s Zynq SoC.
{"title":"Programmable delay lines on different LUT implementations for CRO-PUF","authors":"Guillermo Díez-Señorans, M. Garcia-Bosque, C. Sánchez-Azqueta, S. Celma","doi":"10.1109/prime55000.2022.9816829","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816829","url":null,"abstract":"In this paper we analyze the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA due to differences in detailed routing at LUT level. The different PUF configurations for a given set of ring oscillators are generated using programmable delay lines on the cells realizing the inverters, while only one LUT input is used for the propagation of the oscillations along the ring. This architecture is suitable for implementation in FPGA, so the experiments have been conducted on Xilinx’s Zynq SoC.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816751
Lukasz Farian, Pablo Fernández-Peramo, P. Häfliger, J. A. Leñero-Bardallo
A new method to obtain sub-pixel measurement resolution for sun sensors based on spiking pixels is presented. The procedure is intended to increase the resolution of the estimated angle. The method uses the profile of incident light to estimate the angle of the vector towards the sun with sub-pixel resolution. Read-out time, data bandwidth, and spatial resolution are improved. Experimental results are provided. The proposed method can be implemented in any asynchronous sun sensor operating in Time-to-First-Spike (TFS) mode.
{"title":"Centroid estimation method with sub-pixel resolution for event-based sun sensors","authors":"Lukasz Farian, Pablo Fernández-Peramo, P. Häfliger, J. A. Leñero-Bardallo","doi":"10.1109/prime55000.2022.9816751","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816751","url":null,"abstract":"A new method to obtain sub-pixel measurement resolution for sun sensors based on spiking pixels is presented. The procedure is intended to increase the resolution of the estimated angle. The method uses the profile of incident light to estimate the angle of the vector towards the sun with sub-pixel resolution. Read-out time, data bandwidth, and spatial resolution are improved. Experimental results are provided. The proposed method can be implemented in any asynchronous sun sensor operating in Time-to-First-Spike (TFS) mode.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127234618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/prime55000.2022.9816754
A. V. Radogna, S. Capone, L. Francioso, P. Siciliano, S. D’Amico
In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit’s operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS $28mathrm{~nm}$ FDSOI technology with a total area occupation of $45mumathrm{m}times 45mumathrm{m}$. From the RTL synthesis, a total power consumption of $8.2mumathrm{W}$ is obtained.
{"title":"An Integrated Multi-Order Digital Control Unit for Maximum Length Sequence Circulant Matrix Generation","authors":"A. V. Radogna, S. Capone, L. Francioso, P. Siciliano, S. D’Amico","doi":"10.1109/prime55000.2022.9816754","DOIUrl":"https://doi.org/10.1109/prime55000.2022.9816754","url":null,"abstract":"In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit’s operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS $28mathrm{~nm}$ FDSOI technology with a total area occupation of $45mumathrm{m}times 45mumathrm{m}$. From the RTL synthesis, a total power consumption of $8.2mumathrm{W}$ is obtained.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127249070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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