Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708722
S. Azuma, Ryotatsu Yanagimoto, S. Kamitani, M. Edamoto, K. Arata, H. Matsui, H. Akada, R. Masuda, K. Hoshino, K. Nagura, H. Ogawa
This paper presents a 1.25 Gbps optical links design for mobile handsets. The system consists of an optical connector and a SER/DES main chip. The former contains an 850 nm VCSEL (vertical cavity surface emission laser), a GaAs-PIN photodiode and a transimpedance amplifier (TIA). The later includes a serializer, a deserializer, a VCSEL driver, a limiting amplifier, a PLL and a CDR. The chip and TIA were fabricated in a 0.13 um CMOS process with MIM capacitors. A digital type CDR with fine timing controls allows sharing a VCO between transmitter and receiver, resulting in reduced both power consumption and silicon area. The system fully demonstrated a 1.25 Gbps data and video stream transmission, consuming 108.4 mW of power under 1.2 V/3.3 V supply voltages.
本文提出了一种用于手机的1.25 Gbps光链路设计方案。该系统由一个光连接器和一个SER/DES主芯片组成。前者包含一个850 nm垂直腔面发射激光器，一个GaAs-PIN光电二极管和一个跨阻放大器(TIA)。后者包括序列化器、反序列化器、VCSEL驱动程序、限制放大器、锁相环和CDR。该芯片和TIA采用0.13 um CMOS工艺，采用MIM电容器制造。具有精细定时控制的数字型CDR允许在发射器和接收器之间共享一个压控振荡器，从而降低功耗和硅面积。该系统充分展示了1.25 Gbps的数据和视频流传输，在1.2 V/3.3 V供电电压下消耗108.4 mW的功率。
{"title":"1.25Gbps optical links for mobile handsets","authors":"S. Azuma, Ryotatsu Yanagimoto, S. Kamitani, M. Edamoto, K. Arata, H. Matsui, H. Akada, R. Masuda, K. Hoshino, K. Nagura, H. Ogawa","doi":"10.1109/ASSCC.2008.4708722","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708722","url":null,"abstract":"This paper presents a 1.25 Gbps optical links design for mobile handsets. The system consists of an optical connector and a SER/DES main chip. The former contains an 850 nm VCSEL (vertical cavity surface emission laser), a GaAs-PIN photodiode and a transimpedance amplifier (TIA). The later includes a serializer, a deserializer, a VCSEL driver, a limiting amplifier, a PLL and a CDR. The chip and TIA were fabricated in a 0.13 um CMOS process with MIM capacitors. A digital type CDR with fine timing controls allows sharing a VCO between transmitter and receiver, resulting in reduced both power consumption and silicon area. The system fully demonstrated a 1.25 Gbps data and video stream transmission, consuming 108.4 mW of power under 1.2 V/3.3 V supply voltages.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708738
K. Niitsu, S. Kawai, N. Miura, H. Ishikuro, T. Kuroda
This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90 nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading any of timing margin, data rate and bit error rate.
{"title":"A 65 fJ/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3D system integration","authors":"K. Niitsu, S. Kawai, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2008.4708738","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708738","url":null,"abstract":"This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90 nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading any of timing margin, data rate and bit error rate.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121452195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.
{"title":"A 0.35μm CMOS sub-1V low-quiescent-current low-dropout regulator","authors":"Yuh-Shyan Hwang, Ming-Shian Lin, Bo-Han Hwang, Jiann-Jong Chen","doi":"10.1109/ASSCC.2008.4708751","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708751","url":null,"abstract":"A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708748
F. Zhang, B. Yang, B. Wicks, Z. Liu, C. Ta, Y. Mo, K. Wang, G. Felic, P. Nadagouda, T. Walsh, W. Shieh, I. Mareels, R. Evans, E. Skafidas
This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.
{"title":"A 60-GHz direct-conversion transmitter in 130-nm CMOS","authors":"F. Zhang, B. Yang, B. Wicks, Z. Liu, C. Ta, Y. Mo, K. Wang, G. Felic, P. Nadagouda, T. Walsh, W. Shieh, I. Mareels, R. Evans, E. Skafidas","doi":"10.1109/ASSCC.2008.4708748","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708748","url":null,"abstract":"This paper describes the system architecture and design procedure for a 60-GHz transmitter in 130-nm CMOS process. The transmitter achieves a saturation power output of better than 4 dBm and an output-referred 1-dB compression point of 2 dBm. The LO to RF port isolation is better than 27 dB from 57 to 65 GHz. To the best of the authorspsila knowledge, this is the first reported 60-GHz transmitter in 130-nm CMOS that incorporates on-chip filtering.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708828
Jin-Siang Syu, C. Meng, G. Huang
A trifilar-coupling quadrature voltage-controlled oscillator (QVCO) is demonstrated using 0.35-mum SiGe heterojunction bipolar transistor (HBT) technology. The trifilar transformer consisting of one primary coil and two secondary coils is used in this work to separate the collector and base bias for output voltage swing optimization and also to replace a conventional transistor-coupling method for quadrature output generation, simultaneously. As a result, the trifilar-coupling QVCO achieves the 191.6-dBc/Hz FOM at the supply voltage of 1.2 V The on-chip passive single side-band (SSB) upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Consequently, the side-band rejection ratio of 37.7 dB is achieved.
采用0.35 μ m SiGe异质结双极晶体管(HBT)技术，设计了一种三线耦合正交压控振荡器(QVCO)。在这项工作中，使用由一个初级线圈和两个次级线圈组成的三线变压器来分离集电极和基极偏置，以优化输出电压摆幅，同时也取代了传统的晶体管耦合方法来产生正交输出。结果表明，三线耦合QVCO在1.2 V电源电压下实现了191.6 dbc /Hz的FOM，片上无源单边带(SSB)上变频混频器也能很好地测量QVCO的正交精度。因此，获得了37.7 dB的边带抑制比。
{"title":"SiGe HBT quadrature VCO utilizing trifilar transformers","authors":"Jin-Siang Syu, C. Meng, G. Huang","doi":"10.1109/ASSCC.2008.4708828","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708828","url":null,"abstract":"A trifilar-coupling quadrature voltage-controlled oscillator (QVCO) is demonstrated using 0.35-mum SiGe heterojunction bipolar transistor (HBT) technology. The trifilar transformer consisting of one primary coil and two secondary coils is used in this work to separate the collector and base bias for output voltage swing optimization and also to replace a conventional transistor-coupling method for quadrature output generation, simultaneously. As a result, the trifilar-coupling QVCO achieves the 191.6-dBc/Hz FOM at the supply voltage of 1.2 V The on-chip passive single side-band (SSB) upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Consequently, the side-band rejection ratio of 37.7 dB is achieved.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122595975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708768
Jeong-Kyoum Kim, Jaeha Kim, D. Jeong
This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.
{"title":"A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS","authors":"Jeong-Kyoum Kim, Jaeha Kim, D. Jeong","doi":"10.1109/ASSCC.2008.4708768","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708768","url":null,"abstract":"This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708764
R. Palmer, J. Poulton, A. Fuller, J. Chen, J. Zerbe
This paper highlights design considerations for low-power, high-performance mobile memory and logic interfaces, based on the results from the 14 mW, 6.25 Gb/s transceiver test chip demonstrated in 90 nm CMOS. One of the keys to achieving 2.25 mW/Gbps was the highly-sensitive, low-offset receiver. An accurate receiver enables low-swing signaling and requires less power and area from the transmitter. The smaller transceiver design in turn lowers the clock distribution power and improves the signal quality by presenting less loading to the clock and the channel, respectively. The improved signal quality enables even lower signal swing and a ldquospiral of goodnessrdquo continues. This paper examines these aspects in detail and discusses their potential implications to a broad spectrum of future low-power, high-performance mobile interface designs.
{"title":"Design considerations for low-power high-performance mobile logic and memory interfaces","authors":"R. Palmer, J. Poulton, A. Fuller, J. Chen, J. Zerbe","doi":"10.1109/ASSCC.2008.4708764","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708764","url":null,"abstract":"This paper highlights design considerations for low-power, high-performance mobile memory and logic interfaces, based on the results from the 14 mW, 6.25 Gb/s transceiver test chip demonstrated in 90 nm CMOS. One of the keys to achieving 2.25 mW/Gbps was the highly-sensitive, low-offset receiver. An accurate receiver enables low-swing signaling and requires less power and area from the transmitter. The smaller transceiver design in turn lowers the clock distribution power and improves the signal quality by presenting less loading to the clock and the channel, respectively. The improved signal quality enables even lower signal swing and a ldquospiral of goodnessrdquo continues. This paper examines these aspects in detail and discusses their potential implications to a broad spectrum of future low-power, high-performance mobile interface designs.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708735
V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi
This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family-feedthrough logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).
{"title":"Design of energy efficient 10ps per bit adder circuits in CMOS","authors":"V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/ASSCC.2008.4708735","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708735","url":null,"abstract":"This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family-feedthrough logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127725627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708794
Long Yan, Namjun Cho, J. Yoo, Binhee Kim, H. Yoo
A 2.88 nJ/Conversion low energy biopotential acquisition system is designed for portable healthcare device. Two dry copper contact electrodes with 1.2-cm diameter are used to easily interface between skin and healthcare device. Chopping technique is adopted at readout front end to obtain thermal noise floor of 1.3 uVrms over 0.5~200 Hz and CMRR over 100 dB to mitigate common-mode body potential induced from AC power line. A 4-stage gain control and band selection blocks are integrated to digitally calibrate for different types of biomedical signal and an 8-bit synchronous successive approximation register (SAR) A/D is used to digitize sensed biopotentials. A test chip is implemented in 0.18 um, 1.8 V supply CMOS technology and successively verified by readout ECG signal with two electrodes contact at chest of body with separating 6 cm.
{"title":"A two-electrode 2.88nJ/conversion biopotential acquisition system for portable healthcare device","authors":"Long Yan, Namjun Cho, J. Yoo, Binhee Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708794","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708794","url":null,"abstract":"A 2.88 nJ/Conversion low energy biopotential acquisition system is designed for portable healthcare device. Two dry copper contact electrodes with 1.2-cm diameter are used to easily interface between skin and healthcare device. Chopping technique is adopted at readout front end to obtain thermal noise floor of 1.3 uVrms over 0.5~200 Hz and CMRR over 100 dB to mitigate common-mode body potential induced from AC power line. A 4-stage gain control and band selection blocks are integrated to digitally calibrate for different types of biomedical signal and an 8-bit synchronous successive approximation register (SAR) A/D is used to digitize sensed biopotentials. A test chip is implemented in 0.18 um, 1.8 V supply CMOS technology and successively verified by readout ECG signal with two electrodes contact at chest of body with separating 6 cm.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115939292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708719
Choongyeun Cho, D.D. Kim, Jonghae Kim
This paper introduces a process variability model to determine the performance and yield of the cell broadband engine (CBE) in 65 nm SOI CMOS. The model incorporates spatial (die-to-die), temporal (manufacturing process drift), and parametric dimensions, and provides microprocessor performance tracking and comprehensive view on the process variability with embedded ring oscillator measurement at the wafer level. It extracts CBE performance regularity within die for the circuit design and models, and reveals the semiconductor manufacturing signatures in wafers and lots for process technology. The model reduces performance estimation testing requirements by surpassing conventional methodspsila accuracy by 28%.
本文介绍了一种工艺变化模型，用于确定65nm SOI CMOS小区宽带引擎(CBE)的性能和良率。该模型结合了空间(模对模)，时间(制造过程漂移)和参数维度，并提供微处理器性能跟踪和在晶圆级上使用嵌入式环形振荡器测量的过程可变性的全面视图。为电路设计和模型提取芯片内部CBE性能规律，为工艺技术揭示晶圆和批次中的半导体制造特征。该模型降低了性能评估测试的要求，比传统方法的准确率提高了28%。
{"title":"Cell Broadband Engine performance and yield benchmark in 65nm SOI CMOS with spatial, temporal and parametric process variability model","authors":"Choongyeun Cho, D.D. Kim, Jonghae Kim","doi":"10.1109/ASSCC.2008.4708719","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708719","url":null,"abstract":"This paper introduces a process variability model to determine the performance and yield of the cell broadband engine (CBE) in 65 nm SOI CMOS. The model incorporates spatial (die-to-die), temporal (manufacturing process drift), and parametric dimensions, and provides microprocessor performance tracking and comprehensive view on the process variability with embedded ring oscillator measurement at the wafer level. It extracts CBE performance regularity within die for the circuit design and models, and reveals the semiconductor manufacturing signatures in wafers and lots for process technology. The model reduces performance estimation testing requirements by surpassing conventional methodspsila accuracy by 28%.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116036983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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