Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708769
P. Park, A. C. Carusone
A binary receiver analog front-end (AFE) targeting 20 Gb/s for use with coaxial cable channels is presented. To accommodate links of varying lengths, the AFE includes an analog peaking equalizer followed by a post-amplifier. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89 mm2 in a 90-nm CMOS process and dissipates 138 mW from a 1.3-V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s data stream transmitted over coaxial cable with 7.5-dB loss at 10 GHz.
{"title":"A 20-Gb/s coaxial cable receiver analog front-end in 90-nm CMOS technology","authors":"P. Park, A. C. Carusone","doi":"10.1109/ASSCC.2008.4708769","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708769","url":null,"abstract":"A binary receiver analog front-end (AFE) targeting 20 Gb/s for use with coaxial cable channels is presented. To accommodate links of varying lengths, the AFE includes an analog peaking equalizer followed by a post-amplifier. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89 mm2 in a 90-nm CMOS process and dissipates 138 mW from a 1.3-V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s data stream transmitted over coaxial cable with 7.5-dB loss at 10 GHz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708762
Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto
We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.
{"title":"A low-power processor for portable navigation devices: 456 mW at 400 MHz and 24 mW in software standby mode","authors":"Khoa Dac Tran, P. Van Nguyen, Hoa Tan Lu, Cuong Phuc Phan, Quang Phan, H. Kudo, H. Masuda, S. Negishi, M. Yamamoto, K. Hirose, Y. Okamoto","doi":"10.1109/ASSCC.2008.4708762","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708762","url":null,"abstract":"We have developed a processor (SH-MobileR2) optimized for both low power and high performance. SH-MobileR2 includes a 32-bit RISC type SuperH CPU with 720 MIPS performance at 400 MHz operating frequency, and a Floating Point unit with 2.8 GFLOPS performance. The CPU also has a 256-KByte secondary unified cache on top of the 64-KByte primary split cache. Compared to the previous SH-MobileR processor, SH-MobileR2 introduces four peripheral modules: a DDR-SDRAM controller, an Interconnect Buffers with 128-Kbyte embedded Media RAM, an improved Video Processing unit (VPU5F), and an enhanced 2-D Graphics accelerator for higher performance in map rendering and graphic applications. Low-power consumption is achieved by optimizing blends of a 90 nm CMOS triple Vth cells, and applying four power-down modes. The low-power consumption and the high performance of SH-MobileR2 processor is the most suitable for portable navigation devices.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"41 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708755
Feng Su, W. Ki
An integrated switched-capacitor power converter with reconfigurable conversion ratios of 4times/5times/6times/7times/8times for mobile display driver applications is presented. This converter requires only four flying capacitors for realizing all the conversion ratios, and when achieving 4times and 5times, the original redundant flying capacitor is reconfigured to the dual-branch architecture to enhance efficiency. The advantages of both level-shifter and PN-switches control schemes are combined as a hybrid gate control scheme in eliminating reversion current. Gate switching loss of power transistors is reduced by a charge recycling mechanism. The design was fabricated in a 0.35 mum 50 V CMOS process. Measurement results confirm that the converter could achieve an output voltage higher than 14 V for a supply voltage that ranges from 2 V to 5 V. The converter delivers 1 mA even when the supply voltage is as low as 2 V.
提出了一种可重构转换比为4倍/5倍/6倍/7倍/8倍的集成开关电容功率转换器，用于移动显示驱动。该变换器只需要4个飞行电容即可实现所有的转换比，当达到4倍和5倍时，将原来冗余的飞行电容重新配置为双支路架构以提高效率。将移电平和pn开关两种控制方式的优点结合在一起，形成一种混合门控制方式来消除反向电流。通过电荷回收机制降低了功率晶体管的栅极开关损耗。该设计采用0.35 μ m 50 V CMOS工艺。测量结果证实，在2 V至5 V的电源电压范围内，转换器可以实现高于14 V的输出电压。即使电源电压低至2 V，转换器也能提供1 mA。
{"title":"An integrated reconfigurable SC Power converter with hybrid gate control scheme for mobile display driver applications","authors":"Feng Su, W. Ki","doi":"10.1109/ASSCC.2008.4708755","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708755","url":null,"abstract":"An integrated switched-capacitor power converter with reconfigurable conversion ratios of 4times/5times/6times/7times/8times for mobile display driver applications is presented. This converter requires only four flying capacitors for realizing all the conversion ratios, and when achieving 4times and 5times, the original redundant flying capacitor is reconfigured to the dual-branch architecture to enhance efficiency. The advantages of both level-shifter and PN-switches control schemes are combined as a hybrid gate control scheme in eliminating reversion current. Gate switching loss of power transistors is reduced by a charge recycling mechanism. The design was fabricated in a 0.35 mum 50 V CMOS process. Measurement results confirm that the converter could achieve an output voltage higher than 14 V for a supply voltage that ranges from 2 V to 5 V. The converter delivers 1 mA even when the supply voltage is as low as 2 V.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125120689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708800
Fei Song, H. Liao, Jiang Chen, Le Ye, Huaizhou Yang, Junhua Liu, Jinshu Zhao, Ru Huang
A 1.8-V 0.18..m CMOS direct-conversion Tuner for UHF band mobile digital TV applications is presented. To meet the stringent requirements of Noise Figure (NF) and IIP3, a capacitor cross-coupled (CCC) common-gate LNA and a novel high-linearity, low-flicker noise Gilbert Mixer are adopted. The LNA achieves 26 dB variable gain by using digital controlled current-steering technique and a resistive attenuator. To overcome the gain roll-off at the high frequency channels, a current reuse self-biased post-LNA buffer is proposed as the interface between the VGLNA and Mixer. In addition, a fully integrated DC Offset Correction (DCOC) circuit with switchable high-pass corner frequency, is introduced to realize both low high-pass cutoff frequency and short settling time. A wideband integer-N synthesizer using an adaptive frequency calibration (AFC) of dichotomizing technique, settles less than 200 mus for LO generation. The tuner achieves 3.8 dB NF, 0dBm IIP3@20dB LNA gain attenuation, 92 dB gain dynamic range and occupies 3.45 mm times 3.4 mm silicon area, while drawing 59 mA from 1.8-V voltage supply.
A 1.8-v 0.18..介绍了一种适用于UHF波段移动数字电视的CMOS直接转换调谐器。为了满足噪声图(NF)和IIP3的严格要求，采用了电容交叉耦合(CCC)共门LNA和一种新型的高线性度、低闪变噪声吉尔伯特混频器。LNA采用数字控制电流转向技术和电阻衰减器实现26db可变增益。为了克服高频通道的增益滚降，提出了电流复用自偏置后lna缓冲器作为VGLNA和混频器之间的接口。此外，还引入了一种可切换高通角频率的全集成直流偏置校正(DCOC)电路，实现了低高通截止频率和短稳定时间。一种宽带整数n合成器采用自适应频率校准(AFC)的二分类技术，产生LO的时间小于200 μ s。调谐器实现3.8 dB NF, 0dBm IIP3@20dB LNA增益衰减，92 dB增益动态范围，占用3.45 mm乘以3.4 mm的硅面积，从1.8 v电压电源吸收59 mA。
{"title":"A 1.8-V CMOS direct-conversion tuner for mobile DTV applications","authors":"Fei Song, H. Liao, Jiang Chen, Le Ye, Huaizhou Yang, Junhua Liu, Jinshu Zhao, Ru Huang","doi":"10.1109/ASSCC.2008.4708800","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708800","url":null,"abstract":"A 1.8-V 0.18..m CMOS direct-conversion Tuner for UHF band mobile digital TV applications is presented. To meet the stringent requirements of Noise Figure (NF) and IIP3, a capacitor cross-coupled (CCC) common-gate LNA and a novel high-linearity, low-flicker noise Gilbert Mixer are adopted. The LNA achieves 26 dB variable gain by using digital controlled current-steering technique and a resistive attenuator. To overcome the gain roll-off at the high frequency channels, a current reuse self-biased post-LNA buffer is proposed as the interface between the VGLNA and Mixer. In addition, a fully integrated DC Offset Correction (DCOC) circuit with switchable high-pass corner frequency, is introduced to realize both low high-pass cutoff frequency and short settling time. A wideband integer-N synthesizer using an adaptive frequency calibration (AFC) of dichotomizing technique, settles less than 200 mus for LO generation. The tuner achieves 3.8 dB NF, 0dBm IIP3@20dB LNA gain attenuation, 92 dB gain dynamic range and occupies 3.45 mm times 3.4 mm silicon area, while drawing 59 mA from 1.8-V voltage supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122781312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708716
Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, S. Cheng, Chun-Chia Chen, F. Chiu, Kung-Sheng Lin, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, G. Chen, T. Hsiao, Chi-Hui Wang
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.
{"title":"A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications","authors":"Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, S. Cheng, Chun-Chia Chen, F. Chiu, Kung-Sheng Lin, Chung-Bin Wu, Sling Liang, Sheng-Jen Wang, G. Chen, T. Hsiao, Chi-Hui Wang","doi":"10.1109/ASSCC.2008.4708716","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708716","url":null,"abstract":"A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal CMOS process with area of 5.06 mm2. For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708808
Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang
A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-mum CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.
{"title":"A 2-GS/s 6-bit flash ADC with offset calibration","authors":"Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang","doi":"10.1109/ASSCC.2008.4708808","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708808","url":null,"abstract":"A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-mum CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131126542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708812
P. K. Das, B. Amrutur, J. Sridhar, V. Visvanathan
We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5 ps and a DNL of 1.2 ps.
{"title":"On-chip clock network skew measurement using sub-sampling","authors":"P. K. Das, B. Amrutur, J. Sridhar, V. Visvanathan","doi":"10.1109/ASSCC.2008.4708812","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708812","url":null,"abstract":"We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5 ps and a DNL of 1.2 ps.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133308447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708729
F. Hsieh, Tai-Cheng Lee
A 700-MHz 6-bit pipelined ADC with current-switching open-loop residue amplification and global-gain control is designed. Using a multiplexed-input architecture to implement T/H and MDAC circuits, the transmission-gate switching is replaced by the current-switching technique. Without the need of digital calibration, a global-gain control technique is employed to eliminate the gain error. Fabricated in a 0.13-mum CMOS technology, the ADC consumes 24 mW from a 1.2-V power supply while the active area is only 0.052 mm2.
设计了一种带电流开关开环剩余放大和全局增益控制的700 mhz 6位流水线ADC。采用多路输入架构实现T/H和MDAC电路，用电流开关技术取代了传输门开关。在不需要数字校准的情况下，采用全局增益控制技术消除增益误差。该ADC采用0.13 μ m CMOS技术制造，在1.2 v电源下功耗为24 mW，而有效面积仅为0.052 mm2。
{"title":"A 6-bit pipelined analog-to-digital converter with current-switching open-loop residue amplification","authors":"F. Hsieh, Tai-Cheng Lee","doi":"10.1109/ASSCC.2008.4708729","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708729","url":null,"abstract":"A 700-MHz 6-bit pipelined ADC with current-switching open-loop residue amplification and global-gain control is designed. Using a multiplexed-input architecture to implement T/H and MDAC circuits, the transmission-gate switching is replaced by the current-switching technique. Without the need of digital calibration, a global-gain control technique is employed to eliminate the gain error. Fabricated in a 0.13-mum CMOS technology, the ADC consumes 24 mW from a 1.2-V power supply while the active area is only 0.052 mm2.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116141073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.
{"title":"A 0.35μm CMOS sub-1V low-quiescent-current low-dropout regulator","authors":"Yuh-Shyan Hwang, Ming-Shian Lin, Bo-Han Hwang, Jiann-Jong Chen","doi":"10.1109/ASSCC.2008.4708751","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708751","url":null,"abstract":"A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708768
Jeong-Kyoum Kim, Jaeha Kim, D. Jeong
This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.
{"title":"A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS","authors":"Jeong-Kyoum Kim, Jaeha Kim, D. Jeong","doi":"10.1109/ASSCC.2008.4708768","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708768","url":null,"abstract":"This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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