Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708765
T. Hashida, Y. Bando, M. Nagata
Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at 135 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by more than 30 dB, purifying power supply current for internal circuits. Chip-to-chip power line communication invokes supplementary diagnosis functionality to be embedded in SoCs at the time of power connection, with the reduced cost of pin counts.
{"title":"Chip-to-chip half duplex data communication at 135 Mbps over power-supply rails","authors":"T. Hashida, Y. Bando, M. Nagata","doi":"10.1109/ASSCC.2008.4708765","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708765","url":null,"abstract":"Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at 135 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by more than 30 dB, purifying power supply current for internal circuits. Chip-to-chip power line communication invokes supplementary diagnosis functionality to be embedded in SoCs at the time of power connection, with the reduced cost of pin counts.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708715
B. Krenik
Fourth generation (4G) technology will offer many advancements to the wireless market, including downlink data rates well over 100 megabits per second (Mbps), low latency, very efficient spectrum use and low-cost implementations. With impressive network capabilities, 4G enhancements promise to bring the wireless experience to an entirely new level with impressive user applications, such as sophisticated graphical user interfaces, high-end gaming, high-definition video and high-performance imaging. This paper will explore what 4G technology is, as well as some of the key factors that must be addressed to fully comprehend the benefits and challenges of successfully implementing 4G. Silicon level technology issues will be addressed, such as next-generation applications processing, modem technology, power management and integration. Finally, the trends and predictions for 4G network deployment will be discussed.
{"title":"4G wireless technology: When will it happen? What does it offer?","authors":"B. Krenik","doi":"10.1109/ASSCC.2008.4708715","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708715","url":null,"abstract":"Fourth generation (4G) technology will offer many advancements to the wireless market, including downlink data rates well over 100 megabits per second (Mbps), low latency, very efficient spectrum use and low-cost implementations. With impressive network capabilities, 4G enhancements promise to bring the wireless experience to an entirely new level with impressive user applications, such as sophisticated graphical user interfaces, high-end gaming, high-definition video and high-performance imaging. This paper will explore what 4G technology is, as well as some of the key factors that must be addressed to fully comprehend the benefits and challenges of successfully implementing 4G. Silicon level technology issues will be addressed, such as next-generation applications processing, modem technology, power management and integration. Finally, the trends and predictions for 4G network deployment will be discussed.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132136017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708801
Kwang-Chun Choi, Duho Kim, M. Ko, W. Choi
A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18 mum CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply while the chip area is 165 times 110 PMZ. The power-consumption is less than that of the conventional BPSK demodulators and the chip-size is smaller. The proposed circuit is verified by 1-meter 60-GHz wireless link tests with 1-Gb/s data.
{"title":"1-Gb/s mixed-mode BPSK demodulator using a half-rate linear phase detector for 60-GHz wireless PAN applications","authors":"Kwang-Chun Choi, Duho Kim, M. Ko, W. Choi","doi":"10.1109/ASSCC.2008.4708801","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708801","url":null,"abstract":"A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18 mum CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply while the chip area is 165 times 110 PMZ. The power-consumption is less than that of the conventional BPSK demodulators and the chip-size is smaller. The proposed circuit is verified by 1-meter 60-GHz wireless link tests with 1-Gb/s data.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127396378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708734
Y. Ikenaga, M. Nomura, Y. Nakazawa, Y. Hayashi
We have developed a voltage control scheme to reduce control time using a delay monitor and step-by-step supply-voltage control. With this scheme, voltage control steps are adaptively controlled, and there are temporary overshoots in the reference voltage. Experimental results with a 65-nm CMOS device indicate that the adaptive voltage control steps successfully reduce the voltage control time by about 35 % over that with fixed step. Simulation results indicate that temporary reference voltage overshoots reduce control time by more than 50%. The combination of these schemes is also effective for control time reduction.
{"title":"Fast voltage control scheme with adaptive voltage control steps and temporary reference voltage overshoots for dynamic voltage and frequency scaling","authors":"Y. Ikenaga, M. Nomura, Y. Nakazawa, Y. Hayashi","doi":"10.1109/ASSCC.2008.4708734","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708734","url":null,"abstract":"We have developed a voltage control scheme to reduce control time using a delay monitor and step-by-step supply-voltage control. With this scheme, voltage control steps are adaptively controlled, and there are temporary overshoots in the reference voltage. Experimental results with a 65-nm CMOS device indicate that the adaptive voltage control steps successfully reduce the voltage control time by about 35 % over that with fixed step. Simulation results indicate that temporary reference voltage overshoots reduce control time by more than 50%. The combination of these schemes is also effective for control time reduction.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114523573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708820
Seungjin Park, S. Woo, Hyunsoo Ha, Yunjae Suh, Hong-June Park, J. Sim
A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18 mum CMOS, shows a wide lock-range of 10 MHz-1 GHz with the rms jitter of 5.7 ps at 1 GHz.
提出了一种基于晶体管的片上自校正技术，以获得与pvt无关的电路参数。所提出的性能决定晶体管的直接I-V校准方法，在实现复杂度低的情况下，有效地实现了精密电路的稳定运行。作为锁相环设计的一个示例应用，该校准方案可调整压控振荡器增益和电荷泵电流等关键参数，以实现自适应带宽特性。该锁相环采用0.18 μ m CMOS实现，锁相范围为10mhz - 1ghz, 1ghz时的有效值抖动为5.7 ps。
{"title":"A transistor-based background self-calibration for reducing PVT sensitivity with a design example of an adaptive bandwidth PLL","authors":"Seungjin Park, S. Woo, Hyunsoo Ha, Yunjae Suh, Hong-June Park, J. Sim","doi":"10.1109/ASSCC.2008.4708820","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708820","url":null,"abstract":"A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18 mum CMOS, shows a wide lock-range of 10 MHz-1 GHz with the rms jitter of 5.7 ps at 1 GHz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115114929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708784
N. Ickes, D. Finchelstein, A. Chandrakasan
We describe a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 muW (10 pJ per instruction). Architectural optimizations for energy efficiency include a custom CPU instruction set, miniature instruction cache, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory.
{"title":"A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications","authors":"N. Ickes, D. Finchelstein, A. Chandrakasan","doi":"10.1109/ASSCC.2008.4708784","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708784","url":null,"abstract":"We describe a micropower DSP intended for medium bandwidth microsensor applications (such as acoustic sensing and tracking) which achieves 4 MIPS performance at 40 muW (10 pJ per instruction). Architectural optimizations for energy efficiency include a custom CPU instruction set, miniature instruction cache, hardware accelerator cores for FIR filter and FFT operations, and extensive power gating of both logic and memory.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"229 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708806
I-Hsin Wang, Shen-Iuan Liu
A four-bit 10 GSample/sec flash analog-to-digital converter (ADC) with merged interpolation and reference voltage is presented. In this flash ADC, two clock-gated interpolation amplifiers are adopted and the number of resistor strings is reduced. An on-chip phase-locked loop is integrated to double sample the input signal and down sample the converted digital outputs, respectively. Furthermore, a digital-to-analog converter is embedded for the sake of measurements. This chip has been fabricated in 0.13 mum CMOS process and the ADCpsilas power consumption is 115 mW for a 1.2 V supply voltage. This ADC achieves the SNDR of 25 dB, INL of plusmn0.25 LSB, and DNL of plusmn0.5 LSB.
{"title":"A 4-bit 10GSample/sec flash ADC with merged interpolation and reference voltage","authors":"I-Hsin Wang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2008.4708806","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708806","url":null,"abstract":"A four-bit 10 GSample/sec flash analog-to-digital converter (ADC) with merged interpolation and reference voltage is presented. In this flash ADC, two clock-gated interpolation amplifiers are adopted and the number of resistor strings is reduced. An on-chip phase-locked loop is integrated to double sample the input signal and down sample the converted digital outputs, respectively. Furthermore, a digital-to-analog converter is embedded for the sake of measurements. This chip has been fabricated in 0.13 mum CMOS process and the ADCpsilas power consumption is 115 mW for a 1.2 V supply voltage. This ADC achieves the SNDR of 25 dB, INL of plusmn0.25 LSB, and DNL of plusmn0.5 LSB.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129811874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708776
T. Kusumoto, D. Ogawa, K. Dosaka, M. Miyama, Y. Matsuda
A low power and low noise Ternary Content Addressable Memory (TCAM) architecture is proposed. A TCAM is a powerful engine for search and sort processing, but it has serious power consumption and power line noise problems. To solve these problems, we have developed a charge recycling scheme for match lines, search lines and a Checkerboard Array arrangement. By using these technologies, TCAM power and power line noise can be reduced by 50 % when compared with conventional designs.
{"title":"A charge recycling TCAM with Checkerboard Array arrangement for low power applications","authors":"T. Kusumoto, D. Ogawa, K. Dosaka, M. Miyama, Y. Matsuda","doi":"10.1109/ASSCC.2008.4708776","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708776","url":null,"abstract":"A low power and low noise Ternary Content Addressable Memory (TCAM) architecture is proposed. A TCAM is a powerful engine for search and sort processing, but it has serious power consumption and power line noise problems. To solve these problems, we have developed a charge recycling scheme for match lines, search lines and a Checkerboard Array arrangement. By using these technologies, TCAM power and power line noise can be reduced by 50 % when compared with conventional designs.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127415100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708823
Jongsik Kim, Sangwon Han, Tae Wook Kim, Boeun Kim, Hyunchol Shin
A resistively degenerated differential amplifier is linearized by using a source-coupled auxiliary FET pair. The structure does not lower the effective g3 of the degenerated auxiliary FET pair while it efficiently cancels the second harmonic feedback component. Realized in 0.18-mum CMOS, the proposed differential amplifier achieves 9.8 dB of power gain, +7.7 dBm of output P1dB, and +25.8 dBm of peak OIP3. The maximum output power level with OIP3 greater than +20 dBm is extended by 7 ~ 10 dB compared to the conventional structure adopting a source-decoupled auxiliary FET pair. The results prove that the proposed degeneration configuration is suitable for linearizing a resistively degenerated CMOS differential amplifier.
{"title":"A 2.4-GHz CMOS resistively degenerated differential amplifier linearized using source coupled auxiliary FET pair","authors":"Jongsik Kim, Sangwon Han, Tae Wook Kim, Boeun Kim, Hyunchol Shin","doi":"10.1109/ASSCC.2008.4708823","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708823","url":null,"abstract":"A resistively degenerated differential amplifier is linearized by using a source-coupled auxiliary FET pair. The structure does not lower the effective g3 of the degenerated auxiliary FET pair while it efficiently cancels the second harmonic feedback component. Realized in 0.18-mum CMOS, the proposed differential amplifier achieves 9.8 dB of power gain, +7.7 dBm of output P1dB, and +25.8 dBm of peak OIP3. The maximum output power level with OIP3 greater than +20 dBm is extended by 7 ~ 10 dB compared to the conventional structure adopting a source-decoupled auxiliary FET pair. The results prove that the proposed degeneration configuration is suitable for linearizing a resistively degenerated CMOS differential amplifier.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708744
Y. Yoshihara, R. Fujimoto, N. Ono, T. Mitomo, H. Hoshino, M. Hamada
A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.
{"title":"A 60-GHz CMOS power amplifier with Marchand balun-based parallel power combiner","authors":"Y. Yoshihara, R. Fujimoto, N. Ono, T. Mitomo, H. Hoshino, M. Hamada","doi":"10.1109/ASSCC.2008.4708744","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708744","url":null,"abstract":"A novel Marchand balun-based parallel power combiner suitable for a 60-GHz CMOS power amplifier is proposed. It improves the power efficiency by solving the issues of the phase difference of the signals to be combined and the low coupling factor of the on-chip balun in scaled CMOS technologies. The power amplifier using the proposed power combiner is fabricated in a 90 nm CMOS process with 1.2 V supply. Measured power gain, output referred 1-dB compression point, and saturated output power are 11.2 dB, +8.3 dBm, and +11.2 dBm, respectively, at 60-GHz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122241851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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