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2008 IEEE Asian Solid-State Circuits Conference最新文献

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A 6b stochastic flash analog-to-digital converter without calibration or reference ladder 一个6b随机闪光模数转换器,没有校准或参考阶梯
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708805
S. Weaver, B. Hershberg, D. Knierim, U. Moon
A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.
提出了一种6位随机闪存ADC。通过平行连接许多比较器,通过允许随机偏移来设置单个跳闸点,从而避免了参考阶梯。ADC传递函数是比较器偏移量的累积密度函数。提出了一种将传递函数线性度提高8.5 dB的方法。采用0.18 μ m CMOS制造的测试芯片,在900 mV电源和140 mV比较器偏置标准偏差的情况下,实现了超过4.9 b的ENOB,最高可达18 MS/s,比较器是数字单元,允许自动合成。fs = 8 MHz时,核心总功耗为631muW。
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引用次数: 37
A 60-GHz, 14% tuning range, multi-band VCO with a single variable inductor 60 ghz, 14%调谐范围,带单变量电感的多频段压控振荡器
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708746
Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu, Tai-You Lu
This paper presents the design of a 60-GHz, 14% tuning range VCO with a single variable inductor (VID). By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 53.1 to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 times 0.36 mm2.
本文介绍了一种60 ghz、14%调谐范围的单变量电感(VID)压控振荡器的设计。采用所提出的频率调谐方案,在不牺牲其工作频率的情况下,实现了宽调谐范围和多频段操作。该VCO采用90纳米CMOS工艺制造,能够覆盖53.1至61.3 GHz的频率范围。在10mhz偏置时,61.3 ghz载波的相位噪声约为-118.75 dBc/Hz,输出功率为-6.6 dBm。VCO核心从0.7 v电源耗散8.7 mW。芯片尺寸为0.28 × 0.36 mm2。
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引用次数: 18
A wide-range all-digital multiphase DLL with supply noise tolerance 一种宽范围全数字多相DLL,具有电源噪声容限
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708817
Hyunsoo Chae, Dongsuk Shin, Kisoo Kim, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim
An 80-to-832 MHz all-digital 8-differential-phase DLL in a 0.18 um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19 mm2 and dissipates 48 mW at 832 MHz from a 1.8 V supply. The peak-to-peak jitter and rms jitter are 12 ps and 1.73 ps with a quiet supply at 832 MHz, respectively. The peak-to-peak and rms jitter with a 100 mV peak-to-peak triangular supply noise at 100 MHz are 21 ps and 2.99 ps, respectively.
采用双窗口鉴相器、容噪延迟单元和电源噪声下的延迟补偿技术,开发了一种80 ~ 832 MHz全数字8差相DLL,实现了低抖动和电源噪声容限。所提出的DLL占用0.19 mm2,从1.8 V电源在832 MHz时耗散48 mW。峰值抖动和均方根抖动分别为12ps和1.73 ps,在832 MHz的安静电源下。在100 MHz下,100 mV峰对峰三角形电源噪声的峰对峰抖动和均方根抖动分别为21 ps和2.99 ps。
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引用次数: 6
A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS 一个1.6mm2 4,096个逻辑元件的90nm CMOS多上下文FPGA核心
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708736
N. Miyamoto, T. Ohmi
In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 times 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36 mm times 1.15 mm in 90 nm CMOS technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SR-TCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.
在本文中,我们提出了一个动态可重构的多上下文FPGA核心,称为柔性处理器IV (FP4)。FP4包含16乘以16的物理逻辑元素(LE)和16个上下文存储平面,因此实际上总共有4,096个LE可用。在90纳米CMOS技术中,核心尺寸仅为1.36 mm乘以1.15 mm。FP4的一个关键问题是防止多上下文执行速度的下降。因此,我们开发了移位寄存器型时序通信模块(SR-TCM)和设计自动化软件PELOC。PELOC可以将大于FP4物理容量的电路划分为几个较小的子电路,同时保持所有子电路之间的关键路径延迟相等。通过使用SR-TCM和PELOC,我们证实了FP4的执行速度几乎是恒定的,无论使用多少上下文。
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引用次数: 9
A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset 带有四分之一速率线性鉴相器的3.2 gb /s收发器,减少了相位偏移
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708767
Kyung-Soo Ha, L. Kim
In this paper, the transceiver which incorporates a PLL using a ring voltage-controlled oscillator (VCO), a phase interpolator (PI), the quarter-rate linear phase detector (PD) and an output driver with pre-emphasis is presented. The phase detector which uses a clock whose frequency is a quarter of the data rate and reduces the phase offset is proposed. The transceiver, implemented in a 0.18-mum CMOS technology, operates at 3.2-Gb/s over a 10-cm PCB line with the bit error rate (BER) of less than 10-12. The chip area is 3.7 times 2.5 mm2 and the core without I/O consumes 45-mA and I/O buffers consume 80-mA from a 1.8-V supply.
本文介绍了一种由环压控振荡器(VCO)、相位插补器(PI)、四分之一速率线性鉴相器(PD)和前置输出驱动器组成的锁相环收发器。提出了一种采用频率为数据速率的四分之一的时钟并减小相位偏移的鉴相器。该收发器采用0.18 μ m CMOS技术,在10厘米的PCB线上以3.2 gb /s的速度运行,误码率(BER)小于10-12。芯片面积为3.7乘以2.5 mm2,无I/O的核心消耗45 ma, I/O缓冲消耗80 ma,来自1.8 v电源。
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引用次数: 1
A sub-1v low-dropout regulator with an on-chip voltage reference 具有片上基准电压的低于1v的低压差稳压器
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708754
Wei-Jen Huang, Shen-Iuan Liu
A sub-1V 50 mA low-dropout regulator (LDR) with an on-chip voltage reference is presented. This LDR utilizes the push-pull output stage to reduce the size of the power PMOS transistor. The proposed LDR with the on-chip voltage reference has been fabricated in 0.18 mum CMOS process, and its active area is 0.148 mm2. Experimental results demonstrate that the voltage reference and the LDR work for the supply voltage of 0.6 V~1.2V. For the proposed LDR under a supply of 0.6 V, the measured settling time, voltage dip, and quiescent current are less than 2mus, 50 mV, and 16.6 muA, respectively.
提出了一种具有片上基准电压的低于1v的50ma低压差稳压器(LDR)。该LDR利用推挽输出级来减小功率PMOS晶体管的尺寸。采用0.18 μ m CMOS工艺制作了片上基准电压的LDR,其有源面积为0.148 mm2。实验结果表明,基准电压和LDR工作在0.6 V~1.2V的电源电压范围内。在0.6 V电源下,LDR的稳定时间、电压降和静态电流分别小于2mus、50mv和16.6 muA。
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引用次数: 1
A low-noise self-calibrating dynamic comparator for high-speed ADCs 一种用于高速adc的低噪声自校准动态比较器
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708780
M. Miyahara, Y. Asada, Daehwa Paik, Akira Matsuzawa
This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.
本文提出了一种采用自校准技术的低偏置电压、低噪声动态锁存比较器。新的校准技术不需要任何放大器来抵消偏置电压和静态电流。在低功耗下,在1 σ时可实现1.69 mV的低失调电压,而在不校准的情况下可测量13.7 mV。此外,所提议的比较器只需要一个相位时钟,而传统上需要两个相位时钟,导致时钟松弛。此外,在1 σ处获得了0.6 mV的低输入噪声,比传统输入噪声低三倍。原型比较器采用90nm 10M1P CMOS技术实现。实验和仿真结果表明,该比较器在250 MHz工作时实现1.69 mV偏置,功耗为40 muW/GHz (20 fJ/conv)。从1.0 V电源。
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引用次数: 377
An 8mW 10b 50MS/s pipelined ADC using 25dB opamp 一个8mW 10b 50MS/s的流水线ADC,使用25dB运放
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708726
Min Gyu Kim, V. Kratyuk, P. Hanumolu, G. Ahn, Sunwoo Kwon, U. Moon
In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.
提出了一种10位50ms /s的流水线ADC。在MDAC操作中使用了一个25db开环直流增益放大器。由于使用参考缩放方案与背景偏移校准相结合,因此可以容忍极端的低opamp直流增益。在管道中插入一个中间增益级,以补偿基准和信号摆幅的累积减小。采用90 nm CMOS工艺实现的原型IC实现了-63.2 dB THD, 48.8 dB SNR和48.6 dB SNDR,同时从1 V电源消耗8 mW。
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引用次数: 3
Design and performance evaluation of an 8-processor 8,640 MIPS SoC with overhead reduction of interrupt handling in a multi-core system 在多核系统中减少中断处理开销的8处理器8640 MIPS SoC的设计和性能评估
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708761
Huong Thien Hoang, P. T. Vo, Y. T. Vo, Liem Tan Pham, N. Otsuki, M. Ito, O. Nishii
We have developed a platform SoC including eight SuperH processor cores for high performance applications. It achieves 8,640 MIPS at 600 MHz for Dhrystone 2.1. The eight processor cores are divided into two clusters. Each cluster has a snoop controller to maintain cache coherency. The main internal system bus, packet-based split transaction, is 64 bits wide and runs at 300 MHz. As increasing number of processor cores in the system, enhancing overall system performance and optimizing power are important aims and design challenges. In this paper, we introduce one scheme to improve the system performance by reducing overhead of interrupt handling in multi-core system. We have added an automatic-rotating interrupt distribution scheme to processor cores to reduce overhead in handling interrupt requests. As a result, the processing time in Linux kernel is improved by 21% when SPLASH-2 is executed.
我们开发了一个平台SoC,包括八个SuperH处理器内核,用于高性能应用。Dhrystone 2.1在600 MHz时达到8,640 MIPS。8个处理器核心被分为两个集群。每个集群都有一个snoop控制器来维护缓存一致性。主要的内部系统总线,基于分组的分割事务,是64位宽,运行在300mhz。随着系统中处理器内核数量的增加,提高系统整体性能和优化功耗是重要的目标和设计挑战。本文介绍了一种在多核系统中通过减少中断处理开销来提高系统性能的方案。我们为处理器内核添加了一个自动旋转的中断分配方案,以减少处理中断请求的开销。因此,当执行SPLASH-2时,Linux内核中的处理时间提高了21%。
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引用次数: 1
Aiming for an environmental-oriented CE platform 以环境为导向的CE平台为目标
Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708713
Y. Kushiki
I have lived through an epic technological revolution, the digitization of analog products. As a part of that, Panasonic helped to build the digital networking world by developing a semiconductor-based integrated platform, the UniPhier. The twenty-first century will become the ubiquitous + eco-friendly era, in which we will seek drastic energy savings in both products and networks. In the future, we aim to assimilate all of our individual energy-saving technologies into an eco-friendly architecture on the CE platform, and to develop appliances and systems that optimize energy usage in the home. Our concept is an autonomous, coexisting, controllable, decentralized system that incorporates an autonomous optimizing model and embeds an energy management OS. By expanding this system from the home to the social infrastructure, we aim to get closer to realizing a society whose energy usage is optimized for the ecology.
我经历了一场史诗般的技术革命,模拟产品的数字化。作为其中的一部分,松下通过开发基于半导体的集成平台UniPhier帮助建立了数字网络世界。21世纪将成为无处不在+生态友好的时代,我们将在产品和网络上寻求大幅节能。未来,我们的目标是将我们所有的节能技术融入到CE平台上的环保建筑中,并开发优化家庭能源使用的电器和系统。我们的概念是一个自主的、共存的、可控的、分散的系统,它包含了一个自主的优化模型,并嵌入了一个能源管理操作系统。通过将这个系统从家庭扩展到社会基础设施,我们的目标是更接近实现一个能源使用为生态优化的社会。
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引用次数: 0
期刊
2008 IEEE Asian Solid-State Circuits Conference
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