Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708777
Shinya Kajiyama, M. Fujito, Hideo Kasai, M. Mizuno, T. Yamaguchi, Y. Shinagawa
We propose a novel 300 MHz embedded flash memory for dual-core microcontrollers targeting shared ROM architecture. One of the features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduced performance penalty due to shared ROM access conflict. The second feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch because of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and the proposed sense amplifiers achieves significant reduction in access-conflict penalties with shared ROM and enhanced performance of 32-bit RISC dual-core microcontrollers by 30%.
{"title":"A 300 MHz embedded flash memory with pipeline architecture and offset-free sense amplifiers for dual-core automotive microcontrollers","authors":"Shinya Kajiyama, M. Fujito, Hideo Kasai, M. Mizuno, T. Yamaguchi, Y. Shinagawa","doi":"10.1109/ASSCC.2008.4708777","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708777","url":null,"abstract":"We propose a novel 300 MHz embedded flash memory for dual-core microcontrollers targeting shared ROM architecture. One of the features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduced performance penalty due to shared ROM access conflict. The second feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch because of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and the proposed sense amplifiers achieves significant reduction in access-conflict penalties with shared ROM and enhanced performance of 32-bit RISC dual-core microcontrollers by 30%.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132619066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708743
A. Natarajan, S. Nicolson, Ming-Da Tsai, B. Floyd
A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.
{"title":"A 60GHz variable-gain LNA in 65nm CMOS","authors":"A. Natarajan, S. Nicolson, Ming-Da Tsai, B. Floyd","doi":"10.1109/ASSCC.2008.4708743","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708743","url":null,"abstract":"A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131777084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708760
Kwanho Kim, Joo-Young Kim, Seungjin Lee, Minsu Kim, H. Yoo
A 76.8 GB/s 46 mW low-latency network-on-chip (NoC) provides a communication platform for a real-time object recognition processor. The tree-based topology NoC with three crossbar switches is designed for low-latency by adopting dual-channel and adaptive switching. The NoC can be dynamically configured to exploit both data-level and object-level parallelism on the object recognition processor. FLIT-level clock gating and packet-based power management scheme are employed for low power consumption. The NoC is implemented in 0.13 mum CMOS process and provides 76.8 GB/s aggregated bandwidth at 400 MHz with 2-clock cycle latency while dissipating 46 mW at 1.2 V.
{"title":"A 76.8 GB/s 46 mW low-latency network-on-chip for real-time object recognition processor","authors":"Kwanho Kim, Joo-Young Kim, Seungjin Lee, Minsu Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708760","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708760","url":null,"abstract":"A 76.8 GB/s 46 mW low-latency network-on-chip (NoC) provides a communication platform for a real-time object recognition processor. The tree-based topology NoC with three crossbar switches is designed for low-latency by adopting dual-channel and adaptive switching. The NoC can be dynamically configured to exploit both data-level and object-level parallelism on the object recognition processor. FLIT-level clock gating and packet-based power management scheme are employed for low power consumption. The NoC is implemented in 0.13 mum CMOS process and provides 76.8 GB/s aggregated bandwidth at 400 MHz with 2-clock cycle latency while dissipating 46 mW at 1.2 V.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126372744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708723
Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi
A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.
{"title":"An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility","authors":"Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi","doi":"10.1109/ASSCC.2008.4708723","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708723","url":null,"abstract":"A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122917085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708803
J. Daniels, W. Dehaene, M. Steyaert, A. Wiesbauer
A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.
{"title":"A 350-MHz combined TDC-DTC With 61 ps resolution for asynchronous ΔΣ ADC applications","authors":"J. Daniels, W. Dehaene, M. Steyaert, A. Wiesbauer","doi":"10.1109/ASSCC.2008.4708803","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708803","url":null,"abstract":"A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125579491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708814
M. Ker, Cheng-Cheng Yen, C. Liao, Tung-Yang Chen, Chih-Chung Tsai
An on-chip transient-to-digital converter for system-level electrostatic discharge (ESD) protection is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients during the system-level ESD events. The output digital thermometer codes can correspond to different ESD voltages under system-level ESD tests. The experimental results in a 0.18-mum CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.
提出了一种用于系统级静电放电(ESD)保护的片上瞬态-数字转换器。所提出的瞬态-数字转换器旨在检测系统级ESD事件期间的快速电瞬态。在系统级ESD测试中，输出的数字温度计代码可以对应不同的ESD电压。在3.3 v器件的0.18 μ m CMOS集成电路(IC)上的实验结果证实了该检测功能和数字输出代码。
{"title":"Transient-to-digital converter for ESD protection design in microelectronic systems","authors":"M. Ker, Cheng-Cheng Yen, C. Liao, Tung-Yang Chen, Chih-Chung Tsai","doi":"10.1109/ASSCC.2008.4708814","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708814","url":null,"abstract":"An on-chip transient-to-digital converter for system-level electrostatic discharge (ESD) protection is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients during the system-level ESD events. The output digital thermometer codes can correspond to different ESD voltages under system-level ESD tests. The experimental results in a 0.18-mum CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116973090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708802
J. Ryckaert, J. Borremans, B. Verbruggen, J. Van Driessche, L. Van der Perre, J. Craninckx, G. van der Plas
A 6th order RF bandpass SigmaDelta ADC operating on the 2.4 GHz ISM band is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators. By using a mirrored-image sampling technique, the clock frequency is reduced to 3 GS/s, thereby reducing the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR respectively on a 60 MHz bandwidth with 40 mW of power consumption.
{"title":"A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored-image RF bandpass ΣΔ ADC in 90nm CMOS","authors":"J. Ryckaert, J. Borremans, B. Verbruggen, J. Van Driessche, L. Van der Perre, J. Craninckx, G. van der Plas","doi":"10.1109/ASSCC.2008.4708802","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708802","url":null,"abstract":"A 6th order RF bandpass SigmaDelta ADC operating on the 2.4 GHz ISM band is presented. The bandpass loop filter is based on digitally programmable Gm-LC resonators. By using a mirrored-image sampling technique, the clock frequency is reduced to 3 GS/s, thereby reducing the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40 dB and 62 dB of SNDR and SFDR respectively on a 60 MHz bandwidth with 40 mW of power consumption.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115677723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708766
Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu
A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.
{"title":"A 15–20GHz delay-locked loop in 90nm CMOS technology","authors":"Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2008.4708766","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708766","url":null,"abstract":"A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129820120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708774
Keunsoo Song, Cheul-Hee Koo, N. Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.
{"title":"A single-loop DLL using an OR-AND duty-cycle correction technique","authors":"Keunsoo Song, Cheul-Hee Koo, N. Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung","doi":"10.1109/ASSCC.2008.4708774","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708774","url":null,"abstract":"In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708770
Y. Lee, S. Sheikhaei, S. Mirabbasi
A PMOS-based active inductor circuit for high-speed I/O applications is presented. The active inductor can operate with low voltage headroom and requires no voltage boosting. A prototype output driver circuit using the active inductor is implemented in 90 nm CMOS. The peaking frequency and its corresponding gain magnitude of the active-inductor circuit can be adjusted to facilitate channel loss compensation. Operating at 10 Gb/s over a 6-in FR4 channel, as compared to the case when the active-inductor structure is disabled, the use of active inductor circuit in the transmitter side increases the vertical eye opening at the receiver side by a factor of two and reduces the peak-to-peak jitter of the received data by 30%. By keeping the current of the active inductor above a certain value, impedance variations are minimized and appropriate impedance matching is achieved (S22 less than -10 dB). The active-inductor circuit occupies 17 times 25 mum2 and has a low overhead power consumption of 0.8 mW, i.e., ~10% of the overall power of the prototype output driver.
{"title":"A 10Gb/s active-inductor structure with peaking control in 90nm CMOS","authors":"Y. Lee, S. Sheikhaei, S. Mirabbasi","doi":"10.1109/ASSCC.2008.4708770","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708770","url":null,"abstract":"A PMOS-based active inductor circuit for high-speed I/O applications is presented. The active inductor can operate with low voltage headroom and requires no voltage boosting. A prototype output driver circuit using the active inductor is implemented in 90 nm CMOS. The peaking frequency and its corresponding gain magnitude of the active-inductor circuit can be adjusted to facilitate channel loss compensation. Operating at 10 Gb/s over a 6-in FR4 channel, as compared to the case when the active-inductor structure is disabled, the use of active inductor circuit in the transmitter side increases the vertical eye opening at the receiver side by a factor of two and reduces the peak-to-peak jitter of the received data by 30%. By keeping the current of the active inductor above a certain value, impedance variations are minimized and appropriate impedance matching is achieved (S22 less than -10 dB). The active-inductor circuit occupies 17 times 25 mum2 and has a low overhead power consumption of 0.8 mW, i.e., ~10% of the overall power of the prototype output driver.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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