Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708783
Chih-Jen Cheng, Chung-Jui Wu, Shuenn-Yuh Lee
A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-mum CMOS technology, consuming total power of 1.29 muW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a power-supply rejection ratio (PSRR) of -30 dB with the output ripple of 570 muVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 muA, LDO yields a line regulation that is less than 3% deviation.
介绍了一种新型的双电压起搏系统。为了减小电源电压纹波和减小施加在分路电阻上的工艺变化，提出了一种全片上低差(LDO)稳压器。同时，利用可调节的起搏电路和感觉反馈，传递16阶振幅的电刺激，诱导心脏收缩。采用台积电0.35 μ m CMOS工艺制作了带LDO稳压器的起搏器电路，其中1.2 v LDO的接地电流为185 nA, 1 v起搏器步进控制器的功耗为30 nW，总功耗为1.29 muW。实验结果表明，在输入正弦波为19.6 mVpp的情况下，LDO稳压器的电源抑制比(PSRR)为-30 dB，输出纹波为570 muVpp。即使负载电流高达10mua, LDO也能产生小于3%偏差的线路调节。
{"title":"Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker","authors":"Chih-Jen Cheng, Chung-Jui Wu, Shuenn-Yuh Lee","doi":"10.1109/ASSCC.2008.4708783","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708783","url":null,"abstract":"A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-mum CMOS technology, consuming total power of 1.29 muW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a power-supply rejection ratio (PSRR) of -30 dB with the output ripple of 570 muVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 muA, LDO yields a line regulation that is less than 3% deviation.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121835899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708821
Shih-Chun Lin, Tai-Cheng Lee
An 833-MHz 132-phase clock generator with self-calibrated circuits is presented. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phases is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-mum CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply.
介绍了一种带有自校准电路的833 mhz 132相时钟发生器。由于输出相位数是两个延迟锁环的级数的乘积，因此使用两个延迟锁环有效地产生相位。提出了一种采用顺序比较法的动态链接库标定算法。校准电路只需要一个电荷泵和一个鉴相器，所有输出信号经过同一路径。因此，可以避免器件失配的影响，并且可以消除路径的失配。这种带有自校准电路的多相时钟发生器采用0.13 μ m CMOS技术制造，同时从单个1.2 v电源消耗67.2 mW。
{"title":"An 833-MHz 132-phase multiphase clock generator with self-calibration circuits","authors":"Shih-Chun Lin, Tai-Cheng Lee","doi":"10.1109/ASSCC.2008.4708821","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708821","url":null,"abstract":"An 833-MHz 132-phase clock generator with self-calibrated circuits is presented. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phases is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-mum CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121983320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708756
D. Finchelstein, V. Sze, M. Sinangil, Y. Koken, A. Chandrakasan
The H.264/AVC video coding standard can deliver high compression efficiency at a cost of large complexity and power. The increasing popularity of video capture and playback on portable devices requires that the energy of the video codec be kept to a minimum. This paper proposes several architecture optimizations such as increased parallelism, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation and reduce the power of a high-definition decoder. An H.264/AVC Baseline Level 3.1 decoder ASIC was fabricated in 65 nm CMOS and verified. It operates down to 0.7-V and has a measured power of 1.8 mW when decoding a high definition 720 p video at 30 frames per second, which is over an order of magnitude lower than previously published results.
{"title":"A low-power 0.7-V H.264 720p video decoder","authors":"D. Finchelstein, V. Sze, M. Sinangil, Y. Koken, A. Chandrakasan","doi":"10.1109/ASSCC.2008.4708756","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708756","url":null,"abstract":"The H.264/AVC video coding standard can deliver high compression efficiency at a cost of large complexity and power. The increasing popularity of video capture and playback on portable devices requires that the energy of the video codec be kept to a minimum. This paper proposes several architecture optimizations such as increased parallelism, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation and reduce the power of a high-definition decoder. An H.264/AVC Baseline Level 3.1 decoder ASIC was fabricated in 65 nm CMOS and verified. It operates down to 0.7-V and has a measured power of 1.8 mW when decoding a high definition 720 p video at 30 frames per second, which is over an order of magnitude lower than previously published results.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122181295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708737
K. Ikeuchi, K. Inagaki, H. Kusamitsu, T. Ito, M. Takamiya, T. Sakurai
Using capacitively coupled signaling, the feasibility of implementing an electronic connector as short as 240 mum in height is demonstrated for the first time using 0.18 mum CMOS technology and 125 mum FR4 printed circuit boards (PCBs). Maximum data rate of 500 Mbps/pin and 3.6 Gbps/mm2 are measured with 670 muW/pin of power consumption even with large parasitic capacitance associated with the FR4 board. Compared to the conventional circuits, the proposed self reset circuit can send signals 2.8x faster at the same parasitic capacitance or allow 6x more parasitic capacitance at the same data rate.
利用电容耦合信号，首次证明了使用0.18 μ m CMOS技术和125 μ m FR4印刷电路板(pcb)实现短至240 μ m高度的电子连接器的可行性。最大数据速率为500 Mbps/引脚和3.6 Gbps/mm2，功耗为670 muW/引脚，即使与FR4板相关的寄生电容很大。与传统电路相比，所提出的自复位电路在相同的寄生电容下发送信号速度提高2.8倍，或在相同的数据速率下允许6倍的寄生电容。
{"title":"500Mbps, 670μW/pin capacitively coupled receiver with self reset scheme for wireless connectors","authors":"K. Ikeuchi, K. Inagaki, H. Kusamitsu, T. Ito, M. Takamiya, T. Sakurai","doi":"10.1109/ASSCC.2008.4708737","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708737","url":null,"abstract":"Using capacitively coupled signaling, the feasibility of implementing an electronic connector as short as 240 mum in height is demonstrated for the first time using 0.18 mum CMOS technology and 125 mum FR4 printed circuit boards (PCBs). Maximum data rate of 500 Mbps/pin and 3.6 Gbps/mm2 are measured with 670 muW/pin of power consumption even with large parasitic capacitance associated with the FR4 board. Compared to the conventional circuits, the proposed self reset circuit can send signals 2.8x faster at the same parasitic capacitance or allow 6x more parasitic capacitance at the same data rate.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708819
Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu
In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.
{"title":"20Gb/s 1/4-rate and 40Gb/s 1/8-rate burst-mode CDR circuits in 0.13 μm CMOS","authors":"Hong-Lin Chu, Chang-Lin Hsieh, Shen-luan Liu","doi":"10.1109/ASSCC.2008.4708819","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708819","url":null,"abstract":"In this paper, 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate burst-mode clock and data recovery (BMCDR) circuits are presented. The proposed inductorless gated digitally-controlled oscillator using a digitally frequency calibration loop is presented. These two BMCDR circuits have been fabricated in 0.13..m CMOS technology. For a PRBS of 27-1, the measured peak-to-peak jitter of the recovered clock for the 20 Gb/s 1/4-rate and 40 Gb/s 1/8-rate BMCDR circuits is 23.8 ps and 51 ps, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132784308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708827
A. Bansal, C. Heng, Yuanjin Zheng
A 2 GHz CMOS VCO, employing noise cancellation to eliminate flicker noise up-conversion, has been fabricated in 0.35 mum CMOS. An overall phase noise reduction of 10 dB has been measured with the proposed technique, and phase noise of -121.6 dBc/Hz@500 kHz offset has been achieved. The VCO core consumes 2.8 mA under 2.4V supply and occupies an area of 0.7 mmtimes0.8 mm. The proposed VCO measured FOM of -186 dBc/Hz.
采用噪声消除技术，在0.35 μ m CMOS上变频制备了一种2 GHz CMOS压控振荡器。采用所提出的技术，总体相位噪声降低了10 dB，相位噪声达到-121.6 dBc/Hz@500 kHz偏置。在2.4V电源下，VCO芯线功耗为2.8 mA，面积为0.7 mm × 0.8 mm。所提出的压控振荡器的测量频率为-186 dBc/Hz。
{"title":"2GHz CMOS noise cancellation VCO","authors":"A. Bansal, C. Heng, Yuanjin Zheng","doi":"10.1109/ASSCC.2008.4708827","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708827","url":null,"abstract":"A 2 GHz CMOS VCO, employing noise cancellation to eliminate flicker noise up-conversion, has been fabricated in 0.35 mum CMOS. An overall phase noise reduction of 10 dB has been measured with the proposed technique, and phase noise of -121.6 dBc/Hz@500 kHz offset has been achieved. The VCO core consumes 2.8 mA under 2.4V supply and occupies an area of 0.7 mmtimes0.8 mm. The proposed VCO measured FOM of -186 dBc/Hz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123663767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 12th order active-RC filter for DVB Tuner applications with automatic frequency tuning (AFT) is presented in this paper. The filter is implemented in Butterworth biquad structure. The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched-capacitor array. The measurement results indicate that the precision of tuning circuit can be controlled less than plusmn2.3%, the in-band group delay variation is 70 ns, and the in-band IM3 achieves -60 dB with -27 dbm input power. This proposed filter circuit, fabricated in a SMIC 0.18 mum CMOS process, consumes 6 mA current with 1.8 V power supply.
提出了一种用于DVB自动调谐调谐器的12阶有源rc滤波器。该滤波器采用巴特沃斯双单元结构实现。引入了AFT电路，通过7位开关电容阵列补偿频率变化。测量结果表明，调谐电路的精度可控制在±2.3%以内，带内群延迟变化为70 ns，带内IM3在输入功率为-27 dbm时可达到-60 dB。该滤波电路采用中芯国际0.18 μ m CMOS工艺，在1.8 V电源下消耗6 mA电流。
{"title":"A 12th order active-RC filter with automatic frequency tuning for DVB Tuner applications","authors":"Liang Zou, Kefeng Han, Youchun Liao, Hao Min, Zhangwen Tang","doi":"10.1109/ASSCC.2008.4708782","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708782","url":null,"abstract":"A 12th order active-RC filter for DVB Tuner applications with automatic frequency tuning (AFT) is presented in this paper. The filter is implemented in Butterworth biquad structure. The AFT circuit is introduced to compensate the frequency variation by a 7-bits switched-capacitor array. The measurement results indicate that the precision of tuning circuit can be controlled less than plusmn2.3%, the in-band group delay variation is 70 ns, and the in-band IM3 achieves -60 dB with -27 dbm input power. This proposed filter circuit, fabricated in a SMIC 0.18 mum CMOS process, consumes 6 mA current with 1.8 V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124196350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708791
Hyejung Kim, Yongsang Kim, H. Yoo
A low energy sensor node processor is proposed for continuous healthcare monitoring application. The bio signal processing block is integrated into the processor to support the compression and the encryption. A quadratic level bio signal compression algorithm is proposed to reduce the transmission power consumption and the memory capacity. And the AES-128 data encryption datapath is integrated for user privacy and authentication. The CR is 8.4:1, the PRD is 0.897% and the compression rate is 6.4 Mbps. The encryption rate is 1.6 Mbps and the normalized performance is 0.4b/cycle/k-gates which is the highest value compared to the related works. The proposed processor consumes 0.56 nJ/bit at 1V supply voltage with 1MHz operating frequency in 0.25-mum CMOS process.
提出了一种低功耗传感器节点处理器，用于连续健康监测。将生物信号处理块集成到处理器中，支持压缩和加密。为了降低传输功耗和存储容量，提出了一种二次级生物信号压缩算法。并集成了AES-128数据加密数据路径，实现了用户隐私和身份验证。CR为8.4:1,PRD为0.87%，压缩率为6.4 Mbps。加密速率为1.6 Mbps，标准化性能为0.4b/cycle/k-gates，是目前相关工作中最高的。该处理器采用0.25 μ m CMOS工艺，在1V电源电压和1MHz工作频率下功耗为0.56 nJ/bit。
{"title":"A low energy bio sensor node processor for continuous healthcare monitoring system","authors":"Hyejung Kim, Yongsang Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708791","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708791","url":null,"abstract":"A low energy sensor node processor is proposed for continuous healthcare monitoring application. The bio signal processing block is integrated into the processor to support the compression and the encryption. A quadratic level bio signal compression algorithm is proposed to reduce the transmission power consumption and the memory capacity. And the AES-128 data encryption datapath is integrated for user privacy and authentication. The CR is 8.4:1, the PRD is 0.897% and the compression rate is 6.4 Mbps. The encryption rate is 1.6 Mbps and the normalized performance is 0.4b/cycle/k-gates which is the highest value compared to the related works. The proposed processor consumes 0.56 nJ/bit at 1V supply voltage with 1MHz operating frequency in 0.25-mum CMOS process.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130401905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708757
Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, H. Yoo
A 66 fps 38 mW nearest neighbor matching processor for real-time object recognition has been fabricated in 0.13 mum CMOS technology. It consists of RISC processing core, pre-fetch DMA, and two independent sets of logic merged memories. Based on hierarchical vector quantization (H-VQ) algorithm, implemented processor achieves 22.5X cycle time reduction in matching process without any accuracy loss in VQ operation. As a result, 66 fps frame rate is obtained for QVGA (320times240 pixels) video images with 5632-entry database.
采用0.13 μ m CMOS技术，研制了一种66fps、38mw的实时目标识别最近邻匹配处理器。它由RISC处理核、预取DMA和两组独立的逻辑合并存储器组成。基于层次矢量量化(H-VQ)算法，实现的处理器在匹配过程中减少22.5倍的周期时间，且不损失VQ操作的精度。因此，在5632个条目的数据库中，QVGA (320times240像素)视频图像的帧率为66 fps。
{"title":"A 66fps 3 8mW nearest neighbor matching processor with hierarchical VQ algorithm for real-time object recognition","authors":"Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, H. Yoo","doi":"10.1109/ASSCC.2008.4708757","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708757","url":null,"abstract":"A 66 fps 38 mW nearest neighbor matching processor for real-time object recognition has been fabricated in 0.13 mum CMOS technology. It consists of RISC processing core, pre-fetch DMA, and two independent sets of logic merged memories. Based on hierarchical vector quantization (H-VQ) algorithm, implemented processor achieves 22.5X cycle time reduction in matching process without any accuracy loss in VQ operation. As a result, 66 fps frame rate is obtained for QVGA (320times240 pixels) video images with 5632-entry database.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708792
Xinkai Chen, Xiaoyu Zhang, Lingwei Zhang, Nan Qi, Hanjun Jiang, Zhihua Wang
This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.
本文介绍了一种采用低功耗ASIC控制和处理的无线胶囊内镜系统的设计。该系统旨在解决系统功耗降低、系统小型化和无线唤醒等设计难题。ASIC设计采用优化的系统架构，集成了面积和功耗高效的图像压缩模块，电源管理单元(PMU)和具有零待机电流的新型无线唤醒子系统，以应对这些挑战。该ASIC采用0.18 mm CMOS技术制造，其芯片面积为3.4 mm*3.3 mm。数字核心可以在低至0.95V的电源下工作，功耗仅为1.3 mW。无线胶囊内窥镜原型已经用该ASIC实现。
{"title":"A wireless capsule endoscopic system with a low-power controlling and processing ASIC","authors":"Xinkai Chen, Xiaoyu Zhang, Lingwei Zhang, Nan Qi, Hanjun Jiang, Zhihua Wang","doi":"10.1109/ASSCC.2008.4708792","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708792","url":null,"abstract":"This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129418905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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