Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708809
T. Sato, H. Ueyama, N. Nakayama, K. Masu
Transistor array design for accurate sub-threshold current measurement is proposed. The proposed array achieves both compact layout area and pico-ampere order precision, which is particularly useful in off-state current variation characterization. The effect of masking current caused by the transistors that share the same measurement PAD is carefully eliminated using leakage cut-off switches and potential equalizing supply. Experimental array design consisting of 1023 low threshold voltage devices demonstrated accurate measurement of subthreshold leakage current with precision of 10-pA.
{"title":"A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation","authors":"T. Sato, H. Ueyama, N. Nakayama, K. Masu","doi":"10.1109/ASSCC.2008.4708809","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708809","url":null,"abstract":"Transistor array design for accurate sub-threshold current measurement is proposed. The proposed array achieves both compact layout area and pico-ampere order precision, which is particularly useful in off-state current variation characterization. The effect of masking current caused by the transistors that share the same measurement PAD is carefully eliminated using leakage cut-off switches and potential equalizing supply. Experimental array design consisting of 1023 low threshold voltage devices demonstrated accurate measurement of subthreshold leakage current with precision of 10-pA.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"13 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126103615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708725
Yuanching Lien, Jri Lee
A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.
采用90纳米CMOS技术实现了一个带THA的6-b 1-GS/s分位ADC。该电路集成了用于精细ADC的折叠输入以及失调校准和数字校正技术，实现了高达奈奎斯特的大于5.2 ENOB和40 db SFDR，以及1.1 ghz ERBW，功耗仅为30 mW。
{"title":"A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology","authors":"Yuanching Lien, Jri Lee","doi":"10.1109/ASSCC.2008.4708725","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708725","url":null,"abstract":"A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125032078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708811
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
This paper measures and compares power supply and ground noises in a triple-well structure and a twin-well stricture. The measurement results of power supply and ground waveforms in a 90 nm CMOS process reveal that the power noise reduction thanks to the increased junction capacitance associated with the triple-well structure overwhelms the ground noise suppression due to the resistive network of p-substrate in the twin-well structure. These noise suppression effects are well correlated with the simulation that uses on-chip RC power distribution model with package inductance, chip-level p-substrate resistive mesh and distributed well junction capacitances.
{"title":"Measurement of supply noise suppression by substrate and deep N-well in 90nm process","authors":"Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye","doi":"10.1109/ASSCC.2008.4708811","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708811","url":null,"abstract":"This paper measures and compares power supply and ground noises in a triple-well structure and a twin-well stricture. The measurement results of power supply and ground waveforms in a 90 nm CMOS process reveal that the power noise reduction thanks to the increased junction capacitance associated with the triple-well structure overwhelms the ground noise suppression due to the resistive network of p-substrate in the twin-well structure. These noise suppression effects are well correlated with the simulation that uses on-chip RC power distribution model with package inductance, chip-level p-substrate resistive mesh and distributed well junction capacitances.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708829
Y. Kanazawa, Y. Fujimoto, K. Iizuka
A widely tunable RF LC-tracking filter is developed for tackling the odd harmonic mixing problem in wideband CMOS RF receivers. The filter is composed of two cascaded RLC tanks, where proposed programmable transconductor stages with built-in LPF are used. IIP3 of 127.7 dBmuV and input-referred noise of 20.1 dBmuV over signal band of 5.6 MHz are confirmed by measurements. The chip, fabricated in 0.18 mum CMOS process, occupies 2.8 mm2 and draws 34-120mA from a 1.8V supply.
针对宽带CMOS射频接收机中的奇谐波混频问题，研制了一种宽可调谐射频lc跟踪滤波器。该滤波器由两个级联的RLC罐组成，其中使用内置LPF的可编程变换器级。在5.6 MHz的信号频带上，IIP3为127.7 dBmuV，输入参考噪声为20.1 dBmuV。该芯片采用0.18 μ m CMOS工艺制造，占地2.8 mm2，从1.8V电源输出34-120mA。
{"title":"A 130M to 1GHz digitally tunable RF LC-tracking filter for CMOS RF receivers","authors":"Y. Kanazawa, Y. Fujimoto, K. Iizuka","doi":"10.1109/ASSCC.2008.4708829","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708829","url":null,"abstract":"A widely tunable RF LC-tracking filter is developed for tackling the odd harmonic mixing problem in wideband CMOS RF receivers. The filter is composed of two cascaded RLC tanks, where proposed programmable transconductor stages with built-in LPF are used. IIP3 of 127.7 dBmuV and input-referred noise of 20.1 dBmuV over signal band of 5.6 MHz are confirmed by measurements. The chip, fabricated in 0.18 mum CMOS process, occupies 2.8 mm2 and draws 34-120mA from a 1.8V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122085255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708815
Chao-Ching Hung, Chihun Lee, Lan-chou Cho, Shen-Iuan Liu
In this paper, a 57.1-59 GHz fractional-N frequency synthesizer has been fabricated in 90 nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12 dB with the same PLL bandwidth. It consumes 89 mW from a 1.2 V analog supply with output buffers and 16 mW from a 1.2 V digital supply. The chip occupies 0.86 times1.28 mm2 and the measured phase noise at 58.359375 GHz with the offset frequency of 2 MHz is -95.1 dBc/Hz.
{"title":"A 57.1–59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique","authors":"Chao-Ching Hung, Chihun Lee, Lan-chou Cho, Shen-Iuan Liu","doi":"10.1109/ASSCC.2008.4708815","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708815","url":null,"abstract":"In this paper, a 57.1-59 GHz fractional-N frequency synthesizer has been fabricated in 90 nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12 dB with the same PLL bandwidth. It consumes 89 mW from a 1.2 V analog supply with output buffers and 16 mW from a 1.2 V digital supply. The chip occupies 0.86 times1.28 mm2 and the measured phase noise at 58.359375 GHz with the offset frequency of 2 MHz is -95.1 dBc/Hz.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114673825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708732
Yung-Chih Liang, Ching-Ji Huang, Wei-Bin Yang
This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130 nm CMOS technology, the measured operation rate of 8bit times 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48 mW from 0.5-V power supply.
{"title":"A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage","authors":"Yung-Chih Liang, Ching-Ji Huang, Wei-Bin Yang","doi":"10.1109/ASSCC.2008.4708732","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708732","url":null,"abstract":"This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130 nm CMOS technology, the measured operation rate of 8bit times 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48 mW from 0.5-V power supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121834688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708793
K. Kiyoyama, Y. Tanaka, M. Onoda, T. Fukushima, T. Tanaka, M. Koyanagi
A wireless communication system with a closed-loop power control function for bio-implantable applications is described which keeps the power dissipation of implantable unit at the allowable level for human body. The function is controlled by monitoring an excessive current at the implantable unit and limiting the power transmission at the external interrogator unit. The implantable unit with the closed-loop power control function has been fabricated in a standard 0.18 mum CMOS technology, achieved less than 530 muW with a 1.8 V and the chip core size of 0.14 mm2. The system uses inductive coupling at 13.56 MHz with internal and external coils. Experimental results confirm its stable power supply to the implantable unit over a coil distance of 0.5 to 10 mm.
{"title":"A closed-loop power control function for bio-implantable devices","authors":"K. Kiyoyama, Y. Tanaka, M. Onoda, T. Fukushima, T. Tanaka, M. Koyanagi","doi":"10.1109/ASSCC.2008.4708793","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708793","url":null,"abstract":"A wireless communication system with a closed-loop power control function for bio-implantable applications is described which keeps the power dissipation of implantable unit at the allowable level for human body. The function is controlled by monitoring an excessive current at the implantable unit and limiting the power transmission at the external interrogator unit. The implantable unit with the closed-loop power control function has been fabricated in a standard 0.18 mum CMOS technology, achieved less than 530 muW with a 1.8 V and the chip core size of 0.14 mm2. The system uses inductive coupling at 13.56 MHz with internal and external coils. Experimental results confirm its stable power supply to the implantable unit over a coil distance of 0.5 to 10 mm.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129086897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708810
N. Drego, A. Chandrakasan, D. Boning
Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates specific variation parameters and their measurement approach for use in such models, leading to critical considerations in aggressive voltage scaling systems. We describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring-oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide spatial variation data for digital circuits. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered.
{"title":"An all-digital, highly scalable architecture for measurement of spatial variation in digital circuits","authors":"N. Drego, A. Chandrakasan, D. Boning","doi":"10.1109/ASSCC.2008.4708810","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708810","url":null,"abstract":"Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates specific variation parameters and their measurement approach for use in such models, leading to critical considerations in aggressive voltage scaling systems. We describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring-oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide spatial variation data for digital circuits. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708786
S. Ushiki, K. Nakamura, K. Shimizu, Qi Wang, Y. Abe, S. Goto, T. Ikenaga
This paper presents a high-throughput and highly-reliable baseband processor LSI based on LDPC coding OFDM UWB. This LSI targets for wireless LAN systems inside a car which enable to translate a high-resolution video under noisy environment. A chip capable of operating at 147 MHz was fabricated using UMC 0.13 mum 1P8M CMOS technology. By adopting the OFDM modulation with 1024 sub-carriers, it achieves a throughput of 820 Mb/s and 10-4 BER performance under 30 dB CNR with 5/6 coding rate. Power dissipation is 189 mW/391 mW (TX/RX).
{"title":"A 820 Mb/s baseband processor LSI based on LDPC coded OFDM for UWB systems","authors":"S. Ushiki, K. Nakamura, K. Shimizu, Qi Wang, Y. Abe, S. Goto, T. Ikenaga","doi":"10.1109/ASSCC.2008.4708786","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708786","url":null,"abstract":"This paper presents a high-throughput and highly-reliable baseband processor LSI based on LDPC coding OFDM UWB. This LSI targets for wireless LAN systems inside a car which enable to translate a high-resolution video under noisy environment. A chip capable of operating at 147 MHz was fabricated using UMC 0.13 mum 1P8M CMOS technology. By adopting the OFDM modulation with 1024 sub-carriers, it achieves a throughput of 820 Mb/s and 10-4 BER performance under 30 dB CNR with 5/6 coding rate. Power dissipation is 189 mW/391 mW (TX/RX).","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-12DOI: 10.1109/ASSCC.2008.4708807
B. Chen, Szukang Hsien, C. Chiang, K. Juang
This paper presents a 6-bit, 1.2-GSample/s flash ADC with new proposed wideband track-and-hold amplifier (THA) fabricated in TSMC 0.13-mum CMOS technology. The wideband THA employs a front-end super source follower (SSF), which has a very low input capacitance of only 0.2-pf, to boost analog bandwidth without any on-chip passive inductor. Moreover, the flatness of the data bandwidth of ADC will improve. The SSF can also relax the power consumption of the voltage buffer in the THA.
{"title":"A 6-Bit, 1.2-GS/s ADC with wideband THA in 0.13-μm CMOS","authors":"B. Chen, Szukang Hsien, C. Chiang, K. Juang","doi":"10.1109/ASSCC.2008.4708807","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708807","url":null,"abstract":"This paper presents a 6-bit, 1.2-GSample/s flash ADC with new proposed wideband track-and-hold amplifier (THA) fabricated in TSMC 0.13-mum CMOS technology. The wideband THA employs a front-end super source follower (SSF), which has a very low input capacitance of only 0.2-pf, to boost analog bandwidth without any on-chip passive inductor. Moreover, the flatness of the data bandwidth of ADC will improve. The SSF can also relax the power consumption of the voltage buffer in the THA.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"87 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134351407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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