Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517421
M. Amagai
The reliability of semiconductor devices and packages used in microelectronics is compromised by interfacial delamination and homogenous cracking that is initiated at the edge of the interface between dissimilar materials during processing and stress tests. These failures have certain characteristics in that they begin at the stress singularity point. The knowledge of interfacial fracture mechanics is very important to the design for reliability of these devices and packages. In this paper, a model of stress singularity is proposed and applications of the model for the characterization of interfaces are subsequently presented. Examples are integrated circuit (IC) device interfaces and plastic package interfaces. These interfaces were mainly characterized with the order of stress singularity. Furthermore, this study demonstrates applications of the stress intensity factors for the stress singularity fields. The stress intensity factors were obtained from a r-/spl theta/ coordinate system, the order of stress singularity, the Dunders' parameters, and the extrapolation as a function of distance. The relationship between the stress intensity factors and the interfacial fracture toughness strength as a function of mode mixity was also investigated for delamination at the edge of the interface. The proposed numerical scheme was verified by the experiments on the lead-on-chip (LOC) package delamination in a soldering process.
{"title":"Investigation of stress singularity fields and stress intensity factors for interfacial delamination (an application of thermosetting polyimide for a tapeless lead-on-chip (LOC) package)","authors":"M. Amagai","doi":"10.1109/ECTC.1996.517421","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517421","url":null,"abstract":"The reliability of semiconductor devices and packages used in microelectronics is compromised by interfacial delamination and homogenous cracking that is initiated at the edge of the interface between dissimilar materials during processing and stress tests. These failures have certain characteristics in that they begin at the stress singularity point. The knowledge of interfacial fracture mechanics is very important to the design for reliability of these devices and packages. In this paper, a model of stress singularity is proposed and applications of the model for the characterization of interfaces are subsequently presented. Examples are integrated circuit (IC) device interfaces and plastic package interfaces. These interfaces were mainly characterized with the order of stress singularity. Furthermore, this study demonstrates applications of the stress intensity factors for the stress singularity fields. The stress intensity factors were obtained from a r-/spl theta/ coordinate system, the order of stress singularity, the Dunders' parameters, and the extrapolation as a function of distance. The relationship between the stress intensity factors and the interfacial fracture toughness strength as a function of mode mixity was also investigated for delamination at the edge of the interface. The proposed numerical scheme was verified by the experiments on the lead-on-chip (LOC) package delamination in a soldering process.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"46 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120904983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550809
S. Chew
This paper describes the characterization of epoxy mold compound by subjecting transfer-molded encapsulants to a temperature programme simulating post-mold cure using thermomechanical analysis and dynamic mechanical analysis. The real-time change in dimension and viscoelastic properties of the epoxy encapsulant during an experimental post-mold cure process is measured. Results show evidence of residual cure shrinkage and flexural storage modulus growth occuring during experimental post-mold cure; sharp initially but stabilize subsequently. A minimum post-mold cure duration is recommended in order to ensure optimum dimensional and mechanical stability of the epoxy encapsulant.
{"title":"Thermal and viscoelastic characterization of transfer-molded epoxy encapsulant during simulated post-mold cure","authors":"S. Chew","doi":"10.1109/ECTC.1996.550809","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550809","url":null,"abstract":"This paper describes the characterization of epoxy mold compound by subjecting transfer-molded encapsulants to a temperature programme simulating post-mold cure using thermomechanical analysis and dynamic mechanical analysis. The real-time change in dimension and viscoelastic properties of the epoxy encapsulant during an experimental post-mold cure process is measured. Results show evidence of residual cure shrinkage and flexural storage modulus growth occuring during experimental post-mold cure; sharp initially but stabilize subsequently. A minimum post-mold cure duration is recommended in order to ensure optimum dimensional and mechanical stability of the epoxy encapsulant.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550508
Seung-Soo Han, G. May
Silicon dioxide films deposited by plasma-enhanced chemical vapor deposition PECVD) are useful as interlayer dielectrics for metal-insulator structures such as multichip modules. Due to the complex nature of particle dynamics within a plasma, it is difficult to determine the exact nature of the relationship between PECVD process conditions and their effects on critical output parameters. In this study, neural network process models are used in conjunction with genetic algorithms to determine the necessary process recipes to achieve novel film qualities. To characterize the PECVD process, SiO/sub 2/ films deposited in a plasma-Therm 700 series PECVD system under varying conditions are analyzed using a central composite experimental design. Parameters varied include substrate temperature, pressure, RF power, silane flow and nitrous oxide flow. Data from this experiment is used to train back-propagation neural networks to model deposition rate, refractive index, permittivity, film stress, wet etch rate, uniformity, silanol concentration, and water concentration. A recipe synthesis procedure is then performed using genetic algorithms, Powell's algorithm, the simplex method, and hybrid combinations thereof to generate the necessary deposition conditions to obtain novel film qualities, including zero residual stress, 0% non-uniformity, 0% impurities, and low permittivity. Recipes predicted by these techniques are verified by experiment, and the performance of each synthesis method is compared.
{"title":"Recipe synthesis for PECVD SiO/sub 2/ films using neural networks and genetic algorithms","authors":"Seung-Soo Han, G. May","doi":"10.1109/ECTC.1996.550508","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550508","url":null,"abstract":"Silicon dioxide films deposited by plasma-enhanced chemical vapor deposition PECVD) are useful as interlayer dielectrics for metal-insulator structures such as multichip modules. Due to the complex nature of particle dynamics within a plasma, it is difficult to determine the exact nature of the relationship between PECVD process conditions and their effects on critical output parameters. In this study, neural network process models are used in conjunction with genetic algorithms to determine the necessary process recipes to achieve novel film qualities. To characterize the PECVD process, SiO/sub 2/ films deposited in a plasma-Therm 700 series PECVD system under varying conditions are analyzed using a central composite experimental design. Parameters varied include substrate temperature, pressure, RF power, silane flow and nitrous oxide flow. Data from this experiment is used to train back-propagation neural networks to model deposition rate, refractive index, permittivity, film stress, wet etch rate, uniformity, silanol concentration, and water concentration. A recipe synthesis procedure is then performed using genetic algorithms, Powell's algorithm, the simplex method, and hybrid combinations thereof to generate the necessary deposition conditions to obtain novel film qualities, including zero residual stress, 0% non-uniformity, 0% impurities, and low permittivity. Recipes predicted by these techniques are verified by experiment, and the performance of each synthesis method is compared.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517453
J. Collins, I. Lealman, P.J. Fiddyment, A. Thurlow, C. Ford, D. Rogers, C.A. Jones
Lasers have been passively aligned to cleaved singlemode optical fibres on a silicon bench with coupling efficiencies of over 50%. This is the highest known reported result. Using the relaxed tolerances obtained from large spotsize lasers a very simple high performance laser package has also be produced. The combination of semiconductor device developments, silicon micromachining and novel packaging techniques has realised complicated optoelectronic modules which will give the technical performance and economic requirements needed for future optical telecommunication networks.
{"title":"The packaging of large spot-size optoelectronic devices","authors":"J. Collins, I. Lealman, P.J. Fiddyment, A. Thurlow, C. Ford, D. Rogers, C.A. Jones","doi":"10.1109/ECTC.1996.517453","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517453","url":null,"abstract":"Lasers have been passively aligned to cleaved singlemode optical fibres on a silicon bench with coupling efficiencies of over 50%. This is the highest known reported result. Using the relaxed tolerances obtained from large spotsize lasers a very simple high performance laser package has also be produced. The combination of semiconductor device developments, silicon micromachining and novel packaging techniques has realised complicated optoelectronic modules which will give the technical performance and economic requirements needed for future optical telecommunication networks.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132392978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517441
K. Wun, G. Margaritis
Seven underfill formulations have been evaluated for fast-flow fast-cure and low-clearance flow application for flip chip assembly. The effects of different ingredients are discussed. At least one formulation is found to have superior flow rate under a 30-micron die than any known commercial underfill available so far.
{"title":"The evaluation of fast-flow, fast-cure underfills for flip chip on organic substrates","authors":"K. Wun, G. Margaritis","doi":"10.1109/ECTC.1996.517441","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517441","url":null,"abstract":"Seven underfill formulations have been evaluated for fast-flow fast-cure and low-clearance flow application for flip chip assembly. The effects of different ingredients are discussed. At least one formulation is found to have superior flow rate under a 30-micron die than any known commercial underfill available so far.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114675502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550876
S. Robinson, F. Anigbo, G. Shevchuk
With the growing use of fiber optics in Local Area Networks (LANs), efforts to cost reduce the optical components has intensified. In general, optoelectronic components for Fiber Distributed Data Interface (FDDI) and Fiber Channel LANs have been LED-based Optical Data Links (ODLs). Due to the bi-directional nature of most links, the trend has been towards the integration of simplex optical transmitters and receivers into Optical Transceivers. Further cost reductions through the use of automated assembly processes such as two step overmolding have also been reported recently. In this paper, we propose a molding technique designed to further cost reduce optoelectronic devices. The technique involves the use of a one-step overmolding process to encapsulate the electronics and injection molded connector receptacle. The injection molded receptacle is designed to provide support and alignment for the Optical Sub-Assemblies (OSAs) prior to overmolding. With the electronics on its substrate (Leadframe/HIC), the optics on the receptacle, and the link between the optics and the electronics complete (wirebonded), the substrate and the receptacle are overmolded in one step. This technique eliminates the need for the first mold process inherent in the two stage overmolding technique. The one step method also removes the need for precision mold features required for optical port alignment and subsequent final assembly (necessary in the two step method). This method, however, combines five active components into one integrated unit-requiring the use of "Known Good Die" to ensure a trouble free device.
{"title":"Advanced molding technique for optical transceivers","authors":"S. Robinson, F. Anigbo, G. Shevchuk","doi":"10.1109/ECTC.1996.550876","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550876","url":null,"abstract":"With the growing use of fiber optics in Local Area Networks (LANs), efforts to cost reduce the optical components has intensified. In general, optoelectronic components for Fiber Distributed Data Interface (FDDI) and Fiber Channel LANs have been LED-based Optical Data Links (ODLs). Due to the bi-directional nature of most links, the trend has been towards the integration of simplex optical transmitters and receivers into Optical Transceivers. Further cost reductions through the use of automated assembly processes such as two step overmolding have also been reported recently. In this paper, we propose a molding technique designed to further cost reduce optoelectronic devices. The technique involves the use of a one-step overmolding process to encapsulate the electronics and injection molded connector receptacle. The injection molded receptacle is designed to provide support and alignment for the Optical Sub-Assemblies (OSAs) prior to overmolding. With the electronics on its substrate (Leadframe/HIC), the optics on the receptacle, and the link between the optics and the electronics complete (wirebonded), the substrate and the receptacle are overmolded in one step. This technique eliminates the need for the first mold process inherent in the two stage overmolding technique. The one step method also removes the need for precision mold features required for optical port alignment and subsequent final assembly (necessary in the two step method). This method, however, combines five active components into one integrated unit-requiring the use of \"Known Good Die\" to ensure a trouble free device.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134143206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517431
R. Schluter, K.J. Pearsall, R. W. Burns
Over the past few years card connectors have progressed significantly from the 0.100" pitch gold tabs of the first PC's. New developments in card technology are driving higher connector pin count and denser, more unique connector packaging. Since more and more circuits must go from card to card, the card edge connectors have migrated to surface mount and are now straddling the card in order to achieve this higher number of required interconnections. A straddle mount connector system is evaluated in an electronic card assembly test facility for both material and process impacts. Emphasis is placed on the connector and associated process materials used. The contact integrity after successful solder attach has been evaluated. While in-depth details of the attach and subsequent repair process have been reported previously, the critical process parameters will be highlighted in this paper.
{"title":"A straddle mount connector system attach process","authors":"R. Schluter, K.J. Pearsall, R. W. Burns","doi":"10.1109/ECTC.1996.517431","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517431","url":null,"abstract":"Over the past few years card connectors have progressed significantly from the 0.100\" pitch gold tabs of the first PC's. New developments in card technology are driving higher connector pin count and denser, more unique connector packaging. Since more and more circuits must go from card to card, the card edge connectors have migrated to surface mount and are now straddling the card in order to achieve this higher number of required interconnections. A straddle mount connector system is evaluated in an electronic card assembly test facility for both material and process impacts. Emphasis is placed on the connector and associated process materials used. The contact integrity after successful solder attach has been evaluated. While in-depth details of the attach and subsequent repair process have been reported previously, the critical process parameters will be highlighted in this paper.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133284700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517374
Ji-Chen Yang, L. Weng, Goh Jing Sua, Yew Chee Kiang
This paper reports the investigation into Lead-On-Chip (LOG) package cracking resistance, the effects of mold compound properties, and the package cracking predication. The vehicle for such investigation was a DRAM LOC package and four mold compounds under two IR reflow processes (220/spl deg/C and 260/spl deg/C). As the reliability of the LOC package is strongly dependent on the mechanical properties of the mold compound, great efforts were put into its characterizations. The mold compound characterization was conducted using an Instron Universal Tester with a temperature chamber which regulated the testing temperature from -60 to 260/spl deg/C. These characterizations included temperature dependence, loading speed effects, moisture effects, creep behaviour, etc. The linear elastic fracture mechanics method was used to predict package cracking resistance. This included obtaining mold compound fracture toughness through 3-point bending test at the IR reflow temperatures, finite element analysis to obtain package stress intensity factors at these conditions, and correlate with the package reliability test results.
{"title":"Effects of mold compound properties on lead-on-chip (LOC) package reliability during IR reflow","authors":"Ji-Chen Yang, L. Weng, Goh Jing Sua, Yew Chee Kiang","doi":"10.1109/ECTC.1996.517374","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517374","url":null,"abstract":"This paper reports the investigation into Lead-On-Chip (LOG) package cracking resistance, the effects of mold compound properties, and the package cracking predication. The vehicle for such investigation was a DRAM LOC package and four mold compounds under two IR reflow processes (220/spl deg/C and 260/spl deg/C). As the reliability of the LOC package is strongly dependent on the mechanical properties of the mold compound, great efforts were put into its characterizations. The mold compound characterization was conducted using an Instron Universal Tester with a temperature chamber which regulated the testing temperature from -60 to 260/spl deg/C. These characterizations included temperature dependence, loading speed effects, moisture effects, creep behaviour, etc. The linear elastic fracture mechanics method was used to predict package cracking resistance. This included obtaining mold compound fracture toughness through 3-point bending test at the IR reflow temperatures, finite element analysis to obtain package stress intensity factors at these conditions, and correlate with the package reliability test results.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517465
S. Matsuda, K. Kata, H. Nakajima, E. Hagimoto
A molded fine-pitch ball grid array (FPBGA) structure, consisting of the fabricated chip, carrier tape, molded resin, and solder bumps, has many advantages over conventional structures for chip-scale packages. The assembly process of FPBGA consists of through-hole bonding, lamination, molding, solder bump formation, and outline cutting. The bonding process, which is called through-hole bonding, does not have lead bending or wire or lead crossing and allows a finer chip pad pitch to be used. However, since it is difficult to evaluate the bonding strength of each part, unlike wire bonding or TAB inner lead bonding, we developed several methods for evaluating the through-hole bonding. In the fabrication of molded FPBGA, the back side of the chip is molded by resin, which improves the robustness of the package. In this process, it is important to keep coplanarity of the package surface. We are currently testing the reliability of the molded FPBGA and results are good.
{"title":"Development of molded fine-pitch ball grid array (FPBGA) using through-hole bonding process","authors":"S. Matsuda, K. Kata, H. Nakajima, E. Hagimoto","doi":"10.1109/ECTC.1996.517465","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517465","url":null,"abstract":"A molded fine-pitch ball grid array (FPBGA) structure, consisting of the fabricated chip, carrier tape, molded resin, and solder bumps, has many advantages over conventional structures for chip-scale packages. The assembly process of FPBGA consists of through-hole bonding, lamination, molding, solder bump formation, and outline cutting. The bonding process, which is called through-hole bonding, does not have lead bending or wire or lead crossing and allows a finer chip pad pitch to be used. However, since it is difficult to evaluate the bonding strength of each part, unlike wire bonding or TAB inner lead bonding, we developed several methods for evaluating the through-hole bonding. In the fabrication of molded FPBGA, the back side of the chip is molded by resin, which improves the robustness of the package. In this process, it is important to keep coplanarity of the package surface. We are currently testing the reliability of the molded FPBGA and results are good.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"36 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517456
S. Rosser, M. K. Kerr, C. S. Chang, J. Fang, Zhaoqing Chen, Yuzhe Chen
A simplified laboratory experiment representing simultaneously switching circuits in a multi-reference plane package is described. Experimental data is compared to theoretical calculations and to simulated data from three modeling techniques of progressive complexity, including lumped element, hybrid lumped element/transmission line, and full wave solutions. The merits and limitations of each technique are presented.
{"title":"Measurement and simulation of simultaneous switching noise in the multi-reference plane package","authors":"S. Rosser, M. K. Kerr, C. S. Chang, J. Fang, Zhaoqing Chen, Yuzhe Chen","doi":"10.1109/ECTC.1996.517456","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517456","url":null,"abstract":"A simplified laboratory experiment representing simultaneously switching circuits in a multi-reference plane package is described. Experimental data is compared to theoretical calculations and to simulated data from three modeling techniques of progressive complexity, including lumped element, hybrid lumped element/transmission line, and full wave solutions. The merits and limitations of each technique are presented.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126973418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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