Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550889
A. R. Syed
A combined design of experiment and numerical analysis approach is used to determine the effect of four design parameters on the thermal fatigue life of solder joints. The four parameters considered were: substrate thickness, array configuration, ball pitch, acid pad size. A full factorial experiment was designed which was conducted numerically. A validated life prediction model was then used to determine the fatigue lives for each combination. Up to a factor of five improvement in fatigue life is predicted when these parameters were changed from one level to another.
{"title":"Thermal fatigue reliability enhancement of plastic ball grid array (PBGA) packages","authors":"A. R. Syed","doi":"10.1109/ECTC.1996.550889","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550889","url":null,"abstract":"A combined design of experiment and numerical analysis approach is used to determine the effect of four design parameters on the thermal fatigue life of solder joints. The four parameters considered were: substrate thickness, array configuration, ball pitch, acid pad size. A full factorial experiment was designed which was conducted numerically. A validated life prediction model was then used to determine the fatigue lives for each combination. Up to a factor of five improvement in fatigue life is predicted when these parameters were changed from one level to another.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550754
T. Zhou, M. Hundt
The objective of this work is to understand the effect of the board/system environment on package thermal performance. It is found that for most plastic packages and in typical application environment, the majority of heat is conducted to the board. The junction to ambient thermal resistance can be obtained by the package thermal resistance and board thermal resistance. For a particular package, as the board and system environment changes, the package thermal resistance does not change, what changes is the board resistance. Thermal enhancement can be achieved in board and system level in additional to package level. The board and system act as the system heat sink. The thermal resistance of this heat sink is represented by the board to ambient thermal resistance. In this study, the sensitivity of the board thermal resistance to different parameters is examined by simulation. These parameters include: package size and placement, board construction and mounting, and the component interaction. It is suggested that by carefully designing the board and system, the optimal thermal performance can be reached.
{"title":"Board and system level effects on plastic package thermal performance","authors":"T. Zhou, M. Hundt","doi":"10.1109/ECTC.1996.550754","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550754","url":null,"abstract":"The objective of this work is to understand the effect of the board/system environment on package thermal performance. It is found that for most plastic packages and in typical application environment, the majority of heat is conducted to the board. The junction to ambient thermal resistance can be obtained by the package thermal resistance and board thermal resistance. For a particular package, as the board and system environment changes, the package thermal resistance does not change, what changes is the board resistance. Thermal enhancement can be achieved in board and system level in additional to package level. The board and system act as the system heat sink. The thermal resistance of this heat sink is represented by the board to ambient thermal resistance. In this study, the sensitivity of the board thermal resistance to different parameters is examined by simulation. These parameters include: package size and placement, board construction and mounting, and the component interaction. It is suggested that by carefully designing the board and system, the optimal thermal performance can be reached.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124107702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550500
N. Bhandarkar, L. Beng
This paper describes a method of leadframe design which reduces thermal deformation and stress in the chip, and improves moldability of leadframe-based plastic encapsulated IC packages. The design works by splitting the die-pad into several sections joined together by flexible expansion joints. The split die-pad allows relative motion between the sections of the pad and breaks down the total die-pad length that is rigidly attached to the chip into smaller segments. These two factors reduce the magnitude of coefficient-of-thermal-expansion (CTE) mismatch and out-of-plane deformation of the assembly, resulting in reduced chip stress and improved moldability.
{"title":"Low-stress leadframe design for plastic IC packages","authors":"N. Bhandarkar, L. Beng","doi":"10.1109/ECTC.1996.550500","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550500","url":null,"abstract":"This paper describes a method of leadframe design which reduces thermal deformation and stress in the chip, and improves moldability of leadframe-based plastic encapsulated IC packages. The design works by splitting the die-pad into several sections joined together by flexible expansion joints. The split die-pad allows relative motion between the sections of the pad and breaks down the total die-pad length that is rigidly attached to the chip into smaller segments. These two factors reduce the magnitude of coefficient-of-thermal-expansion (CTE) mismatch and out-of-plane deformation of the assembly, resulting in reduced chip stress and improved moldability.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126291933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550896
Y. Hotta, H. Sigyo, S. Kondo, S. Oizumi
This paper describes the Foil covered PACkage (FPAC) technology developed by Nitto Denko. This concept involves using a thin metal foil on the package. Consequently the package can show very high solder resistance. An improvement of the laser marking, a reduction in the warpage of the package are some of the other advantages of this technology. The concept can also be adapted to provide an EMI shield.
{"title":"Foil covered PACkage (FPAC): a new package concept","authors":"Y. Hotta, H. Sigyo, S. Kondo, S. Oizumi","doi":"10.1109/ECTC.1996.550896","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550896","url":null,"abstract":"This paper describes the Foil covered PACkage (FPAC) technology developed by Nitto Denko. This concept involves using a thin metal foil on the package. Consequently the package can show very high solder resistance. An improvement of the laser marking, a reduction in the warpage of the package are some of the other advantages of this technology. The concept can also be adapted to provide an EMI shield.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550885
P. Vianco, J. Rejent, I. Artaki, U. Ray, D. Finley, A. Jackson
Enhanced performance goals and environmental restrictions have heightened the consideration for use of alternative solders as replacements for the traditional tin-lead (Sn-Pb) eutectic and near-eutectic alloys. However, the implementation of non-Pb bearing surface finishes may lag behind solder alloy development. A study was performed which examined the effect(s) of Pb contamination on the performance of Sn-Ag-Bi and Sn-Ag-Cu-Sb lead-free solders by the controlled addition of 63Sn-37Pb solder at levels of 0.5-8.0 Wt.%. Thermal analysis and ring-in-plug shear strength studies were conducted on bulk solder properties. Circuit board prototype studies centered on the performance of 20I/O SOIC gull wing joints. Both alloys exhibited declines in their melting temperatures with greater Sn-Pb additions. The ringing-plug shear strength of the Sn-Ag-Cu-Sb solder increased slightly with Sn-Pb levels while the Sn-Ag-Bi alloy experienced a strength loss. The mechanical behavior of the SOIC Sn-Ag-Bi solder joints reproduced the strength drop to Sn-Pb contamination; however, the strength levels were insensitive to 10,106 thermal cycles. The Sn-Ag-Cu-Sb solder showed a slight decrease in the gull wing joint strengths that was sensitive to the Pb content of the surface finish.
{"title":"Compatibility of lead-free solders with lead containing surface finishes as a reliability issue in electronic assemblies","authors":"P. Vianco, J. Rejent, I. Artaki, U. Ray, D. Finley, A. Jackson","doi":"10.1109/ECTC.1996.550885","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550885","url":null,"abstract":"Enhanced performance goals and environmental restrictions have heightened the consideration for use of alternative solders as replacements for the traditional tin-lead (Sn-Pb) eutectic and near-eutectic alloys. However, the implementation of non-Pb bearing surface finishes may lag behind solder alloy development. A study was performed which examined the effect(s) of Pb contamination on the performance of Sn-Ag-Bi and Sn-Ag-Cu-Sb lead-free solders by the controlled addition of 63Sn-37Pb solder at levels of 0.5-8.0 Wt.%. Thermal analysis and ring-in-plug shear strength studies were conducted on bulk solder properties. Circuit board prototype studies centered on the performance of 20I/O SOIC gull wing joints. Both alloys exhibited declines in their melting temperatures with greater Sn-Pb additions. The ringing-plug shear strength of the Sn-Ag-Cu-Sb solder increased slightly with Sn-Pb levels while the Sn-Ag-Bi alloy experienced a strength loss. The mechanical behavior of the SOIC Sn-Ag-Bi solder joints reproduced the strength drop to Sn-Pb contamination; however, the strength levels were insensitive to 10,106 thermal cycles. The Sn-Ag-Cu-Sb solder showed a slight decrease in the gull wing joint strengths that was sensitive to the Pb content of the surface finish.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121286026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550883
C.L. Hernadez, F. Hosking
A new solderability test method has been developed at Sandia National Laboratories that simulates the capillary flow physics of solders' on circuit board surfaces. The solderability test geometry was incorporated on a circuit board prototype that was developed for a National Center for Manufacturing Sciences (NCMS) program. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, NCMS, and several PWB fabricators (AT&T, IBM, Texas Instruments, United Technologies/Hamilton Standard and Hughes Aircraft) to advance PWB interconnect technology. The test was used to investigate the effects of environmental prestressing on the solderability of printed wiring board (PWB) copper finishes. Aging was performed in a controlled chamber representing a typical indoor industrial environment. Solderability testing on as-fabricated and exposed copper samples was performed with the Sn-Pb eutectic solder at four different reflow temperatures (215, 230, 245 and 260/spl deg/C). Rosin mildly activated (RMA), low solids (LS), and citric acid-based (CA) fluxes were included in the evaluation. Under baseline conditions, capillary flow was minimal at the lowest temperatures with all fluxes. Wetting increased with temperature at both baseline and prestressing conditions. Poor wetting, however, was observed at all temperatures with the LS flux. Capillary flow is effectively restored with the CA flux.
{"title":"PWB solder wettability after simulated storage","authors":"C.L. Hernadez, F. Hosking","doi":"10.1109/ECTC.1996.550883","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550883","url":null,"abstract":"A new solderability test method has been developed at Sandia National Laboratories that simulates the capillary flow physics of solders' on circuit board surfaces. The solderability test geometry was incorporated on a circuit board prototype that was developed for a National Center for Manufacturing Sciences (NCMS) program. The work was conducted under a cooperative research and development agreement between Sandia National Laboratories, NCMS, and several PWB fabricators (AT&T, IBM, Texas Instruments, United Technologies/Hamilton Standard and Hughes Aircraft) to advance PWB interconnect technology. The test was used to investigate the effects of environmental prestressing on the solderability of printed wiring board (PWB) copper finishes. Aging was performed in a controlled chamber representing a typical indoor industrial environment. Solderability testing on as-fabricated and exposed copper samples was performed with the Sn-Pb eutectic solder at four different reflow temperatures (215, 230, 245 and 260/spl deg/C). Rosin mildly activated (RMA), low solids (LS), and citric acid-based (CA) fluxes were included in the evaluation. Under baseline conditions, capillary flow was minimal at the lowest temperatures with all fluxes. Wetting increased with temperature at both baseline and prestressing conditions. Poor wetting, however, was observed at all temperatures with the LS flux. Capillary flow is effectively restored with the CA flux.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550881
D. Baldwin, R. Deshmukh, C. S. Hau
For miniature interconnection applications, innovative material systems based on gallium alloys offer potentially attractive alternatives over commonly used bonding materials, such as solders and conductive adhesives, without the reliability and environmental drawbacks. Gallium alloys are mechanically alloyed mixtures of a liquid metal and metallic powders, formed at room temperature which cure to form solid intermetallic interconnects. Through the course of this work, gallium alloys have been investigated for flip-chip interconnect applications. Specifically, this paper presents the results of a preliminary feasibility study demonstrating the applicability of gallium alloys as flip-chip on laminate interconnect materials. The topics covered include the test vehicle assembly process, reliability screening results, preliminary failure mode analysis, and interconnect microstructure analysis. To demonstrate preliminary feasibility and application, gallium alloyed with copper and nickel was used as micro-miniature interconnects between bare silicon chips and printed circuit boards. This initial study shows feasibility of such interconnects and the reliability tests demonstrate sufficient cyclic fatigue reliability in the presence of underfill material. Moreover, through the course of this work a new micro-dispensing technology for gallium alloys was developed which leverages existing industry infrastructure. This initial study represents a significant advancement in microelectronic interconnect materials unveiling the potential for an innovative lead-free interconnect alternative.
{"title":"Gallium alloy interconnects for flip-chip assembly applications","authors":"D. Baldwin, R. Deshmukh, C. S. Hau","doi":"10.1109/ECTC.1996.550881","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550881","url":null,"abstract":"For miniature interconnection applications, innovative material systems based on gallium alloys offer potentially attractive alternatives over commonly used bonding materials, such as solders and conductive adhesives, without the reliability and environmental drawbacks. Gallium alloys are mechanically alloyed mixtures of a liquid metal and metallic powders, formed at room temperature which cure to form solid intermetallic interconnects. Through the course of this work, gallium alloys have been investigated for flip-chip interconnect applications. Specifically, this paper presents the results of a preliminary feasibility study demonstrating the applicability of gallium alloys as flip-chip on laminate interconnect materials. The topics covered include the test vehicle assembly process, reliability screening results, preliminary failure mode analysis, and interconnect microstructure analysis. To demonstrate preliminary feasibility and application, gallium alloyed with copper and nickel was used as micro-miniature interconnects between bare silicon chips and printed circuit boards. This initial study shows feasibility of such interconnects and the reliability tests demonstrate sufficient cyclic fatigue reliability in the presence of underfill material. Moreover, through the course of this work a new micro-dispensing technology for gallium alloys was developed which leverages existing industry infrastructure. This initial study represents a significant advancement in microelectronic interconnect materials unveiling the potential for an innovative lead-free interconnect alternative.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517464
John A. Abbott, G. Hamilton, N. Kalidas, M. Murtuza, C. Thornton, S. Thomas, Y. Umeda, D. Malladi, D. Towne, S. Chao
This paper describes the development of a 520 terminal Plastic Ball Grid Array (PBGA) package to meet the system level requirements of the UltraSPARC-I/sup TM/ microprocessor. The Printed Circuit Board (PCB) substrate PBGA package developed was designed to handle chip operation above 200 MHz and dissipate 36 watts of power with the assistance of an integral heat sink and airflow. Mechanical stresses, board level reliability, thermal and electrical requirements are outlined. The package enhancements and process refinements executed to meet the design goals and reliability requirements are presented.
{"title":"Design and development of a high performance PBGA package for the UltraSPARC-I/sup TM/ processor","authors":"John A. Abbott, G. Hamilton, N. Kalidas, M. Murtuza, C. Thornton, S. Thomas, Y. Umeda, D. Malladi, D. Towne, S. Chao","doi":"10.1109/ECTC.1996.517464","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517464","url":null,"abstract":"This paper describes the development of a 520 terminal Plastic Ball Grid Array (PBGA) package to meet the system level requirements of the UltraSPARC-I/sup TM/ microprocessor. The Printed Circuit Board (PCB) substrate PBGA package developed was designed to handle chip operation above 200 MHz and dissipate 36 watts of power with the assistance of an integral heat sink and airflow. Mechanical stresses, board level reliability, thermal and electrical requirements are outlined. The package enhancements and process refinements executed to meet the design goals and reliability requirements are presented.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115465603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.517415
D. Scheider, D. Hopkins, P. Zucco, Edward Moszczynski, M. Griffin, M. Takács, J. Galvagni
Multilayer ceramic (MLC) capacitors are composite structures made of alternating layers of ceramic (dielectric material) and metal (electrodes). The dielectric material is barium titanate-based ceramic and the electrodes are made of platinum. C4 (controlled collapse chip connections) technology is used to provide multiple attachment points to substrates. A high dielectric constant of barium titanate-based ceramic helps to achieve a large capacitance/size ratio. The capacitance ranges from 32 nF to 100 nF in body sizes up to 1.85/spl times/1.6/spl times/0.85 mm. In this paper, we cover design, reliability and electrical characterization of capacitors with C4 interconnections. Reliability stress tests performed during qualification were designed to cover a wide range of field applications and included stress tests such as liquid to liquid thermal shock, moisture resistance and thermal cycles per Mil.Std., high temperature bias, temperature humidity bias and tensile pull. A visual inspection of parts post stress and physical analysis of unstressed parts were also performed. The parameters monitored during stress testing were: capacitance, leakage current and plate resistance. The electrical characterization measurements included effects of frequency, temperature and voltage. Inductance measurements were included based on a self-resonance technique.
{"title":"Reliability and characterization of MLC decoupling capacitors with C4 interconnections","authors":"D. Scheider, D. Hopkins, P. Zucco, Edward Moszczynski, M. Griffin, M. Takács, J. Galvagni","doi":"10.1109/ECTC.1996.517415","DOIUrl":"https://doi.org/10.1109/ECTC.1996.517415","url":null,"abstract":"Multilayer ceramic (MLC) capacitors are composite structures made of alternating layers of ceramic (dielectric material) and metal (electrodes). The dielectric material is barium titanate-based ceramic and the electrodes are made of platinum. C4 (controlled collapse chip connections) technology is used to provide multiple attachment points to substrates. A high dielectric constant of barium titanate-based ceramic helps to achieve a large capacitance/size ratio. The capacitance ranges from 32 nF to 100 nF in body sizes up to 1.85/spl times/1.6/spl times/0.85 mm. In this paper, we cover design, reliability and electrical characterization of capacitors with C4 interconnections. Reliability stress tests performed during qualification were designed to cover a wide range of field applications and included stress tests such as liquid to liquid thermal shock, moisture resistance and thermal cycles per Mil.Std., high temperature bias, temperature humidity bias and tensile pull. A visual inspection of parts post stress and physical analysis of unstressed parts were also performed. The parameters monitored during stress testing were: capacitance, leakage current and plate resistance. The electrical characterization measurements included effects of frequency, temperature and voltage. Inductance measurements were included based on a self-resonance technique.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-28DOI: 10.1109/ECTC.1996.550814
D.L. Smith, A.S. Alimonda
We have used sputter-deposition and standard lithography to fabricate arrays of cantilevered metal micro-springs on 80 /spl mu/m pitch, and we have obtained 100% electrical contact to 200-pad chips bonded face-down against them. Four-point resistance is 0.38 /spl Omega/ for Mo-Cr springs on Al pads. Since the contacts themselves are not bonded and since the springs have high elastic compliance, this technology is very resistant to mechanical shock and stress, can accommodate large nonplanarity in mating surfaces, facilitates replacement of bad chips, and could be used for wafer-scale probing.
{"title":"A new flip-chip technology for high-density packaging","authors":"D.L. Smith, A.S. Alimonda","doi":"10.1109/ECTC.1996.550814","DOIUrl":"https://doi.org/10.1109/ECTC.1996.550814","url":null,"abstract":"We have used sputter-deposition and standard lithography to fabricate arrays of cantilevered metal micro-springs on 80 /spl mu/m pitch, and we have obtained 100% electrical contact to 200-pad chips bonded face-down against them. Four-point resistance is 0.38 /spl Omega/ for Mo-Cr springs on Al pads. Since the contacts themselves are not bonded and since the springs have high elastic compliance, this technology is very resistant to mechanical shock and stress, can accommodate large nonplanarity in mating surfaces, facilitates replacement of bad chips, and could be used for wafer-scale probing.","PeriodicalId":143519,"journal":{"name":"1996 Proceedings 46th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116010967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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