Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000515
E. Kidd, B. Campbell, R. Dillingham
Validating surface chemical composition and properties of die pad surfaces is crucial for achieving joint reliability in microelectronic wire bonding operations. Die pad surfaces undergo a number of surface sensitive manufacturing steps prior to bonding that will affect joint performance; contact and environmental contaminants from process aids, shipping, handling, storage and out time are all key players in surface degradation. Microelectronics manufacturers may implement cleaning and/or surface activation operations to remediate surfaces from upstream contaminants, however, understanding and quantifying the effect of such processes requires the ability to manipulate and monitor the top few molecular layers of a material responsible for adhesion—the surface. This presentation will investigate surface chemistries of atmospheric plasma cleaned and non-cleaned die pad surfaces as determined by X-ray photoelectron spectroscopy (XPS) and surface energy measurements via contact angle techniques.
{"title":"Controlling Surface Sensitive Processes in Microelectronics Manufacturing to Improve Wire Bonded Joint Reliability","authors":"E. Kidd, B. Campbell, R. Dillingham","doi":"10.4071/2380-4505-2019.1.000515","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000515","url":null,"abstract":"\u0000 Validating surface chemical composition and properties of die pad surfaces is crucial for achieving joint reliability in microelectronic wire bonding operations. Die pad surfaces undergo a number of surface sensitive manufacturing steps prior to bonding that will affect joint performance; contact and environmental contaminants from process aids, shipping, handling, storage and out time are all key players in surface degradation. Microelectronics manufacturers may implement cleaning and/or surface activation operations to remediate surfaces from upstream contaminants, however, understanding and quantifying the effect of such processes requires the ability to manipulate and monitor the top few molecular layers of a material responsible for adhesion—the surface.\u0000 This presentation will investigate surface chemistries of atmospheric plasma cleaned and non-cleaned die pad surfaces as determined by X-ray photoelectron spectroscopy (XPS) and surface energy measurements via contact angle techniques.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"40 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85740224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000591
Dewei Xu, Zhiguo Sun, Haojun Zhang, S. Pozder, P. Justison, Seungho Kook, R. Augur, R. Fox
Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to porous carbon-doped oxides (p-SiCOH) have been implemented. However, due to the process integration challenges with inherently weak low-k materials, the trend to pursue lower k dielectrics has come to a plateau as technology nodes scale down past 20/14nm. On the other hand, the trend of geometry layer thickness shrinking down, such as trench CD and height, via CD and height, etc., still continues for each advanced technology node. In the BEOL stack adhesion layers (oxide + gradient layers) (ALs) with higher k value were introduced to enhance interface adhesion strength between SiCOH/p-SiCOH and dielectric cap film (SiCN), which offset the intrinsic RC benefit from low-k dielectric material. At more advanced nodes and beyond, the combined ALs and cap film could be up to via or trench height, which poses a huge challenge to meet desired RC performance and technology node scaling. Therefore, the thickness reduction of ALs and cap film becomes necessary for further technology node scaling. In this study, samples with interfacial full ALs, reduced ALs and bulk only (no ALs) for p-SiCOH (k=2.75) on various cap films were prepared, such as SiCN, SiCN/ODC, SiCN/AlONx, etc. TOF-SIMS analyses was used to confirm the composition of the dielectric stacks and later check the debonded surface morphology. Four-point bend adhesion tests were conducted to evaluate interfacial adhesion strength. Results show the interfacial adhesion strength on samples with reduced Als and bulk only (no ALs) is dropped by ~20% and ~30%, respectively. Additional ODC layer on top of SiCN would increase the interfacial adhesion strength by ~10%. It is suggested that reduced ALs may be adequate to satisfy overall CPI requirement for the BEOL integration scheme of p-SiCOH on advanced dielectric cap films (AlN + ODC). The coupling capacitance reduction for a combined reduced ALs and advanced dielectric cap can be up to 16% at M0 level and 10% at Mx level for a 40nm metal pitch.
{"title":"A Study on Reduced/Absent Adhesion/Cap Layers for Optimized BEOL RC Performance","authors":"Dewei Xu, Zhiguo Sun, Haojun Zhang, S. Pozder, P. Justison, Seungho Kook, R. Augur, R. Fox","doi":"10.4071/2380-4505-2019.1.000591","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000591","url":null,"abstract":"\u0000 Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to porous carbon-doped oxides (p-SiCOH) have been implemented. However, due to the process integration challenges with inherently weak low-k materials, the trend to pursue lower k dielectrics has come to a plateau as technology nodes scale down past 20/14nm. On the other hand, the trend of geometry layer thickness shrinking down, such as trench CD and height, via CD and height, etc., still continues for each advanced technology node. In the BEOL stack adhesion layers (oxide + gradient layers) (ALs) with higher k value were introduced to enhance interface adhesion strength between SiCOH/p-SiCOH and dielectric cap film (SiCN), which offset the intrinsic RC benefit from low-k dielectric material. At more advanced nodes and beyond, the combined ALs and cap film could be up to via or trench height, which poses a huge challenge to meet desired RC performance and technology node scaling. Therefore, the thickness reduction of ALs and cap film becomes necessary for further technology node scaling.\u0000 In this study, samples with interfacial full ALs, reduced ALs and bulk only (no ALs) for p-SiCOH (k=2.75) on various cap films were prepared, such as SiCN, SiCN/ODC, SiCN/AlONx, etc. TOF-SIMS analyses was used to confirm the composition of the dielectric stacks and later check the debonded surface morphology. Four-point bend adhesion tests were conducted to evaluate interfacial adhesion strength. Results show the interfacial adhesion strength on samples with reduced Als and bulk only (no ALs) is dropped by ~20% and ~30%, respectively. Additional ODC layer on top of SiCN would increase the interfacial adhesion strength by ~10%. It is suggested that reduced ALs may be adequate to satisfy overall CPI requirement for the BEOL integration scheme of p-SiCOH on advanced dielectric cap films (AlN + ODC). The coupling capacitance reduction for a combined reduced ALs and advanced dielectric cap can be up to 16% at M0 level and 10% at Mx level for a 40nm metal pitch.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"88 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89354079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000176
Fu Lei, S BhagavatMilind, C. Selvanayagam, Ken Leong, Barber Ivor
Power, performance, and area gains are important metrics driving the CMOS technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of I/Os, and the scaling driven small IP block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14nm/16nm nodes which used 150um bump pitch coming out of a die, for 7nm node the industry is targeting 130um bump pitch for high performance devices. With this pitch reduction, conventional SnAg solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in High Performance Computing, the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of ELK cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where CTE mismatch between silicon and laminate substrate magnifies the stress. The present paper discusses successful development of Cu pillar bumps for 7nm technology. The development program included a 2-step development path. In the first step, extensive thermo-mechanical modeling was done to find optimal design of copper pillar bump for robustness of interactions with 7nm BEOL ELK layers. In the second step, a 460 mm2 7nm Silicon test Vehicle was fabricated and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7nm silicon. As a result of this development, copper pillar technology has been qualified on AMD products. Today, copper pillar is a fully integral part of AMD's ever-growing 7nm product offering in High Performance Computing.
{"title":"Cu pillar bump development for 7nm Chip package interaction (CPI) technology","authors":"Fu Lei, S BhagavatMilind, C. Selvanayagam, Ken Leong, Barber Ivor","doi":"10.4071/2380-4505-2019.1.000176","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000176","url":null,"abstract":"\u0000 Power, performance, and area gains are important metrics driving the CMOS technology from older nodes to newer ones. Over past several decades, a steady downscaling of feature sizes of CMOS technology has been a leading force enabling continual improvement in circuit speeds and cost per functionality. Increase in functionality drives larger number of I/Os, and the scaling driven small IP block sizes force these larger number of I/Os to be accommodated by reduction of I/O pitches. The result is an unrelenting pressure to reduce bump pitches from one generation of CMOS to another. In contrast to 14nm/16nm nodes which used 150um bump pitch coming out of a die, for 7nm node the industry is targeting 130um bump pitch for high performance devices. With this pitch reduction, conventional SnAg solder bumps face limitations in terms of bridging. Cu pillar bumps are the best candidate for smaller bump pitches. However, for large die sizes prevalent in High Performance Computing, the Cu pillar bumps will induce higher stress on the silicon resulting in higher risks of ELK cracking. If copper pillar bumps are not properly developed, then there is a risk of marginal reliability in terms of chip package interaction. The situation becomes even more dire in large die sizes, where CTE mismatch between silicon and laminate substrate magnifies the stress.\u0000 The present paper discusses successful development of Cu pillar bumps for 7nm technology. The development program included a 2-step development path. In the first step, extensive thermo-mechanical modeling was done to find optimal design of copper pillar bump for robustness of interactions with 7nm BEOL ELK layers. In the second step, a 460 mm2 7nm Silicon test Vehicle was fabricated and its assembly process was optimized to characterize the copper pillar bumps and prove their extended reliability on 7nm silicon. As a result of this development, copper pillar technology has been qualified on AMD products. Today, copper pillar is a fully integral part of AMD's ever-growing 7nm product offering in High Performance Computing.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"9 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87570933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000509
Reinhard Schemmel, Florian Eacock, Collin Dymel, T. Hemsel, M. Hunstig, M. Brökelmann, W. Sextro
Ultrasonic joining is a common industrial process. To build electrical connections in the electronics industry, uni-axial and torsional ultrasonic vibration have been used to join different types of workpieces for decades. Many influencing factors like ultrasonic power, bond normal force, bond duration and frequency are known to have a high impact on bond quality and reliability. Multi-dimensional bonding has been investigated in the past to increase ultrasonic power and consequently bond strength. This contribution is focused on the comparison of circular, multi-frequency planar and uniaxial vibration trajectories used for ultrasonic bonding of copper pins on copper substrate. Bond quality was analyzed by shear tests, scanning acoustic microscopy and interface cross-sections.
{"title":"Impact of multi-dimensional vibration trajectories on quality and failure modes in ultrasonic bonding","authors":"Reinhard Schemmel, Florian Eacock, Collin Dymel, T. Hemsel, M. Hunstig, M. Brökelmann, W. Sextro","doi":"10.4071/2380-4505-2019.1.000509","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000509","url":null,"abstract":"\u0000 Ultrasonic joining is a common industrial process. To build electrical connections in the electronics industry, uni-axial and torsional ultrasonic vibration have been used to join different types of workpieces for decades. Many influencing factors like ultrasonic power, bond normal force, bond duration and frequency are known to have a high impact on bond quality and reliability. Multi-dimensional bonding has been investigated in the past to increase ultrasonic power and consequently bond strength. This contribution is focused on the comparison of circular, multi-frequency planar and uniaxial vibration trajectories used for ultrasonic bonding of copper pins on copper substrate. Bond quality was analyzed by shear tests, scanning acoustic microscopy and interface cross-sections.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"47 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88409603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000202
N. Ogura, Siddharth Ravichandran, Tailong Shi, A. Watanabe, Shuhei Yamada, M. Kathaperumal, R. Tummala
With the number of connected-devices increasing tremendously, communication data rates are projected to be at least 10–100X in the 5G/mm-wave (MMW) technology - much higher than the existing 4G LTE connections.[1], [2] To catch up with the trend, novel packaging technology in the MMW frequency range is required, which will address fundamental MMW technical challenges such as high dielectric loss, degradation of quality factors in passives, increased parasitic, dramatically-enhanced electromagnetic interference, and the reduced radiation efficiency of antenna arrays. State-of-the-art approaches being pursued include organic-core substrates that have a low dielectric constant (Dk) and low dissipation factor (Df) such as fluorine based or liquid-crystal polymer (LCP) substrates in order to achieve enhanced antenna performance and low signal dissipations. These organic-based substrate technologies, however, can neither miniaturize packages nor handle precision signal routings that enable high density packages. To address these challenges, attention is focused on Fan-Out Wafer Level Package (FOWLP) technologies, like eWLB, InFO, and SWIFT, where integrated circuits (ICs) are embedded in epoxy molding compound. [3]–[6] Recently, glass-panel embedding (GPE) technology is emerging as an ideal packaging methodology that enables superior performance along with small form factor, ultra-low-loss, high density, ultra-short interconnects, and low cost. [7] These benefits stem from the advantages of using glass which has excellent properties such as ultra-smooth surface for precision redistribution layer (RDL), exceptional dimensional stability for panel-scalability and tailorability of CTE that allow direct board-attach for improved system performance. In addition, utilizing the epoxy molding compounds as encapsulation material allows the GPE package to be thinner and more robust package with small farm factor. Molding of glass cavity panels also helps with the handling of ultra-thin glass which is seen as a bottleneck towards glass based packaging solutions in production. These facilitates enhanced throughput by allowing more cavity cut outs (more coupons) per panel. This paper presents the first demonstration of ultra-thin GPE with sheet type epoxy molding compound (SMC) for 5G/mm-wave applications. First part of this paper discusses the process-flow used in glass-panel embedding with laminated SMC, including chip placement in glass cavities, lamination of SMC, and the reliability of the package architecture. This paper reports on such a demonstration in 60 μm glass substrates with 40 μm thickness SMC. The second part of this paper focuses on low-loss interconnects for 5G/mm-wave applications and presents the process development of signal routings such as transmission lines and microvias in RDLs as well as through-package vias (TPVs) with via-in-via process. The results suggest that the ultra-thin GPE architecture is a promising packaging technology sol
{"title":"First Demonstration of Ultra-Thin Glass Panel Embedded (GPE) Package with Sheet Type Epoxy Molding Compound for 5G/mm-wave Applications","authors":"N. Ogura, Siddharth Ravichandran, Tailong Shi, A. Watanabe, Shuhei Yamada, M. Kathaperumal, R. Tummala","doi":"10.4071/2380-4505-2019.1.000202","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000202","url":null,"abstract":"\u0000 With the number of connected-devices increasing tremendously, communication data rates are projected to be at least 10–100X in the 5G/mm-wave (MMW) technology - much higher than the existing 4G LTE connections.[1], [2] To catch up with the trend, novel packaging technology in the MMW frequency range is required, which will address fundamental MMW technical challenges such as high dielectric loss, degradation of quality factors in passives, increased parasitic, dramatically-enhanced electromagnetic interference, and the reduced radiation efficiency of antenna arrays.\u0000 State-of-the-art approaches being pursued include organic-core substrates that have a low dielectric constant (Dk) and low dissipation factor (Df) such as fluorine based or liquid-crystal polymer (LCP) substrates in order to achieve enhanced antenna performance and low signal dissipations. These organic-based substrate technologies, however, can neither miniaturize packages nor handle precision signal routings that enable high density packages. To address these challenges, attention is focused on Fan-Out Wafer Level Package (FOWLP) technologies, like eWLB, InFO, and SWIFT, where integrated circuits (ICs) are embedded in epoxy molding compound. [3]–[6]\u0000 Recently, glass-panel embedding (GPE) technology is emerging as an ideal packaging methodology that enables superior performance along with small form factor, ultra-low-loss, high density, ultra-short interconnects, and low cost. [7] These benefits stem from the advantages of using glass which has excellent properties such as ultra-smooth surface for precision redistribution layer (RDL), exceptional dimensional stability for panel-scalability and tailorability of CTE that allow direct board-attach for improved system performance. In addition, utilizing the epoxy molding compounds as encapsulation material allows the GPE package to be thinner and more robust package with small farm factor. Molding of glass cavity panels also helps with the handling of ultra-thin glass which is seen as a bottleneck towards glass based packaging solutions in production. These facilitates enhanced throughput by allowing more cavity cut outs (more coupons) per panel.\u0000 This paper presents the first demonstration of ultra-thin GPE with sheet type epoxy molding compound (SMC) for 5G/mm-wave applications. First part of this paper discusses the process-flow used in glass-panel embedding with laminated SMC, including chip placement in glass cavities, lamination of SMC, and the reliability of the package architecture. This paper reports on such a demonstration in 60 μm glass substrates with 40 μm thickness SMC. The second part of this paper focuses on low-loss interconnects for 5G/mm-wave applications and presents the process development of signal routings such as transmission lines and microvias in RDLs as well as through-package vias (TPVs) with via-in-via process. The results suggest that the ultra-thin GPE architecture is a promising packaging technology sol","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"34 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88438595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000157
D. Hackler, Dale G. Wilson, E. Prack
IC packages are getting thinner to facilitate thinner electronics products. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer™ (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. This presentation shares the development, of SoP application to flexible hybrid electronics (FHE), and where SoP fits in IC packaging technologies. SoP CSP facilitates more functionality for hybrid approaches with printed electronics by allowing seamless integration of thin die into flexible/printed electronics with high reliability. Reliable thin die are an enabler for thinner conventional IC packages and potentially for thinner embedded packages (both FO and substrate based). The presentation also shows the technology roadmap for SoP application to IC packaging.
{"title":"Ultra-Thin Wafer-Level Chip Scale Packaging","authors":"D. Hackler, Dale G. Wilson, E. Prack","doi":"10.4071/2380-4505-2019.1.000157","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000157","url":null,"abstract":"\u0000 IC packages are getting thinner to facilitate thinner electronics products. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer™ (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. This presentation shares the development, of SoP application to flexible hybrid electronics (FHE), and where SoP fits in IC packaging technologies. SoP CSP facilitates more functionality for hybrid approaches with printed electronics by allowing seamless integration of thin die into flexible/printed electronics with high reliability. Reliable thin die are an enabler for thinner conventional IC packages and potentially for thinner embedded packages (both FO and substrate based). The presentation also shows the technology roadmap for SoP application to IC packaging.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"15 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87174622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000131
N. Shashidhar, A. Rao
Alumina and aluminum nitride substrates are routinely used in micro-electronic packaging where large quantity of heat needs to be dissipated, such as in LED packaging, high power electronics and laser packaging. Heat management in high power electronics or LED's is crucial for their lifespan and reliability. The ever-increasing need for higher power keeps challenging the packaging engineers to become more sophisticated in their packaging. With the availability of a 40 μm thick, high thermal conductivity ribbon alumina from Corning, the options available for packaging engineers has widened. This product has very high dielectric breakdown (~10kV at 40 μm thick), high thermal conductivity (>36 W/mK) and is rugged enough to be handled (with components attached) during packaging. These characteristics make ribbon alumina a cost-effective alternative to incumbent materials such as thick aluminum nitride, for use in high power microelectronics packaging. In this paper, high power LED and IGBT modules are modeled using commercially available code from ANSYS®. A geometry representative of typical LED packaging and IGBT packaging is constructed with Ansys Design Modeler platform and the allied meshing is done employing in-built Meshing tool in ANSYS Workbench®. We show that packaging with ~40 μm ribbon alumina delivers performance on par with or better than packaging with thicker aluminum nitride substrates.
{"title":"Low thermal resistance packaging for high power electronics","authors":"N. Shashidhar, A. Rao","doi":"10.4071/2380-4505-2019.1.000131","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000131","url":null,"abstract":"\u0000 Alumina and aluminum nitride substrates are routinely used in micro-electronic packaging where large quantity of heat needs to be dissipated, such as in LED packaging, high power electronics and laser packaging. Heat management in high power electronics or LED's is crucial for their lifespan and reliability. The ever-increasing need for higher power keeps challenging the packaging engineers to become more sophisticated in their packaging.\u0000 With the availability of a 40 μm thick, high thermal conductivity ribbon alumina from Corning, the options available for packaging engineers has widened. This product has very high dielectric breakdown (~10kV at 40 μm thick), high thermal conductivity (>36 W/mK) and is rugged enough to be handled (with components attached) during packaging. These characteristics make ribbon alumina a cost-effective alternative to incumbent materials such as thick aluminum nitride, for use in high power microelectronics packaging.\u0000 In this paper, high power LED and IGBT modules are modeled using commercially available code from ANSYS®. A geometry representative of typical LED packaging and IGBT packaging is constructed with Ansys Design Modeler platform and the allied meshing is done employing in-built Meshing tool in ANSYS Workbench®. We show that packaging with ~40 μm ribbon alumina delivers performance on par with or better than packaging with thicker aluminum nitride substrates.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89602658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000051
R. Hadizadeh, A. Laitinen, Niko Kuusniemi, V. Blaschke, D. Molinero, Eoin O'Toole, M. Pinheiro
Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics. In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.
{"title":"Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch","authors":"R. Hadizadeh, A. Laitinen, Niko Kuusniemi, V. Blaschke, D. Molinero, Eoin O'Toole, M. Pinheiro","doi":"10.4071/2380-4505-2019.1.000051","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000051","url":null,"abstract":"\u0000 Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics.\u0000 In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"20 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77908734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000393
C. Woychik, J. Lauffer, S. Pollard, Rajvi Parmar, Michael Gaige, W. E. Wilson, James Carey, Matthew Neely, Feng Ling, Lijun Chen
A process has been developed to manufacture a glass diplexer module using conventional laminate circuit board processes that have been adapted to handle glass substrates. Over the past few years we have evaluated both Cu plating and electrically conductive adhesives (ECAs) to produce a through glass via (TGV). From this work, it has been determined that Cu plating is a preferred process to form a robust TGV in a manufacturing environment. A Cu plated TGV nicely compliments our semi-additive plating (SAP) processes to produce fine line Cu circuitry on both sides of a glass substrate. In addition, we have successfully laminated an Ajinomoto Buildup Film (ABF) to both sides of a glass substrate having TGVs. The ABF completely filled the vias and also maintained uniform flatness on both sides. The resulting interposer was very flat and suitable for the next level of Cu plating using SAP. The ABF material was able to form high quality blind vias using laser drilling. A more comprehensive characterization of the glass diplexer modules will be presented, which will include X-sections of a double-sided Cu circuitry and Cu MIM (metal-insulator-metal) capacitors and inductors. In addition, the first set of electrical test data will be presented and compared with the modeling work done to date.
{"title":"Characterization and Electrical Performance of Glass Diplexer Modules","authors":"C. Woychik, J. Lauffer, S. Pollard, Rajvi Parmar, Michael Gaige, W. E. Wilson, James Carey, Matthew Neely, Feng Ling, Lijun Chen","doi":"10.4071/2380-4505-2019.1.000393","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000393","url":null,"abstract":"\u0000 A process has been developed to manufacture a glass diplexer module using conventional laminate circuit board processes that have been adapted to handle glass substrates. Over the past few years we have evaluated both Cu plating and electrically conductive adhesives (ECAs) to produce a through glass via (TGV). From this work, it has been determined that Cu plating is a preferred process to form a robust TGV in a manufacturing environment. A Cu plated TGV nicely compliments our semi-additive plating (SAP) processes to produce fine line Cu circuitry on both sides of a glass substrate. In addition, we have successfully laminated an Ajinomoto Buildup Film (ABF) to both sides of a glass substrate having TGVs. The ABF completely filled the vias and also maintained uniform flatness on both sides. The resulting interposer was very flat and suitable for the next level of Cu plating using SAP. The ABF material was able to form high quality blind vias using laser drilling. A more comprehensive characterization of the glass diplexer modules will be presented, which will include X-sections of a double-sided Cu circuitry and Cu MIM (metal-insulator-metal) capacitors and inductors. In addition, the first set of electrical test data will be presented and compared with the modeling work done to date.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"18 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78419263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000033
Saikat Mondal, Saranraj Karuppuswami, Deepak Kumar, A. Kaur, P. Chahal
A miniaturized antenna is required for a small form factor RFID tag. For harmonic RFID tag, the tag should be capable of receiving and transmitting at two different frequencies (fundamental and harmonic). Implementation of two different antennas for the operation would increase the footprint of the antenna. Hence, an optimized antenna structure is proposed, which will have a small form factor while maintaining a considerable gain. The dual band antenna would be capable of receiving at fundamental frequency and transmit information at harmonic frequency while maintaining small tag size. The dual band antenna has a miniaturized rectangular board dimension of 96.5 mm and 81 mm with resonance at 434 MHz at low frequency and 860 MHz to 1000 MHz at high frequency. The harmonic tag was designed with nonlinear transmission line and the dual band antenna. The harmonic RF tag would be useful for numerous RF applications where the single frequency tags will not be a good option such as underground object tagging, tag detection in an industrial set up with strong reflectors such a metal in the vicinity. In this paper, the design, fabrication and characterization of dual band harmonic RFID tag antenna is presented.
{"title":"A Miniaturized Dual Band Antenna for Harmonic RFID Tag","authors":"Saikat Mondal, Saranraj Karuppuswami, Deepak Kumar, A. Kaur, P. Chahal","doi":"10.4071/2380-4505-2019.1.000033","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000033","url":null,"abstract":"\u0000 A miniaturized antenna is required for a small form factor RFID tag. For harmonic RFID tag, the tag should be capable of receiving and transmitting at two different frequencies (fundamental and harmonic). Implementation of two different antennas for the operation would increase the footprint of the antenna. Hence, an optimized antenna structure is proposed, which will have a small form factor while maintaining a considerable gain. The dual band antenna would be capable of receiving at fundamental frequency and transmit information at harmonic frequency while maintaining small tag size. The dual band antenna has a miniaturized rectangular board dimension of 96.5 mm and 81 mm with resonance at 434 MHz at low frequency and 860 MHz to 1000 MHz at high frequency. The harmonic tag was designed with nonlinear transmission line and the dual band antenna. The harmonic RF tag would be useful for numerous RF applications where the single frequency tags will not be a good option such as underground object tagging, tag detection in an industrial set up with strong reflectors such a metal in the vicinity. In this paper, the design, fabrication and characterization of dual band harmonic RFID tag antenna is presented.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78460777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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