Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000067
V. Turkani, V. Akhavan, K. Schroder, Xiao Liu, Luke Prenger, Xavier Martinez
Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (<70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.
临时粘接和脱粘(TB/DB)工艺已成为晶圆级封装技术中有前途的解决方案。这些工艺为晶圆减薄和随后的背面加工提供了一条途径，这对于使用3D通硅通孔(tsv)和扇形圆片级封装等技术实现异质集成至关重要。这些对于整体设备小型化和提高性能至关重要。本文提出了一种新的光子脱键(PDB)方法和相应的键合材料。PDB通过克服与传统脱粘方法相关的许多缺点来增强TB/DB过程。PDB利用闪光灯发出的脉冲宽带光(200nm - 1100nm)将玻璃作为载体晶圆对进行脱粘。这些闪光灯在短时间间隔(~100 μs)内产生高强度光脉冲(高达45 kW/cm2)，以促进脱粘。通过成功地从玻璃载体上剥离薄化(<70 μm)硅片，证明了PDB在TB/DB工艺中的可行性。对薄晶片和载体的脱粘后清洗进行了评估。由于每个闪光灯具有均匀的大面积照明(75 mm x 150 mm)，并且能够连接灯以增加PDB工具的照明面积，PDB方法为晶圆级和面板级封装技术提供了高通量和低成本的去粘接解决方案。
{"title":"Photonic Debonding for Wafer-Level Packaging","authors":"V. Turkani, V. Akhavan, K. Schroder, Xiao Liu, Luke Prenger, Xavier Martinez","doi":"10.4071/1085-8024-2021.1.000067","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000067","url":null,"abstract":"\u0000 Temporary bonding and debonding (TB/DB) processes have emerged as promising solutions in wafer-level packaging technology. These processes offer a pathway to wafer thinning and subsequent backside processing, which are crucial in enabling heterogenous integration using technologies such as 3D through-silicon-vias (TSVs) and fan-out wafer-level packaging. These are critical for overall device miniaturization and increased performance. In this work, a novel photonic debonding (PDB) method and the corresponding bonding material are presented. PDB enhances the TB/DB process by overcoming many of the disadvantages associated with traditional debonding methods. PDB uses pulsed broadband light (200 nm – 1100 nm) from flashlamps to debond temporarily bonded wafer pairs with glass as the carrier wafer. These flashlamps generate high-intensity pulses of light (up to 45 kW/cm2) over short time intervals (~100 μs) to facilitate the debonding. Feasibility of the PDB in the TB/DB process is demonstrated by successfully debonding thinned (<70 μm) silicon wafers from glass carriers. Post-debond cleaning of the thinned wafers and carriers is evaluated. With uniform, large-area illumination (75 mm x 150 mm) per flashlamp and with the ability to concatenate lamps to increase the illumination area of the PDB tool, the PDB method offers a high-throughput and low-cost debonding solution for both wafer-level and panel-level packaging technologies.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89636968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000308
Kazue Hirano, Masaya Toba, Masaki Yamaguchi
Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu foil with large surface roughness. Though a desmear process and Cu foil can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed prepreg in order to realize a smooth and high adhesive seed layer against the dielectric. We also conducted chemical modification for the surface of Cu foil to achieve low attenuation of transmission loss and high adhesion against prepreg. We successfully assembled Cu wirings with L/S = 6/6 μm on prepregs by SAP. High peel strength between Cu foil and prepreg was obtained due to chemical modification for the surface of Cu foil. The normalized transmission loss of Cu wiring assembled through MSAP was improved as compared to Cu foil with rough surface.
{"title":"Low Transmission Loss Cu Wirings with Smooth Seed Layer and High Adhesion against Prepregs","authors":"Kazue Hirano, Masaya Toba, Masaki Yamaguchi","doi":"10.4071/1085-8024-2021.1.000308","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000308","url":null,"abstract":"\u0000 Semiconductor packages for high performance devices with printed circuit boards having multi wiring layers such as FC-BGA have been attracting the attention in order to realize ultra-reliable and low latency communications in 5G networking. Cu wirings for the package are usually fabricated by semi-additive process (SAP) with desmear process and/or modified semi-additive process (MSAP) by using Cu foil with large surface roughness. Though a desmear process and Cu foil can obtain enough adhesion between dielectric and Cu seed layer by anchoring effect to secure reliabilities, the interface between dielectric and Cu seed layer should be smooth to achieve low attenuation of electric signals at high frequencies. Here, instead of that processes, we applied an UV modification for the surface of our developed prepreg in order to realize a smooth and high adhesive seed layer against the dielectric. We also conducted chemical modification for the surface of Cu foil to achieve low attenuation of transmission loss and high adhesion against prepreg. We successfully assembled Cu wirings with L/S = 6/6 μm on prepregs by SAP. High peel strength between Cu foil and prepreg was obtained due to chemical modification for the surface of Cu foil. The normalized transmission loss of Cu wiring assembled through MSAP was improved as compared to Cu foil with rough surface.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78808689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000176
Aditya Purandare, Yihang Chu, Deepak Kumar, Saikat Mondal, A. Mason, P. Chahal
There has been growing interest in the use of passive harmonic RFIDs for diverse range of applications. Conventional RFIDs are prone to self-jamming and multipath interference, and these challenges can be mitigated using the harmonic RFID design. Recently several harmonic RFID designs have been demonstrated. However, there are many designs related, packaging and intellectual property challenges associated with new tag designs. It has been well known that conventional RFIDs produce harmonic content, which is typically suppressed to reduce background noise. Previous experiments have demonstrated that the harmonics generated by conventional RFIDs can be utilized to enhance their performance. In this paper, an RFID chip is characterized for the generation of harmonic frequencies. This is carried out by designing a high frequency board that contains calibration structures along with structures to characterize the RFID chip using a one port network. An equivalent model is then developed, which in turn is used to design a dual band antenna that works at the fundamental and harmonic frequencies. In addition, the conventional RFID interrogator is modified to accommodate the measurement of harmonics generated by the RFIDs. A complete harmonic tag system is designed and implemented, and an example application of harmonic RFID is demonstrated. Here, the harmonic RFID tag is used in an industrial setting where there is large clutter (large reflections from metal structures).
{"title":"Design and Implementation of Harmonic RFID Based on Conventional UHF System","authors":"Aditya Purandare, Yihang Chu, Deepak Kumar, Saikat Mondal, A. Mason, P. Chahal","doi":"10.4071/1085-8024-2021.1.000176","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000176","url":null,"abstract":"\u0000 There has been growing interest in the use of passive harmonic RFIDs for diverse range of applications. Conventional RFIDs are prone to self-jamming and multipath interference, and these challenges can be mitigated using the harmonic RFID design. Recently several harmonic RFID designs have been demonstrated. However, there are many designs related, packaging and intellectual property challenges associated with new tag designs. It has been well known that conventional RFIDs produce harmonic content, which is typically suppressed to reduce background noise. Previous experiments have demonstrated that the harmonics generated by conventional RFIDs can be utilized to enhance their performance. In this paper, an RFID chip is characterized for the generation of harmonic frequencies. This is carried out by designing a high frequency board that contains calibration structures along with structures to characterize the RFID chip using a one port network. An equivalent model is then developed, which in turn is used to design a dual band antenna that works at the fundamental and harmonic frequencies. In addition, the conventional RFID interrogator is modified to accommodate the measurement of harmonics generated by the RFIDs. A complete harmonic tag system is designed and implemented, and an example application of harmonic RFID is demonstrated. Here, the harmonic RFID tag is used in an industrial setting where there is large clutter (large reflections from metal structures).","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79300584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.
有两种潜在的替代封装方案提出了用味之素积聚膜(ABF)衬底取代倒装芯片球栅阵列(FCBGA)。第一种是不含abf的解决方案，即采用层状预浸料的倒装芯片规模封装(FCCSP)。FCCSP是一种成熟的封装解决方案，可以选择多种预浸料来匹配原始ABF表征。FCCSP的聚焦FCBGA尺寸从10mm × 10mm到21mm × 21mm，衬底层数从1+2+1L到2+2+2L。这些应用包括内存控制器、Wi-Fi处理器和数字电视soc。另一种封装解决方案是扇出球栅阵列(FOBGA)，其目标是具有高ABF层数的更大的FCBGA。FCBGA的最大封装尺寸和层数分别为55 mm × 55 mm和6+2+6L。潜在的应用是cpu、人工智能加速器和网络交换机，这些都需要极高的电气性能。FOBGA的设计理念是在FO芯片上重新分配信号碰撞位置，使ABF基板层容纳更多的I/O信号，进一步减少ABF基板的层数。进行了封装信号完整性(SI)和功率完整性(PI)分析，以验证所提出的封装解决方案的电气性能。最后，我们提出了FOBGA的设计准则，以减轻由于衬底层减少而导致的性能下降。
{"title":"Alternative FCBGA Package Solution Evaluation: High-speed Design Optimization and Electrical Characterization of FOBGA","authors":"Hung-Hsiang Cheng, Cheng-Yu Wu, H. Kuo, Chen-Chao Wang, Guo-Cheng Liao, Yun-Hsiang Tien, Yi-Chuan Ding","doi":"10.4071/1085-8024-2021.1.000119","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000119","url":null,"abstract":"\u0000 There are 2 potentially alternative package solutions proposed to replace Flip-Chip Ball Grid Array (FCBGA) with Ajinomoto build-up film (ABF) substrate. First one is ABF-free solution, Flip-Chip Scale Packages (FCCSP) with laminate-based prepreg material. FCCSP is a mature package solution, and there are various prepreg materials which can be selected to match the original ABF characterization. The focused FCBGA size for FCCSP is from 10 mm x 10 mm to 21 mm x 21 mm, and substrate layer count from 1+2+1L to 2+2+2L. The applications cover memory controllers, Wi-Fi processors, and DTV SoCs. The other package solution is Fan-out Ball Grid Array (FOBGA) which is targeting larger FCBGA with high ABF layer count. The focused maximum package size and layer count of FCBGA are 55 mm x 55 mm and 6+2+6L individually. The potential applications are CPUs, AI accelerators, and networking switches which require extremely high electrical performance. The design concept of FOBGA is to redistribute signal bump locations on FO die, and make an ABF substrate layer accommodate more I/O signals to further reduce the layer count of the ABF substrate. The package signal integrity (SI) and power integrity (PI) analyses are performed to validate the electrical performance of proposed package solutions. Finally, we come out with design guidelines of FOBGA to mitigate the performance degradation due to substrate layer reduction.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"143 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87966718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000006
B. Kim, Sanghyeon Lee, JaeBeom Shim, N. Cho, JinYoung Khim
Wafer fabrication (fab) technology has been scaling down for several decades but now faces many barriers to overcome in terms of technology as well as economy. Beyond Moore's law, the scaling becomes a question of how to cost effectively integrate more functions and achieve better performance. For this matter, the semiconductor industry is looking for packaging solutions using system-on-chip (SoC) or System in Package (SiP) technologies. In this paper, using a commercial mobile application processor (AP), design factors for package integration have been identified and the next level of integration will be proposed by design simulation. The commercial mobile AP package is a good candidate for identifying major design factors because it has evolved in both fab processing and package-level design over many years. Package platform has evolved from a single package to a stack die package and Package-on-Package (PoP) structure. As it is scaled down and interfaced more closely with memory, package technology has evolved but now faces various challenges in structure along with many design constraints. To address these issues, the major drivers and design challenges in package technology will be identified and future direction be proposed.
{"title":"Design Constraints and Scale Down Evolution in Advanced Semiconductor Packages","authors":"B. Kim, Sanghyeon Lee, JaeBeom Shim, N. Cho, JinYoung Khim","doi":"10.4071/1085-8024-2021.1.000006","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000006","url":null,"abstract":"\u0000 Wafer fabrication (fab) technology has been scaling down for several decades but now faces many barriers to overcome in terms of technology as well as economy. Beyond Moore's law, the scaling becomes a question of how to cost effectively integrate more functions and achieve better performance. For this matter, the semiconductor industry is looking for packaging solutions using system-on-chip (SoC) or System in Package (SiP) technologies.\u0000 In this paper, using a commercial mobile application processor (AP), design factors for package integration have been identified and the next level of integration will be proposed by design simulation. The commercial mobile AP package is a good candidate for identifying major design factors because it has evolved in both fab processing and package-level design over many years. Package platform has evolved from a single package to a stack die package and Package-on-Package (PoP) structure. As it is scaled down and interfaced more closely with memory, package technology has evolved but now faces various challenges in structure along with many design constraints. To address these issues, the major drivers and design challenges in package technology will be identified and future direction be proposed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"91 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89389691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000298
A. Shorey, S. Nelson, D. Levy, P. Ballentine
Glass has been of great interest for advanced packaging and RF applications for many years. Since glass is an insulator, it provides low loss performance particularly at high frequencies in the mmWave. The low roughness and ability to form in thin and large area formats provide opportunities for fine line spacing to enable miniaturization and cost-effectiveness. The challenge to glass adoption has been to establish high volume manufacturing operations. Leveraging the Viaffirm® temporary bond process provides many advantages to enable use of existing processes to fabricate thin glass substrates. Here we describe the process and examples of how it has been used to enable manufacture of devices on thin glass substrates.
{"title":"Emergence of Glass Solutions for 5G and Heterogeneous Integration","authors":"A. Shorey, S. Nelson, D. Levy, P. Ballentine","doi":"10.4071/1085-8024-2021.1.000298","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000298","url":null,"abstract":"\u0000 Glass has been of great interest for advanced packaging and RF applications for many years. Since glass is an insulator, it provides low loss performance particularly at high frequencies in the mmWave. The low roughness and ability to form in thin and large area formats provide opportunities for fine line spacing to enable miniaturization and cost-effectiveness. The challenge to glass adoption has been to establish high volume manufacturing operations. Leveraging the Viaffirm® temporary bond process provides many advantages to enable use of existing processes to fabricate thin glass substrates. Here we describe the process and examples of how it has been used to enable manufacture of devices on thin glass substrates.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"51 1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78418088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000249
Curtis Grosskopf
More than 50 years ago when the wire pull test method was initially added to Mil-Std 883, in Condition D of Method 2011, Bond Strength (Destructive Bond Pull Test), the test procedure and minimum pull force values were based on pull testing of mostly ultrasonic wedge bonded aluminum and gold wires of just a few different diameters. The minimum pull force values from that original data were extrapolated to cover a much wider range of wire diameters for both gold and aluminum wires. Since the release of this test method the electronics industry has manufactured copper ultrasonic wedge bonds, widely adopted copper thermosonic ball bonding roughly 15 years ago, and even developed a niche market for silver thermosonic ball bonding. The industry also developed specialty bonds such as security bonds, reverse bonds also called "stitch on ball", and even multi-loop wires and ribbons. In all that time neither the test procedure nor the minimum pull force values in Method 2011 were reviewed to determine their appropriateness for these new materials or new types of bonds, even though the industry widely referenced the test method for all of them and thus, by default, accepted its use for all of them. In late 2013, I led a working group within JEDEC's JC14.1 subcommittee, Reliability Test Methods for Packaged Devices, to update JEDEC JESD22-B116, Ball Bond Shear Test Method, to expand its scope to include the shearing of Cu ball bonds. It took the working group three years to address the necessary technical issues to ensure that the revised test method adequately addressed the shearing of copper ball bonds and propose minimum acceptable shear values. The working group produced a greatly improved document with drawings and images depicting the different shear fail modes of both gold and copper bonds and added several informative annexes to aid in the performing of the test method. By 2018 it was apparent that none of the most commonly referenced wire pull test methods in the electronics industry had made any significant progress in updating their documents to include Cu wire bonds. Therefore, the JC14.1 working group agreed to work jointly with the JC-13.7 Subcommittee, New Electronic Device Technology, to create a new, wire pull test method document under JC14.1 that would be a companion to the JESD22-B116. This new document will use Method 2011, Conditions C and D as its basis, but expand on its scope to cover copper wire bonds, both ultrasonic wedge and thermosonic ball bonds. The new test method will describe the process for a ball pull test and a stitch pull test that are referenced for copper bonds by AEC Q006, Qualification Requirement for Component Using Copper (Cu) Wire Interconnection. The test method will also provide guidance on how to perform pull testing on several different bond types used today including reverse bonds, multi-loop bonds, and stacked die. The working group plans to propose minimum pull values for copper wire bonds which JC14.
50多年前，当金属丝拉力测试方法最初被添加到Mil-Std 883中，在方法2011的条件D中，结合强度(破坏性结合拉力测试)，测试程序和最小拉力值是基于对大多数超声波楔形结合铝和金线的拉力测试，只有几个不同的直径。从原始数据中推断出的最小拉力值适用于更大范围的金线和铝线直径。自从这种测试方法发布以来，电子行业已经制造了铜超声楔形键，大约15年前广泛采用铜热超声球键合，甚至开发了银热超声球键合的利基市场。该行业还开发了特种债券，如证券债券，反向债券也被称为“针上球”，甚至多环线和丝带。在所有这些时间里，测试程序和方法2011中的最小拉力值都没有经过审查，以确定它们对这些新材料或新型键的适用性，尽管行业广泛引用了所有这些测试方法，因此默认情况下接受了所有这些测试方法的使用。2013年底，我在JEDEC的JC14.1小组委员会“封装器件可靠性测试方法”中领导了一个工作组，更新JEDEC JESD22-B116“球键剪切测试方法”，将其范围扩大到包括Cu球键剪切。工作组花了三年时间来解决必要的技术问题，以确保修订后的测试方法充分解决铜球键的剪切问题，并提出可接受的最小剪切值。工作组制作了一份大大改进的文件，其中包含了描绘金键和铜键不同剪切破坏模式的图纸和图像，并增加了几个信息附件，以帮助执行测试方法。到2018年，很明显，电子行业中最常用的拉线测试方法都没有在更新其文件以包括铜线键合方面取得任何重大进展。因此，JC14.1工作组同意与JC-13.7新电子设备技术小组委员会共同合作，在JC14.1下创建一个新的拉丝测试方法文件，该文件将成为JESD22-B116的伴侣。本新文件将使用方法2011，条件C和D作为其基础，但扩展其范围，包括铜线键合，超声楔形键合和热超声球键合。新的测试方法将描述AEC Q006《使用铜(Cu)线互连的组件的资格要求》中铜键参考的球拉试验和针拉试验的过程。该测试方法还将提供如何对几种不同类型的键进行拉测试的指导，包括反向键、多环键和堆叠模。工作组计划提出铜线键合的最小拉力值，JC14.1将在JESD47《集成电路应力测试驱动鉴定》中引用。联合工作组完成工作后,针对在2022年的某个时候,JC13.7将能够使用该工作组2011年更新方法的输出条件C & d .本文将首先简要讨论更新B116覆盖铜导线债券,但主要集中在迄今为止完成的功联合工作组,包括拟议中的新文档的大纲,JESD22-B120,打金线拉力测试方法。
{"title":"JEDEC's Generation of Wire Bond Pull Test Methods to Address Pulling of Copper Wire Bonds","authors":"Curtis Grosskopf","doi":"10.4071/1085-8024-2021.1.000249","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000249","url":null,"abstract":"\u0000 More than 50 years ago when the wire pull test method was initially added to Mil-Std 883, in Condition D of Method 2011, Bond Strength (Destructive Bond Pull Test), the test procedure and minimum pull force values were based on pull testing of mostly ultrasonic wedge bonded aluminum and gold wires of just a few different diameters. The minimum pull force values from that original data were extrapolated to cover a much wider range of wire diameters for both gold and aluminum wires. Since the release of this test method the electronics industry has manufactured copper ultrasonic wedge bonds, widely adopted copper thermosonic ball bonding roughly 15 years ago, and even developed a niche market for silver thermosonic ball bonding. The industry also developed specialty bonds such as security bonds, reverse bonds also called \"stitch on ball\", and even multi-loop wires and ribbons. In all that time neither the test procedure nor the minimum pull force values in Method 2011 were reviewed to determine their appropriateness for these new materials or new types of bonds, even though the industry widely referenced the test method for all of them and thus, by default, accepted its use for all of them.\u0000 In late 2013, I led a working group within JEDEC's JC14.1 subcommittee, Reliability Test Methods for Packaged Devices, to update JEDEC JESD22-B116, Ball Bond Shear Test Method, to expand its scope to include the shearing of Cu ball bonds. It took the working group three years to address the necessary technical issues to ensure that the revised test method adequately addressed the shearing of copper ball bonds and propose minimum acceptable shear values. The working group produced a greatly improved document with drawings and images depicting the different shear fail modes of both gold and copper bonds and added several informative annexes to aid in the performing of the test method.\u0000 By 2018 it was apparent that none of the most commonly referenced wire pull test methods in the electronics industry had made any significant progress in updating their documents to include Cu wire bonds. Therefore, the JC14.1 working group agreed to work jointly with the JC-13.7 Subcommittee, New Electronic Device Technology, to create a new, wire pull test method document under JC14.1 that would be a companion to the JESD22-B116. This new document will use Method 2011, Conditions C and D as its basis, but expand on its scope to cover copper wire bonds, both ultrasonic wedge and thermosonic ball bonds. The new test method will describe the process for a ball pull test and a stitch pull test that are referenced for copper bonds by AEC Q006, Qualification Requirement for Component Using Copper (Cu) Wire Interconnection. The test method will also provide guidance on how to perform pull testing on several different bond types used today including reverse bonds, multi-loop bonds, and stacked die. The working group plans to propose minimum pull values for copper wire bonds which JC14.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76979890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000189
D. Shaddock, C. Hoel, N. Stoffel, M. Poliks, M. Alhendi
There is growing interest in extreme temperature electronics to support the mission needs to sense, actuate, and communicate at temperatures beyond the normal range of operations in commercial and military applications. Reliable packaging in the temperature range of more than 300°C has been demonstrated using ceramic multi-chip modules using conventional hybrid circuit technology. This approach typically requires high NRE costs and lead time. Additive manufacturing processes of metals, ceramics, conductors, and dielectrics provides a digital transformation of hybrid circuit manufacturing technology that reduces time and cost for packaging with the added benefits of novel 3D structures and embedded features. This report presents the results of testing to characterize important electrical and mechanical properties of additively manufactured packaging materials (substrates, conductor, dielectrics) and die interconnect methods needed for 300 to 750 °C electronic packaging designs.
{"title":"Additively Manufactured Extreme Temperature Electronics Packaging","authors":"D. Shaddock, C. Hoel, N. Stoffel, M. Poliks, M. Alhendi","doi":"10.4071/1085-8024-2021.1.000189","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000189","url":null,"abstract":"\u0000 There is growing interest in extreme temperature electronics to support the mission needs to sense, actuate, and communicate at temperatures beyond the normal range of operations in commercial and military applications. Reliable packaging in the temperature range of more than 300°C has been demonstrated using ceramic multi-chip modules using conventional hybrid circuit technology. This approach typically requires high NRE costs and lead time. Additive manufacturing processes of metals, ceramics, conductors, and dielectrics provides a digital transformation of hybrid circuit manufacturing technology that reduces time and cost for packaging with the added benefits of novel 3D structures and embedded features. This report presents the results of testing to characterize important electrical and mechanical properties of additively manufactured packaging materials (substrates, conductor, dielectrics) and die interconnect methods needed for 300 to 750 °C electronic packaging designs.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74907657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000292
T. Bernhard, R. Massey, K. Klaeden, S. Zarwell, S. Kempa, E. Steinhaeuser, S. Dieter, F. Brüning
Plated microvias are widely used within todays PCB industry as a means of achieving the high-density designs that are required in modern mobile devices, however, there has been growing concern regarding their long term reliability performance when stacked directly on top of each other. Blind microvias (BMV) have a potentially complex metallurgical structure, with several interfaces located around the target pad - electroless Copper - electrolytic Copper joint. While field experience as shown that there are typically two major types of crystal structures formed across the BMV base, there has been little reported work investigating how or why such structures develop. In this paper, we review these two commonly observed microstructures within filled BMVs and offer proposals on how such structures are created. We subsequently describe a novel means to indicate if the microstructure of a BMV is likely to have a tendency for an early onset of failure.
{"title":"Copper Crystal Structures in Plated Microvias. Their Recrystallisation and a Means to Identify Joints at Risk of Premature Failure","authors":"T. Bernhard, R. Massey, K. Klaeden, S. Zarwell, S. Kempa, E. Steinhaeuser, S. Dieter, F. Brüning","doi":"10.4071/1085-8024-2021.1.000292","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000292","url":null,"abstract":"\u0000 Plated microvias are widely used within todays PCB industry as a means of achieving the high-density designs that are required in modern mobile devices, however, there has been growing concern regarding their long term reliability performance when stacked directly on top of each other.\u0000 Blind microvias (BMV) have a potentially complex metallurgical structure, with several interfaces located around the target pad - electroless Copper - electrolytic Copper joint. While field experience as shown that there are typically two major types of crystal structures formed across the BMV base, there has been little reported work investigating how or why such structures develop. In this paper, we review these two commonly observed microstructures within filled BMVs and offer proposals on how such structures are created. We subsequently describe a novel means to indicate if the microstructure of a BMV is likely to have a tendency for an early onset of failure.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"107 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74918148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000136
M. Tsai, Yung-Sheng Lin, C. Kao, Shan-Bo Wang, T. Lin, Y. Hung
The Sn-4Ag-0.5Cu base solder adding 3 wt.% bismuth (SAC-3Bi) solder has better drop and thermal cycling performance than Sn-4Ag-0.5Cu solder due the excellent mechanical properties in previous study. Therefore, SAC-3Bi has applied in solder joints of wafer level chip scale packaging (WLCSP) in recent year. In this study, SAC-3Bi solder was used on WLCSP device to evaluate electromigration reliability. A specially designed test vehicle for SAC-3Bi solder balls with 200μm diameter Ti/Cu/Cu UBM have been investigated experimentally. The electromigration behavior of solder balls was investigated in terms of the electrical resistance change, and the mechanism was also explored by the microstructure evolutions. The electromigration experiment of the SAC-3Bi solder balls was conducted continuously at 1.2 A to 1.6 A under 170 °C to 185 °C condition. The resistance of solder balls was monitored according to Kelvin structure. An EM prediction model of SAC-3Bi solder balls was built based on Black-type electromigration time to failure equation, followed the JEDEC with five test conditions. The activation energy of SAC-3Bi solder is 0.80 eV ± 0.02 eV, coinciding the activation energy of SAC based solder alloy (0.72 eV ~ 0.89 eV). The microstructure of the solder balls was investigated using a scanning electron microscope (SEM) accompanying energy-dispersive X-ray spectroscopy (EDS) and electron backscatter diffraction (EBSD) for the failure behaviors and phase characterization. There were intermetallic compounds of Cu3Sn and Cu6Sn5 at the interface of copper and solder. We observed two failure modes of SAC-3Bi solder balls during current stressing, the fracture occurred at the UBM/solder ball interface and Cu redistribution layer (RDL), respectively. The failure mechanisms have been investigated in detail from microstructure analysis.
{"title":"Effect of Novel SAC-Bi Solder Joints on Electromigration Reliability for Wafer Level Chip Scale Packages","authors":"M. Tsai, Yung-Sheng Lin, C. Kao, Shan-Bo Wang, T. Lin, Y. Hung","doi":"10.4071/1085-8024-2021.1.000136","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000136","url":null,"abstract":"\u0000 The Sn-4Ag-0.5Cu base solder adding 3 wt.% bismuth (SAC-3Bi) solder has better drop and thermal cycling performance than Sn-4Ag-0.5Cu solder due the excellent mechanical properties in previous study. Therefore, SAC-3Bi has applied in solder joints of wafer level chip scale packaging (WLCSP) in recent year. In this study, SAC-3Bi solder was used on WLCSP device to evaluate electromigration reliability. A specially designed test vehicle for SAC-3Bi solder balls with 200μm diameter Ti/Cu/Cu UBM have been investigated experimentally. The electromigration behavior of solder balls was investigated in terms of the electrical resistance change, and the mechanism was also explored by the microstructure evolutions. The electromigration experiment of the SAC-3Bi solder balls was conducted continuously at 1.2 A to 1.6 A under 170 °C to 185 °C condition. The resistance of solder balls was monitored according to Kelvin structure. An EM prediction model of SAC-3Bi solder balls was built based on Black-type electromigration time to failure equation, followed the JEDEC with five test conditions. The activation energy of SAC-3Bi solder is 0.80 eV ± 0.02 eV, coinciding the activation energy of SAC based solder alloy (0.72 eV ~ 0.89 eV). The microstructure of the solder balls was investigated using a scanning electron microscope (SEM) accompanying energy-dispersive X-ray spectroscopy (EDS) and electron backscatter diffraction (EBSD) for the failure behaviors and phase characterization. There were intermetallic compounds of Cu3Sn and Cu6Sn5 at the interface of copper and solder. We observed two failure modes of SAC-3Bi solder balls during current stressing, the fracture occurred at the UBM/solder ball interface and Cu redistribution layer (RDL), respectively. The failure mechanisms have been investigated in detail from microstructure analysis.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"109 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76095165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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