Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000234
Chih-Yi Huang, Lihong Cao, K. Chang, Chen-Chao Wang
With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc. The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design. In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.
{"title":"High Density Package Design Platform and Assembly Design Kit","authors":"Chih-Yi Huang, Lihong Cao, K. Chang, Chen-Chao Wang","doi":"10.4071/1085-8024-2021.1.000234","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000234","url":null,"abstract":"\u0000 With the miniaturization of integrated circuit technology and process, chips are getting smaller and smaller, and thus it results in fan-out packaging with RDL process was derived to extend the ball grid array design space. The applicable range of RDL now includes products in the fields of Networking, HPC, AI and even SiPh. And the new package types comprised of the RDL process include e-WLB, chip first FOCoS, chip last FOCoS, FO-PoP and 2.5D IC etc.\u0000 The total pin count in FOCoS packaging can be more than ten times than that the pin counts in a large FCBGA packaging; the FOCoS package layout density can reach tens or even hundreds of times than FCBGA. High density and complex connectivity in FOCoS cause more difficult using traditional EDA tool for packaging design. In addition, the RDL process manufacturing equipment is different from that for traditional packaging substrate and it is more like the foundry process, so it is required to consider design rule check and LVS check flow compatible to IC design flow except for the package layout. It is necessary to have different methods and tools from that in the past to complete a reliable design.\u0000 In this paper, there is an introduction about the new design flow and platform for high density package design and it describes the new design platform could overcome the difficulties of layout on high-density packages such as FOCoS. And then talking about FOCoS Assembly Design Kit (ADK) to provide to the IC or system designers, especially the new design rule checking tools and procedure, as well as example about how DRC tools plays an important role in RDL process improvement and design. In addition to checking the design rule for the layout, verifying the interconnections between the components in the package after design is very important to FOCoS packaging which is generally used in multiple dice integration such as homogeneous and heterogeneous integration design.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81513624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000112
Huaibin Zhen, Zhao Wei, Gu Xiao, Chen Dong, Che Haijie, Xu Hong, K. Tan
At present, the general fan-out package generally uses the molding process and uses epoxy molding compound (EMC) material to complete the reconstruction of wafer, but it is not friendly to small-size chips and high fan-out ratio packaging types. In order to solve the problem of small size and high fan-out ratio and other fan-out packaging, JCET ADVANCED PACKAGING CO., LTD. introduced a new kind of encapsulation material, and the wafer reconstruction process in the fan out package is accomplished through three basic processes, such as the lamination process, the leveling process and the silicon support process. However, it also faces warpage problems after curing. Excessive warpage poses a significant challenge to subsequent RDL fabrication, mid-testing and process automation. In this paper, the actual process is reasonably assumed and finite element methods are used to study the effects of chip thickness, fan-out area, the encapsulation material properties and support silicon wafer on the warpage after curing. The lamination process is that an airbag slowly squeezes the encapsulation material into the fan-out area, and the pressure of the airbag can be adjusted by the gas in and out. The wafer surface is uneven after the lamination process, so it needs to be leveled by the leveling process. Leveling process is to make the uneven surface smooth by a heavy and proper amount of steel plate. The encapsulation material is soft, so it is necessary to support the silicon wafer in order to enhance the strength of the structure. In this paper, the curing process is divided into two processes: pre curing process and post curing process. The main function of pre curing is to shape the encapsulation material, and then post curing can make the encapsulation material, chip and supporting silicon have a better combination. The lamination, leveling, and silicon support processes do not involve higher temperatures, so it can be assumed that the reconstructed wafer has no residual stress and warpage. In order to save computer resources and shorten the verification period, the geometric model of simulation is simplified under the condition of ensuring accuracy. Through the finite element method to explore the influence of structural characteristics and material characteristics on the wafer warpage, the selection of parameters is determined according to the actual situation, so as to meet the manufacturability of the structure. The results indicate that with the increase of the thickness of the encapsulated material the encapsulation, wafer warpage is gradually increasing, while the encapsulation material with low modulus and small CTE can improve warpage performance. High modulus, thicker support silicon has a significant effect on reducing warpage, and larger CTE support silicon can also effectively reduce wafer warpage because the larger CTE support silicon reduces the degree of mismatch with the encapsulation CTE. Thinner chips and high fan-out areas tend to
{"title":"Numerical simulation on the warpage of reconstructed wafer during encapsulation process","authors":"Huaibin Zhen, Zhao Wei, Gu Xiao, Chen Dong, Che Haijie, Xu Hong, K. Tan","doi":"10.4071/1085-8024-2021.1.000112","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000112","url":null,"abstract":"\u0000 At present, the general fan-out package generally uses the molding process and uses epoxy molding compound (EMC) material to complete the reconstruction of wafer, but it is not friendly to small-size chips and high fan-out ratio packaging types. In order to solve the problem of small size and high fan-out ratio and other fan-out packaging, JCET ADVANCED PACKAGING CO., LTD. introduced a new kind of encapsulation material, and the wafer reconstruction process in the fan out package is accomplished through three basic processes, such as the lamination process, the leveling process and the silicon support process. However, it also faces warpage problems after curing. Excessive warpage poses a significant challenge to subsequent RDL fabrication, mid-testing and process automation.\u0000 In this paper, the actual process is reasonably assumed and finite element methods are used to study the effects of chip thickness, fan-out area, the encapsulation material properties and support silicon wafer on the warpage after curing. The lamination process is that an airbag slowly squeezes the encapsulation material into the fan-out area, and the pressure of the airbag can be adjusted by the gas in and out. The wafer surface is uneven after the lamination process, so it needs to be leveled by the leveling process. Leveling process is to make the uneven surface smooth by a heavy and proper amount of steel plate. The encapsulation material is soft, so it is necessary to support the silicon wafer in order to enhance the strength of the structure. In this paper, the curing process is divided into two processes: pre curing process and post curing process. The main function of pre curing is to shape the encapsulation material, and then post curing can make the encapsulation material, chip and supporting silicon have a better combination. The lamination, leveling, and silicon support processes do not involve higher temperatures, so it can be assumed that the reconstructed wafer has no residual stress and warpage. In order to save computer resources and shorten the verification period, the geometric model of simulation is simplified under the condition of ensuring accuracy. Through the finite element method to explore the influence of structural characteristics and material characteristics on the wafer warpage, the selection of parameters is determined according to the actual situation, so as to meet the manufacturability of the structure.\u0000 The results indicate that with the increase of the thickness of the encapsulated material the encapsulation, wafer warpage is gradually increasing, while the encapsulation material with low modulus and small CTE can improve warpage performance. High modulus, thicker support silicon has a significant effect on reducing warpage, and larger CTE support silicon can also effectively reduce wafer warpage because the larger CTE support silicon reduces the degree of mismatch with the encapsulation CTE. Thinner chips and high fan-out areas tend to","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88423487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000166
A. Kaiser, P. Matej, K. Hanka, M. Abel, C. Herbort, R. Lang, O. Pursche, K. Ruess, U. Keim
The requirements for thin film substrates have increased over the last years, as new materials, ongoing miniaturization and higher connectivity and complexity of circuit designs are arising. Especially the medical field, with its various application areas, drives the development of new technologies and new material combinations. Specifically, components for catheter or endoscope equipment are often difficult to realize, as limited space/cross section compete with the demand for higher functionality in the tip, and thus, requiring a higher number of connections to be routed out. One possibility to overcome this problem, is a local digitalization of the signals of the various sensors in the tip and doing a serial data transmission to the outside, reducing the required number of leads. To maintain a very small form factor, we have developed a technology that allows the direct integration of thinned ASIC chips into thin film flexible circuits. An example application, for the readout of catheter shape and positioning, was realized. Our contribution will give an overview of the target application and describe the integration technology for the thinned dies together with the build-up of the thin film flexible circuits.
{"title":"Thin film flexible circuits with embedded ASICs–Enabling technology for sophisticated medical applications","authors":"A. Kaiser, P. Matej, K. Hanka, M. Abel, C. Herbort, R. Lang, O. Pursche, K. Ruess, U. Keim","doi":"10.4071/1085-8024-2021.1.000166","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000166","url":null,"abstract":"\u0000 The requirements for thin film substrates have increased over the last years, as new materials, ongoing miniaturization and higher connectivity and complexity of circuit designs are arising. Especially the medical field, with its various application areas, drives the development of new technologies and new material combinations. Specifically, components for catheter or endoscope equipment are often difficult to realize, as limited space/cross section compete with the demand for higher functionality in the tip, and thus, requiring a higher number of connections to be routed out. One possibility to overcome this problem, is a local digitalization of the signals of the various sensors in the tip and doing a serial data transmission to the outside, reducing the required number of leads. To maintain a very small form factor, we have developed a technology that allows the direct integration of thinned ASIC chips into thin film flexible circuits. An example application, for the readout of catheter shape and positioning, was realized.\u0000 Our contribution will give an overview of the target application and describe the integration technology for the thinned dies together with the build-up of the thin film flexible circuits.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84196070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000212
Ken Zhang, N. Kao, David Lai, Yu-Po Wang
ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it has fine trace, better trace dimension control and low cost advantages which compared to normal substrate. But it usually encountered more serious warpage issue for bare substrate and complete package which may influence D/B (die bonding) and SMT yield rate due to its coreless characteristic. Especially for ETS substrate with special trace pattern design (ex. larger Copper area), bare substrate may appear peculiar warpage contour and led to serious non-wetting issue at specific location during D/B process. Thus, if it can predict warpage value and contour accurately for bare substrate and package is an important topic. In this paper, a FCCSP package with ETS substrate was chosen to study trace impact. Bare substrate and package warpage simulation models w/ and w/o considering trace pattern by trace mapping method were performed and compared to shadow moiré results. Analysis results showed that simulation w/ considering trace pattern could get more accurate warpage value and more similar warpage contour for bare substrate and package warpage.
{"title":"Warpage Simulation Study by Trace Mapping Method for FCCSP with ETS Substrate","authors":"Ken Zhang, N. Kao, David Lai, Yu-Po Wang","doi":"10.4071/1085-8024-2021.1.000212","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000212","url":null,"abstract":"\u0000 ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it has fine trace, better trace dimension control and low cost advantages which compared to normal substrate. But it usually encountered more serious warpage issue for bare substrate and complete package which may influence D/B (die bonding) and SMT yield rate due to its coreless characteristic. Especially for ETS substrate with special trace pattern design (ex. larger Copper area), bare substrate may appear peculiar warpage contour and led to serious non-wetting issue at specific location during D/B process. Thus, if it can predict warpage value and contour accurately for bare substrate and package is an important topic.\u0000 In this paper, a FCCSP package with ETS substrate was chosen to study trace impact. Bare substrate and package warpage simulation models w/ and w/o considering trace pattern by trace mapping method were performed and compared to shadow moiré results. Analysis results showed that simulation w/ considering trace pattern could get more accurate warpage value and more similar warpage contour for bare substrate and package warpage.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"29 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89738313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-01DOI: 10.4071/2380-4505-2020.1.000165
B. Peterson, M. Kwan, F. Duewer, Andrew Reid, Rhiannon Brooks
Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said the same in the 60’s. But after decades of increased device level integration, it is an important change. Figure 1 shows an example (future) device: there are large bumps, hybrid bonds--for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point. Figure 1: The wide variety of interconnects on future advanced packages Figure 2: the triangle of misery as applied to standard and Advanced xray imaging (AXI) Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield. There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose. In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.
{"title":"Optimizing X-Ray Inspection for Advanced Packaging Applications","authors":"B. Peterson, M. Kwan, F. Duewer, Andrew Reid, Rhiannon Brooks","doi":"10.4071/2380-4505-2020.1.000165","DOIUrl":"https://doi.org/10.4071/2380-4505-2020.1.000165","url":null,"abstract":"\u0000 Over the coming decade, advanced packaging will become increasingly critical to performance, cost, and density improvements in advanced electronics. There is both an industry push: cost and performance advances in transistor scaling are increasingly difficult. And there is an industry pull: customization for each market can be done far more quickly by assembling a series of parts in a package, rather than by design and integration into a single device. This isnt a new idea: Gordon Moore said the same in the 60’s. But after decades of increased device level integration, it is an important change.\u0000 Figure 1 shows an example (future) device: there are large bumps, hybrid bonds--for extreme bandwidth and low latency connection to cache memory, TSV based DRAM, and multiple CPU to CPU interconnects. Each of these is a failure point.\u0000 Figure 1: The wide variety of interconnects on future advanced packages Figure 2: the triangle of misery as applied to standard and Advanced xray imaging (AXI)\u0000 Manufacturing will necessarily advance in the packaging arena: pin density and package size will both increase to support the high bandwidth and device integration demands. The downside of multiple device integration is a higher set of requirements on the reliability of both the individual devices and the fully assembled system. This is an opportunity to take advantage of new strategies and technologies in package inspection. The sampling challenges for both control and inspection for high reliability require systems that can run at 100% coverage and millions of units per year. An overview of reliability sampling challenges as it relates to the end of line inspection, as well as sampling for both defect type and incidence is critical to understanding how and what to measure to maximize yield.\u0000 There are fundamental tradeoffs between speed, resolution, and signal to noise ratio that inform a systematic engineering understanding of inspection. Optimizing that trade-off specifically for semiconductor inspection leads to dedicated tools with extremely high resolution, speed, and low dose.\u0000 In parallel with the speed requirements, sensitivity, and noise immunity can be improved with an understanding of the systematic sources of noise. These can be mitigated and even eliminated with novel algorithms for both image enhancement and defect location.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"40 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77748997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, C. Ko, C. Peng, Kai-Ming Yang, Tim Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Winnie Lu
In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.
{"title":"Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration","authors":"J. Lau, C. Ko, C. Peng, Kai-Ming Yang, Tim Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Winnie Lu","doi":"10.4071/imaps.1137828","DOIUrl":"https://doi.org/10.4071/imaps.1137828","url":null,"abstract":"\u0000 In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"49 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74144461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-19DOI: 10.4071/2380-4505-2019.1.invitedaihardware000014
O. Suzuki
Invited Session on FUTURE SEMICONDUCTOR PACKAGES FOR AI HARDWARE. Outline: Applications for Advanced Packaging; Global AI Computing Hardware Total Available Market (TAM); Die partitions; Defect Density; FC-BGA Families Trends; Technical Challenges of CUF; Underfills for Advanced Packaging; Severe KOZ on MCM; Bleed Out; Formulation Technique; Concerns during penetration; Chip package interaction (CPI) Challenges; and summary.
{"title":"Recent Advances in Underfill Materials","authors":"O. Suzuki","doi":"10.4071/2380-4505-2019.1.invitedaihardware000014","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.invitedaihardware000014","url":null,"abstract":"\u0000 Invited Session on FUTURE SEMICONDUCTOR PACKAGES FOR AI HARDWARE. Outline: Applications for Advanced Packaging; Global AI Computing Hardware Total Available Market (TAM); Die partitions; Defect Density; FC-BGA Families Trends; Technical Challenges of CUF; Underfills for Advanced Packaging; Severe KOZ on MCM; Bleed Out; Formulation Technique; Concerns during penetration; Chip package interaction (CPI) Challenges; and summary.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"6 2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78397610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-19DOI: 10.4071/2380-4505-2019.1.invitedhir000001
William Chen
Invited Session on HETEROGENEOUS INTEGRATION ROADMAP - Driving Force and Enabling Technology for Systems of the Future. Outline: Introduction and brief overview of the landscape; Heterogeneous Integration is the path forward; Heterogeneous Integration in the smartphone; Heterogeneous integration in high performance applications; Heterogeneous Integration Roadmap; and Summary.
{"title":"Driving Force and Enabling Technology for Systems of the Future","authors":"William Chen","doi":"10.4071/2380-4505-2019.1.invitedhir000001","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.invitedhir000001","url":null,"abstract":"\u0000 Invited Session on HETEROGENEOUS INTEGRATION ROADMAP - Driving Force and Enabling Technology for Systems of the Future. Outline: Introduction and brief overview of the landscape; Heterogeneous Integration is the path forward; Heterogeneous Integration in the smartphone; Heterogeneous integration in high performance applications; Heterogeneous Integration Roadmap; and Summary.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79842851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000550
T. Salzer
In this article, we describe a novel process for hermetic projection weld sealing of semiconductor devices, considered by many to be an important legacy technology from decades gone bye, but not particularly relevant in today's arsenal of sealing technologies. We will demonstrate that with appropriate modifications to be described, this technology can used to seal various high power devices as well as high reliability semiconductors, crystals, hybrid packages, medical electronics, photonic devices, automotive electronics, etc. Its features primarily stem from the fact that it can be used to quickly and efficiently produce true hermetic seals in components. The welding is so rapid, that it is essentially a room temperature technology and the equipment is small enough that it can be housed in an atmosphere controlled chamber filled with any gas that is not explosive. Air, Nitrogen, Argon, Helium and their mixtures are the most commonly utilized gasses. The process is so adiabatic that it can be used to seal many liquids also. In some applications the technology competes against pulsed laser welding, but unlike laser welding the entire seal takes place in a few milliseconds because it is a single discharge, component-shaped spot/projection weld, which means that the entire seam is made in a single high speed discharge. So, in the same time that it takes a laser welding machine to make one of the many small overlapping spot welds required to make a seal, the projection welder has completed the entire operation. This process results in minimal stress and distortion, and maximum hermetic properties, strength and reliability, without requiring electroplating or preforms. Because the weld involves the localized high speed melting of metals, it among the highest energy density processes. A concern with the earlier resistance welding technologies has been the expulsion of particulates, both out of, and into the seal. This expulsion has been systemic and becomes progressively worse as the package size increases. In the course of this presentation we will demonstrate how this concern has been dealt with and corrected. Internal dew points can be held to −40 degrees, or lower if required. Other common applications for this technology include sealing and welding of nuts and studs for hermetic applications and sealing of devices for medical applications that must endure autoclave sterilization. In the course of this presentation, we will take you back to the roots of the original resistance welding process as taught by the early process developers so that you will understand how things have changed, and the reasons for the changes.
{"title":"Advances in Hermetic Projection Weld Sealing","authors":"T. Salzer","doi":"10.4071/2380-4505-2019.1.000550","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000550","url":null,"abstract":"\u0000 In this article, we describe a novel process for hermetic projection weld sealing of semiconductor devices, considered by many to be an important legacy technology from decades gone bye, but not particularly relevant in today's arsenal of sealing technologies. We will demonstrate that with appropriate modifications to be described, this technology can used to seal various high power devices as well as high reliability semiconductors, crystals, hybrid packages, medical electronics, photonic devices, automotive electronics, etc. Its features primarily stem from the fact that it can be used to quickly and efficiently produce true hermetic seals in components. The welding is so rapid, that it is essentially a room temperature technology and the equipment is small enough that it can be housed in an atmosphere controlled chamber filled with any gas that is not explosive. Air, Nitrogen, Argon, Helium and their mixtures are the most commonly utilized gasses. The process is so adiabatic that it can be used to seal many liquids also. In some applications the technology competes against pulsed laser welding, but unlike laser welding the entire seal takes place in a few milliseconds because it is a single discharge, component-shaped spot/projection weld, which means that the entire seam is made in a single high speed discharge. So, in the same time that it takes a laser welding machine to make one of the many small overlapping spot welds required to make a seal, the projection welder has completed the entire operation. This process results in minimal stress and distortion, and maximum hermetic properties, strength and reliability, without requiring electroplating or preforms. Because the weld involves the localized high speed melting of metals, it among the highest energy density processes. A concern with the earlier resistance welding technologies has been the expulsion of particulates, both out of, and into the seal. This expulsion has been systemic and becomes progressively worse as the package size increases. In the course of this presentation we will demonstrate how this concern has been dealt with and corrected. Internal dew points can be held to −40 degrees, or lower if required. Other common applications for this technology include sealing and welding of nuts and studs for hermetic applications and sealing of devices for medical applications that must endure autoclave sterilization. In the course of this presentation, we will take you back to the roots of the original resistance welding process as taught by the early process developers so that you will understand how things have changed, and the reasons for the changes.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"189 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77362163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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