Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000321
Michael Woodcox, Manuel Smeu
The reliability of solder joints depends upon the strength of the interface where two materials are joined. The strengthening of solder joints has been routinely achieved via doping with other elements, though this is not yet well understood at a fundamental level, and typically accomplished by trial and error. In the present work, we have used atomistic modeling based on density functional theory (DFT) and ab initio molecular dynamics (AIMD) to study the mechanical strength of the Sn-Cu interface under various conditions. We have investigated the cleavage energy (CE) of the Sn-Cu interface, and how it changes with various dopants (Ag, Au, Bi, Cu, Ni, Zn) to determine the benefit (or detriment) to the strength of this simulated solder joint. We have also tested multiple faces of Sn ([001], [100] and [110]) as potential interfaces with Cu. Our simulations show that each of the dopants considered, except for Bi, increases the strength of the interface. In all our constructed Sn-Bi interfaces, a single atomic layer of Sn atoms deposits on the Cu and binds strongly to it. The weakest point of the interface is located between the deposited Sn layer and the remaining bulk Sn. For the undoped [001] Sn-Cu system, the cleavage energy between the Sn and Cu layers is 1.63 J/m2, whereas the cleavage energy between the deposited layer of Sn and the remaining Sn bulk is considerably lower: 0.54 J/m2; this is likely the location of joint failure, and the focus of our investigation. We observed this trend in each interface that we studied. As expected, the strength of the Sn-Cu interface can be modified with dopants; the CE of the weakest point can be increased (strengthening it) by 0.1–0.2 J/m2 when doping it with Ag, Au, Cu, Ni and Zn, though Bi results in a decrease (weakening it) by 0.15 J/m2. As a complementary method for investigating this interface, we have used AIMD to simulate a mechanically controlled break junction (MCBJ) of the solder interface by gradually increasing the separation between the two ends of the simulated junction. The process is continued until the junction completely breaks, yielding an energy vs. distance curve, which provides information about the strength of the solder joint that is similar to a stress-strain curve. We observe that, as the Sn is moved away from the Cu, there is a relatively steady increase in energy until the system begins to separate. From this separation point, the energy curve plateaus as the interaction between the two halves of the system vanishes. The location of the breaking point is in excellent accordance with our CE calculations; there is also a correlation between the CE and the amount of distance that the system must be stretched before reaching the breaking point. Furthermore, we have adapted the MCBJ method in AIMD to simulate shearing of the Sn-Cu interface. In these simulations, as opposed to moving Sn atoms away from the Cu atoms perpendicularly to the interface, we are sliding the Sn atoms late
{"title":"Atomistic modeling to predict and improve the strength of doped Sn-Cu solder interfaces","authors":"Michael Woodcox, Manuel Smeu","doi":"10.4071/1085-8024-2021.1.000321","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000321","url":null,"abstract":"\u0000 The reliability of solder joints depends upon the strength of the interface where two materials are joined. The strengthening of solder joints has been routinely achieved via doping with other elements, though this is not yet well understood at a fundamental level, and typically accomplished by trial and error. In the present work, we have used atomistic modeling based on density functional theory (DFT) and ab initio molecular dynamics (AIMD) to study the mechanical strength of the Sn-Cu interface under various conditions. We have investigated the cleavage energy (CE) of the Sn-Cu interface, and how it changes with various dopants (Ag, Au, Bi, Cu, Ni, Zn) to determine the benefit (or detriment) to the strength of this simulated solder joint. We have also tested multiple faces of Sn ([001], [100] and [110]) as potential interfaces with Cu. Our simulations show that each of the dopants considered, except for Bi, increases the strength of the interface. In all our constructed Sn-Bi interfaces, a single atomic layer of Sn atoms deposits on the Cu and binds strongly to it. The weakest point of the interface is located between the deposited Sn layer and the remaining bulk Sn. For the undoped [001] Sn-Cu system, the cleavage energy between the Sn and Cu layers is 1.63 J/m2, whereas the cleavage energy between the deposited layer of Sn and the remaining Sn bulk is considerably lower: 0.54 J/m2; this is likely the location of joint failure, and the focus of our investigation. We observed this trend in each interface that we studied. As expected, the strength of the Sn-Cu interface can be modified with dopants; the CE of the weakest point can be increased (strengthening it) by 0.1–0.2 J/m2 when doping it with Ag, Au, Cu, Ni and Zn, though Bi results in a decrease (weakening it) by 0.15 J/m2. As a complementary method for investigating this interface, we have used AIMD to simulate a mechanically controlled break junction (MCBJ) of the solder interface by gradually increasing the separation between the two ends of the simulated junction. The process is continued until the junction completely breaks, yielding an energy vs. distance curve, which provides information about the strength of the solder joint that is similar to a stress-strain curve. We observe that, as the Sn is moved away from the Cu, there is a relatively steady increase in energy until the system begins to separate. From this separation point, the energy curve plateaus as the interaction between the two halves of the system vanishes. The location of the breaking point is in excellent accordance with our CE calculations; there is also a correlation between the CE and the amount of distance that the system must be stretched before reaching the breaking point. Furthermore, we have adapted the MCBJ method in AIMD to simulate shearing of the Sn-Cu interface. In these simulations, as opposed to moving Sn atoms away from the Cu atoms perpendicularly to the interface, we are sliding the Sn atoms late","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"39 1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76330338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000098
M. Letz, T. Gotschke, F. Wagner, M. Heiss-Chouquet, L. Müller, U. Peuchert, D. Vanderpool
Glasses can be used as core substrate for panel- and/or wafer-level packaging to achieve heterogeneous integration of chiplets and integrated passives in increasingly complex packages. Glass has a large number of advantages: The stiffness of glass (i) allows manufacturing of highly accurate buildup layers. These buildup layers can have manufacturing precision of 1μm and below on large dies with sizes of 50mm x 50mm and more, needed for antenna in package (AiP) applications and high performance computing (HPC). Special glasses can be made with adjusted thermal expansion (CTE) (ii), either adjusted to silicon or with larger thermal expansion to allow packages with buildup layers of epoxy molds and metallization that see high thermal loads either during manufacturing or during operation. Glasses can also be optimized with very good dielectric properties (iii) and can be utilized in antenna-in-package applications. But most of all, economic glass structuring techniques (iv) which can provide millions of vias and thousands of cut-outs in a glass panel are important and are being developed. SCHOTTs Structured Glass Portfolio FLEXINITY® and related technologies provide an excellent starting point for highly sophisticated structured glass substrates required for Advanced Packaging. The biggest hurdle for a large-scale commercialization of glass panel packaging is industrial readiness along the whole process chain. This is needed, to bring glass panel packaging in applications like IC-packaging, RF-MEMS packaging and medical diagnostics or, in combination with cutouts for fan-out, embedding of active and passive components. In addition, metallization processes with good adhesion, excellent electrical properties and high geometric accuracy for glasses are an important step. In the current manuscript, we review the status and discuss our contribution towards achieving industrial readiness for glass in panel- and wafer-level packaging.
玻璃可以用作面板和/或晶圆级封装的核心基板，以在日益复杂的封装中实现小芯片和集成无源的异构集成。玻璃有很多优点:玻璃的刚度(1)允许制造高度精确的堆积层。这些堆积层在尺寸为50mm x 50mm及以上的大型模具上的制造精度可达1μm及以下，适用于封装天线(AiP)应用和高性能计算(HPC)。特殊玻璃可以通过调整热膨胀(CTE) (ii)来制造，既可以调整为硅，也可以调整为更大的热膨胀，以允许在制造或操作过程中具有高热负荷的环氧模具和金属化层的封装。玻璃也可以优化为具有非常好的介电性能(iii)，并可用于天线封装应用。但最重要的是，经济的玻璃结构技术(iv)，它可以在玻璃面板上提供数百万个过孔和数千个切口，是重要的，并且正在开发中。肖特结构化玻璃组合flexity®和相关技术为先进封装所需的高度复杂的结构化玻璃基板提供了一个很好的起点。玻璃面板包装大规模商业化的最大障碍是整个工艺链上的工业准备。这是将玻璃面板封装应用于ic封装、RF-MEMS封装和医疗诊断等应用所必需的，或者与扇形输出的切割结合使用，嵌入有源和无源组件。此外，具有良好附着力、优异电性能和高几何精度的金属化工艺是玻璃的重要一步。在目前的手稿中，我们回顾了现状，并讨论了我们对实现面板和晶圆级封装玻璃的工业就绪度的贡献。
{"title":"Structured glass substrates in wafer- and panel level packaging: Status and recent achievements.","authors":"M. Letz, T. Gotschke, F. Wagner, M. Heiss-Chouquet, L. Müller, U. Peuchert, D. Vanderpool","doi":"10.4071/1085-8024-2021.1.000098","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000098","url":null,"abstract":"\u0000 Glasses can be used as core substrate for panel- and/or wafer-level packaging to achieve heterogeneous integration of chiplets and integrated passives in increasingly complex packages. Glass has a large number of advantages: The stiffness of glass (i) allows manufacturing of highly accurate buildup layers. These buildup layers can have manufacturing precision of 1μm and below on large dies with sizes of 50mm x 50mm and more, needed for antenna in package (AiP) applications and high performance computing (HPC). Special glasses can be made with adjusted thermal expansion (CTE) (ii), either adjusted to silicon or with larger thermal expansion to allow packages with buildup layers of epoxy molds and metallization that see high thermal loads either during manufacturing or during operation. Glasses can also be optimized with very good dielectric properties (iii) and can be utilized in antenna-in-package applications. But most of all, economic glass structuring techniques (iv) which can provide millions of vias and thousands of cut-outs in a glass panel are important and are being developed. SCHOTTs Structured Glass Portfolio FLEXINITY® and related technologies provide an excellent starting point for highly sophisticated structured glass substrates required for Advanced Packaging. The biggest hurdle for a large-scale commercialization of glass panel packaging is industrial readiness along the whole process chain. This is needed, to bring glass panel packaging in applications like IC-packaging, RF-MEMS packaging and medical diagnostics or, in combination with cutouts for fan-out, embedding of active and passive components. In addition, metallization processes with good adhesion, excellent electrical properties and high geometric accuracy for glasses are an important step. In the current manuscript, we review the status and discuss our contribution towards achieving industrial readiness for glass in panel- and wafer-level packaging.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"14 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76336447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000314
F. Le, Haibin Chen, Zunyu Guan, F. Fajardo
Most fluxes and their flux residue are corrosive, and their presence on the surface of assemblies may cause reliability concerns due to electrochemical migration. This study firstly refers to the test method IPC-TM-650 2.3.32D and 2.6.15C and the requirements in J-STD-004A to evaluate flux-induced corrosion and the corrosivity of their flux residue. Then thermogravimetric analysis is used to evaluate the flux residue level after soldering under identical conditions. These comparison data can be utilized to compare flux performance of solder pastes. For the cleanliness evaluation after flux cleaning, the qualitative analysis refers to IPC-A-610G and adopts optical inspection to observe the flux cleaning effect. The quantitative analysis refers to IPC-TM-650 2.3.28B ion chromatography test method to analyze the level of ionic species after flux cleaning. In addition to IPC-TM-650 2.3.28B ion chromatography method, the effectiveness of other methods has been well demonstrated to characterize the fluxes and their flux residue in clip bonding assembly.
{"title":"Assessment of Solder Flux Corrosivity and Flux Residue Level in Clip Bonding Assembly","authors":"F. Le, Haibin Chen, Zunyu Guan, F. Fajardo","doi":"10.4071/1085-8024-2021.1.000314","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000314","url":null,"abstract":"\u0000 Most fluxes and their flux residue are corrosive, and their presence on the surface of assemblies may cause reliability concerns due to electrochemical migration. This study firstly refers to the test method IPC-TM-650 2.3.32D and 2.6.15C and the requirements in J-STD-004A to evaluate flux-induced corrosion and the corrosivity of their flux residue. Then thermogravimetric analysis is used to evaluate the flux residue level after soldering under identical conditions. These comparison data can be utilized to compare flux performance of solder pastes. For the cleanliness evaluation after flux cleaning, the qualitative analysis refers to IPC-A-610G and adopts optical inspection to observe the flux cleaning effect. The quantitative analysis refers to IPC-TM-650 2.3.28B ion chromatography test method to analyze the level of ionic species after flux cleaning. In addition to IPC-TM-650 2.3.28B ion chromatography method, the effectiveness of other methods has been well demonstrated to characterize the fluxes and their flux residue in clip bonding assembly.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"43 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80911955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000368
I. Popova, R. Dieckmann, N. Schroeder, G. Gomes, J. Golden
With the rapidly expanding range of design and integration flows required for advanced packaging, both foundries and OSATs alike are evaluating new types of materials for additive manufacturing - this is especially pertinent for both resist materials and galvanic plating baths. This problem is far from new (1), it is a part of the regularly required re-evaluation of process-material interactions (2) for the new packaging integration schemes, driven by changes in design, process flow, and technology requirements. With increasing demands for bath longevity and robustness of plating performance, material vendors are motivated to minimize interactions between the plating bath chemistries and photoresists, defining the plating pattern. In this study, we have evaluated the effect of several factors including - resist type (i.e. positive, negative, general-purpose vs “plating/packaging” type) and process parameters for both resist and bath material (by comparing several resist materials from different manufacturers with varying processing conditions on silicon wafers). We used reverse phase HPLC with UV-detection as a method of choice in this study to compare resist extractables into the galvanic baths. We utilized a copper plating packaging type galvanic bath as a representative bath material. We evaluated semi-quantitatively the extractable via their HPLC signature into the bath to compare resist properties and further attempt to extrapolate resist stability and breakdown magnitude with possible effects on bath life. The utility of the method developed here allows for comparing and quantifying (note - evaluation is semi-quantitative since no standard solutions of leached components exist) extractables via HPLC (high-performance liquid chromatography) allows for a better understanding of resist bath stability “factors”, and can be further expanded into an online method for detecting early signs of bath contamination by a photoresist. It can also be used for aiding lithographers to better pre-assess photoresist capabilities and aid in the material selection for future plating applications.
{"title":"Understanding photoresist - electroplating bath interactions using HPLC methodology","authors":"I. Popova, R. Dieckmann, N. Schroeder, G. Gomes, J. Golden","doi":"10.4071/1085-8024-2021.1.000368","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000368","url":null,"abstract":"\u0000 With the rapidly expanding range of design and integration flows required for advanced packaging, both foundries and OSATs alike are evaluating new types of materials for additive manufacturing - this is especially pertinent for both resist materials and galvanic plating baths. This problem is far from new (1), it is a part of the regularly required re-evaluation of process-material interactions (2) for the new packaging integration schemes, driven by changes in design, process flow, and technology requirements. With increasing demands for bath longevity and robustness of plating performance, material vendors are motivated to minimize interactions between the plating bath chemistries and photoresists, defining the plating pattern. In this study, we have evaluated the effect of several factors including - resist type (i.e. positive, negative, general-purpose vs “plating/packaging” type) and process parameters for both resist and bath material (by comparing several resist materials from different manufacturers with varying processing conditions on silicon wafers). We used reverse phase HPLC with UV-detection as a method of choice in this study to compare resist extractables into the galvanic baths. We utilized a copper plating packaging type galvanic bath as a representative bath material. We evaluated semi-quantitatively the extractable via their HPLC signature into the bath to compare resist properties and further attempt to extrapolate resist stability and breakdown magnitude with possible effects on bath life. The utility of the method developed here allows for comparing and quantifying (note - evaluation is semi-quantitative since no standard solutions of leached components exist) extractables via HPLC (high-performance liquid chromatography) allows for a better understanding of resist bath stability “factors”, and can be further expanded into an online method for detecting early signs of bath contamination by a photoresist. It can also be used for aiding lithographers to better pre-assess photoresist capabilities and aid in the material selection for future plating applications.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74745587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000332
S. Schmitz, N. Araki, M. Eto, Tadashige Yamaguchi, T. Haibara, Takashi Yamada
This article focuses on the analysis of the interface formation of heavy wire bonding contacts. A test methodology is presented which combines the novel BAMFIT (Bondtec Accelerated Mechanical Fatigue Interface Testing) method, the 3D measurement of fracture patterns and the application of adapted evaluation algorithms. Unlike the shear test, which only measures resistance to mechanical deformation by the shear chisel, the test methodology used directly measures the connected area. Precisely knowing the percentage of bonded area allows the user to fine-tune bonding parameters to closely match the material system being used as well as to identify differences in the material behaviour. In order to work out these subtle differences, 4 wire types were investigated, which basically have very similar mechanical properties. Parameter studies using DoE (design-of-experiment) were performed for all wire materials used. In addition to the deformation of the bonding contacts, shear forces, shear strengths and the percentage of bonded interface area were determined. After analyzing the available data and modeling the process with DoE software, process windows were derived for the wire materials. Here, it was shown that accurate knowledge of the connected area – determined by the testing methodology presented in this publication – allows more accurate decision making regarding the wire material to be used. Furthermore, it could be shown where the heavy wire shear test reaches its limits in such investigations.
{"title":"Advanced bonding interface inspection technique for process optimization in heavy wire bonding","authors":"S. Schmitz, N. Araki, M. Eto, Tadashige Yamaguchi, T. Haibara, Takashi Yamada","doi":"10.4071/1085-8024-2021.1.000332","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000332","url":null,"abstract":"\u0000 This article focuses on the analysis of the interface formation of heavy wire bonding contacts. A test methodology is presented which combines the novel BAMFIT (Bondtec Accelerated Mechanical Fatigue Interface Testing) method, the 3D measurement of fracture patterns and the application of adapted evaluation algorithms. Unlike the shear test, which only measures resistance to mechanical deformation by the shear chisel, the test methodology used directly measures the connected area. Precisely knowing the percentage of bonded area allows the user to fine-tune bonding parameters to closely match the material system being used as well as to identify differences in the material behaviour. In order to work out these subtle differences, 4 wire types were investigated, which basically have very similar mechanical properties. Parameter studies using DoE (design-of-experiment) were performed for all wire materials used. In addition to the deformation of the bonding contacts, shear forces, shear strengths and the percentage of bonded interface area were determined. After analyzing the available data and modeling the process with DoE software, process windows were derived for the wire materials. Here, it was shown that accurate knowledge of the connected area – determined by the testing methodology presented in this publication – allows more accurate decision making regarding the wire material to be used. Furthermore, it could be shown where the heavy wire shear test reaches its limits in such investigations.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"18 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87251081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000390
B. Czerny, G. Khatibi
This paper presents case studies on application of accelerated mechanical fatigue testing for evaluation of wire bond interconnects and interfaces in electronic devices. A dedicated experimental set-up is designed to induce fatigue failure in the weak sites of the devices by reproducing the failure modes occurring during operation. Acceleration is achieved by increasing the mechanical testing frequency enabling determination of lifetime curves in a very short time. Exemplary studies on the degradation and fatigue failure of heavy wire bonds typically used in power electronics are presented and advantages and some restrictions of the proposed method are briefly discussed.
{"title":"Highly accelerated lifetime testing in power electronics","authors":"B. Czerny, G. Khatibi","doi":"10.4071/1085-8024-2021.1.000390","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000390","url":null,"abstract":"\u0000 This paper presents case studies on application of accelerated mechanical fatigue testing for evaluation of wire bond interconnects and interfaces in electronic devices. A dedicated experimental set-up is designed to induce fatigue failure in the weak sites of the devices by reproducing the failure modes occurring during operation. Acceleration is achieved by increasing the mechanical testing frequency enabling determination of lifetime curves in a very short time. Exemplary studies on the degradation and fatigue failure of heavy wire bonds typically used in power electronics are presented and advantages and some restrictions of the proposed method are briefly discussed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91536545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000346
Reinhard Schemmel, N. Müller, Ludger Klahold, T. Hemsel, W. Sextro
Ultrasonic heavy wire bonding is a standard process in packaging technologies of power semiconductor modules. Due to increasing demands on reliability of the electrical contacts under high temperature loads, copper wires with significantly better electrical and thermal properties compared to aluminum are used more often nowadays. This results in new challenges in process development due to higher process forces and ultrasonic power; for this purpose, a simulation model has been developed to improve process development. The process model is based on a co-simulation with sub-models for the different physical phenomena. The sub-models are based on parameters, which need to be identified from measurements. This contribution focusses on the identification of the material model. Therefore, a method is presented, which allows for an iterative identification of the stress-strain characteristics from compression tests based on a modified tensile-compression machine. In compression tests under ultrasonic load, the bond wire material behavior under ultrasonic load is investigated to characterize the so-called ultrasonic-softening-effect. The simulation model with identified model parameters is then used to predict main-effects-diagrams for aluminum and copper wire bond processes on DCB. The simulation results are validated by comparison to results from parameter studies of ultrasonic heavy wire bonding experiments.
{"title":"Experimental parameter identification and validation of a process model for ultrasonic heavy wire bonding","authors":"Reinhard Schemmel, N. Müller, Ludger Klahold, T. Hemsel, W. Sextro","doi":"10.4071/1085-8024-2021.1.000346","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000346","url":null,"abstract":"\u0000 Ultrasonic heavy wire bonding is a standard process in packaging technologies of power semiconductor modules. Due to increasing demands on reliability of the electrical contacts under high temperature loads, copper wires with significantly better electrical and thermal properties compared to aluminum are used more often nowadays. This results in new challenges in process development due to higher process forces and ultrasonic power; for this purpose, a simulation model has been developed to improve process development. The process model is based on a co-simulation with sub-models for the different physical phenomena. The sub-models are based on parameters, which need to be identified from measurements. This contribution focusses on the identification of the material model. Therefore, a method is presented, which allows for an iterative identification of the stress-strain characteristics from compression tests based on a modified tensile-compression machine. In compression tests under ultrasonic load, the bond wire material behavior under ultrasonic load is investigated to characterize the so-called ultrasonic-softening-effect. The simulation model with identified model parameters is then used to predict main-effects-diagrams for aluminum and copper wire bond processes on DCB. The simulation results are validated by comparison to results from parameter studies of ultrasonic heavy wire bonding experiments.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"11 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88840608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000201
T. Smith, Bill Rhyne, Christopher Hatfield
This paper presents the development of a substrate/interposer technology that is capable of supporting DC signal line routing down to <1mil trace and space densities, but also supports wideband, high-frequency and industry leading low loss RF routing from to beyond 175GHz. Building off of the proven performance and reliability of the PolyStrata® technology enabled air-coax routing, this paper discusses the development and addition of a redistribution technology that enables multilayer, high density DC signal routing at any point during the PolyStrata® process. This enhances the Polystrata® offering to a truly integrated substrate manufacturing process supporting high density interconnect requirement of flip-chip RF ICs as well as low loss high performance RF routing. The paper describes the design and fabrication of a demonstration part designed to accept a D-Band Flip-Chip RFIC. The chip side interconnects are 50um diameter copper pillar with solder cap, at 100um pitch with over 200 interconnects on a die. Multiple connections were required from 10Ghz to 175GHz as well has 30+ DC signal lines. The design can support this level of interconnect density and act as an interposer for next level interconnect to a printed circuit board. DC lines were routed out to a 400um pitch while RF interconnects can support transitions to micro-strip or strip-line PCB routing technology or waveguide, for easy and low loss interconnect to the next level system. An added benefit of being integrated into the PolyStrata® process is that high-performance passive components can be monolithically integrated into the interposer, and the demonstration vehicle implements a mmWave pass-band filter as well.
{"title":"Ultra wide-band, low Loss RF substrate with high-density DC routing supporting 5G/6G flip-chip RFICs","authors":"T. Smith, Bill Rhyne, Christopher Hatfield","doi":"10.4071/1085-8024-2021.1.000201","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000201","url":null,"abstract":"\u0000 This paper presents the development of a substrate/interposer technology that is capable of supporting DC signal line routing down to <1mil trace and space densities, but also supports wideband, high-frequency and industry leading low loss RF routing from to beyond 175GHz. Building off of the proven performance and reliability of the PolyStrata® technology enabled air-coax routing, this paper discusses the development and addition of a redistribution technology that enables multilayer, high density DC signal routing at any point during the PolyStrata® process. This enhances the Polystrata® offering to a truly integrated substrate manufacturing process supporting high density interconnect requirement of flip-chip RF ICs as well as low loss high performance RF routing.\u0000 The paper describes the design and fabrication of a demonstration part designed to accept a D-Band Flip-Chip RFIC. The chip side interconnects are 50um diameter copper pillar with solder cap, at 100um pitch with over 200 interconnects on a die. Multiple connections were required from 10Ghz to 175GHz as well has 30+ DC signal lines. The design can support this level of interconnect density and act as an interposer for next level interconnect to a printed circuit board. DC lines were routed out to a 400um pitch while RF interconnects can support transitions to micro-strip or strip-line PCB routing technology or waveguide, for easy and low loss interconnect to the next level system. An added benefit of being integrated into the PolyStrata® process is that high-performance passive components can be monolithically integrated into the interposer, and the demonstration vehicle implements a mmWave pass-band filter as well.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"50 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79103709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000286
V. Chia, Tiffany Wilkus, Laarni Huerta, Wendy Rivello, Jennifer Jew, Fuhe Li, H. Gotts, I-Hsiang Hsu, S. Anderson
A goal of advanced packaging design performance is to reduce power and to achieve better control of heat and electromagnetic interference. Materials to achieve efficient packaging include the use of gold (Au) wire, copper (Cu) alloy, gold/silver (Au/Ag) plating, solder, low-k epoxy and dry-film polymers, silicones and polyimides. Material purity verification and contamination control during the production process is a prerequisite to ensure high yields in packaging because getting this wrong means throwing away multiple chips. This paper describes an Analytical Decision Tree to guide methodology selection, reviews contamination troubleshooting methodologies, and case studies to resolve process issues.
{"title":"Contamination Troubleshooting for Microelectronics Packaging","authors":"V. Chia, Tiffany Wilkus, Laarni Huerta, Wendy Rivello, Jennifer Jew, Fuhe Li, H. Gotts, I-Hsiang Hsu, S. Anderson","doi":"10.4071/1085-8024-2021.1.000286","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000286","url":null,"abstract":"\u0000 A goal of advanced packaging design performance is to reduce power and to achieve better control of heat and electromagnetic interference. Materials to achieve efficient packaging include the use of gold (Au) wire, copper (Cu) alloy, gold/silver (Au/Ag) plating, solder, low-k epoxy and dry-film polymers, silicones and polyimides. Material purity verification and contamination control during the production process is a prerequisite to ensure high yields in packaging because getting this wrong means throwing away multiple chips. This paper describes an Analytical Decision Tree to guide methodology selection, reviews contamination troubleshooting methodologies, and case studies to resolve process issues.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"34 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81322114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000108
Ryuji Hirosawa, Junya Kusunoki
In recent years, as electronic devices such as smartphones become more functional, more compact, and lower cost, many semiconductor makers are studying the packages such as WLP (Wafer Level Package) having re-distribution layer (RDL).With the miniaturization and the increase in the number of pins of a semiconductor package, the method of conduction between a semiconductor chip and an external electrode has been changed from wire connection to bump connection and RDL. And the application of a wafer coating material is also required to have higher functions from a buffer coat film to bump protection and an interlayer insulating film for RDL. Further, in recent years, in addition to the purpose of avoiding the performance deterioration of the semiconductor device due to the high-temperature treatment, a package material having low heat resistance is sometimes used in the FOWLP, and therefore, the wafer coating material is required to lower temperature curable. We have developed a PBO that can be cured at low temperature by shortening the distance between hydroxyl group and carbonyl group in the PBO precursor.
{"title":"Latest technology of wafer coating material for advanced packages","authors":"Ryuji Hirosawa, Junya Kusunoki","doi":"10.4071/1085-8024-2021.1.000108","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000108","url":null,"abstract":"\u0000 In recent years, as electronic devices such as smartphones become more functional, more compact, and lower cost, many semiconductor makers are studying the packages such as WLP (Wafer Level Package) having re-distribution layer (RDL).With the miniaturization and the increase in the number of pins of a semiconductor package, the method of conduction between a semiconductor chip and an external electrode has been changed from wire connection to bump connection and RDL. And the application of a wafer coating material is also required to have higher functions from a buffer coat film to bump protection and an interlayer insulating film for RDL. Further, in recent years, in addition to the purpose of avoiding the performance deterioration of the semiconductor device due to the high-temperature treatment, a package material having low heat resistance is sometimes used in the FOWLP, and therefore, the wafer coating material is required to lower temperature curable. We have developed a PBO that can be cured at low temperature by shortening the distance between hydroxyl group and carbonyl group in the PBO precursor.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"34 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88012546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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