Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000381
K. Tsukamoto, Atsunori Kajiki, Y. Kunimoto, M. Mizuno, Manabu Nakamura, S. Nakazawa, Toshinori Koyama
Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.
异构封装是一种先进的封装技术。特别是对于数据中心服务器、高性能计算(HPC)和人工智能(AI)等高端应用，高带宽内存(HBM)集成是关键，也是迫切需要的。众所周知，2.5D硅中间层封装是HBM互连的扩展解决方案。然而，我们开发了2.1D高密度有机封装，称为i-THOP®(集成薄膜高密度有机封装)，以利用有机溶液的优势。此外，我们现在正专注于2.3D i-THOP®，以在制造中获得更多的好处。2.3 3d结构由两个衬底组成。一个是薄i-THOP®中间层，另一个是传统的积层(BU)基板。这两种衬底被组合为放置在构筑衬底上的中间物。本文对2.3 3d i-THOP®的电学特性进行了研究，从信号和功率完整性的角度证实了2.3 3d结构有机封装的可能性。首先，模拟了两个器件之间的信号完整性，比较了i-THOP®和2.5D硅中间层之间的差异。其次，模拟了芯片与衬底垂直互连中的信号完整性，比较了2.1D、2.3D i-THOP®和2.5D硅中间层的信号完整性。最后，从电力输送的角度，比较了2.1D和2.3D i-THOP®的配电网络(PDN)阻抗。
{"title":"Analysis on Signal and Power Integrity of 2.3D Structure Organic Package","authors":"K. Tsukamoto, Atsunori Kajiki, Y. Kunimoto, M. Mizuno, Manabu Nakamura, S. Nakazawa, Toshinori Koyama","doi":"10.4071/2380-4505-2019.1.000381","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000381","url":null,"abstract":"\u0000 Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75649626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000152
Roman Ostholt, R. Santos, N. Ambrosius, D. Dunker, J. Delrue
The objective of this paper is to demonstrate the feasibility of glass mounting substrates made by Laser Induced Deept Etching (LIDE) technology, which include newly developed passive die alignment structures. The aim of these structures is to compensate for potential die misalignments and die shift issues which become severe when moving to panel level fan-out packaging. The passive alignment structures are located at two adjacent edges of the rectangular cavity and are created in the same process step as the open cavities. The filigree spring-like alignment structures benefit from being processed in a crack- and stress-free manner. Although the spring elements have a minimal dimension of less than 100 μm, these structures show an outstanding break strength while deformed when active dies are placed in the mounting cavity. Depending on the design, the spring elements can have a stroke of several tenths of micrometer which enable the compensation of rather large die displacements. Here, we present examples for LIDE-processed mounting glass substrates with the described features. The performance of the proposed design and method was evaluated with a die accuracy study. Test dies with alignment marks were placed in the cavities and measured relatively to alignments marks on the mounting glass substrate. The Fan-Out packaging concept based on the research shown here combines several advantages: due to the relatively high Young's modulus of the glass, the reconstituted wafer shows less warpage than in the state-of-art; while the passive alignment structures reduce the die shift to a minimum (depending on dicing accuracies and through package vias for package-on-package or antenna-in-package application), and can be readily integrated.
{"title":"Passive Die Alignment in Glass Embedded Fan-Out Packaging","authors":"Roman Ostholt, R. Santos, N. Ambrosius, D. Dunker, J. Delrue","doi":"10.4071/2380-4505-2019.1.000152","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000152","url":null,"abstract":"\u0000 The objective of this paper is to demonstrate the feasibility of glass mounting substrates made by Laser Induced Deept Etching (LIDE) technology, which include newly developed passive die alignment structures. The aim of these structures is to compensate for potential die misalignments and die shift issues which become severe when moving to panel level fan-out packaging.\u0000 The passive alignment structures are located at two adjacent edges of the rectangular cavity and are created in the same process step as the open cavities. The filigree spring-like alignment structures benefit from being processed in a crack- and stress-free manner. Although the spring elements have a minimal dimension of less than 100 μm, these structures show an outstanding break strength while deformed when active dies are placed in the mounting cavity. Depending on the design, the spring elements can have a stroke of several tenths of micrometer which enable the compensation of rather large die displacements.\u0000 Here, we present examples for LIDE-processed mounting glass substrates with the described features. The performance of the proposed design and method was evaluated with a die accuracy study. Test dies with alignment marks were placed in the cavities and measured relatively to alignments marks on the mounting glass substrate. The Fan-Out packaging concept based on the research shown here combines several advantages: due to the relatively high Young's modulus of the glass, the reconstituted wafer shows less warpage than in the state-of-art; while the passive alignment structures reduce the die shift to a minimum (depending on dicing accuracies and through package vias for package-on-package or antenna-in-package application), and can be readily integrated.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84213211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000115
A. Mackie, Hyoryoon Jo, S. Lim
Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.
{"title":"Flip-Chip Flux Evolution","authors":"A. Mackie, Hyoryoon Jo, S. Lim","doi":"10.4071/2380-4505-2019.1.000115","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000115","url":null,"abstract":"\u0000 Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage.\u0000 This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"35 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80259889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.
{"title":"Control of Solder Bump Growing Morphology in Lead Free Plating","authors":"Berdy Weng, Wei-Wei Liu, Lu-Ming Lai, Kuang-Hsiung Chen","doi":"10.4071/2380-4505-2019.1.000488","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000488","url":null,"abstract":"\u0000 Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"36 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74646375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000127
R. Mao, Fen Chen, N. Lee
A series of flux systems have been developed which would result in a reduced viscosity after reflow. This enables a high viscosity, high tack flux to be used to secure components at the component placement and reflow stage, but ends up with a low viscosity flux residue after reflow, thus facilitating the flux residue to be cleaned. A technique for forming such special fluxes is to establish a temporary association force within the materials themselves, such as an acid-base association. This kind of association force can increase the apparent molecular weight and cause material viscosity to increase. After a heating process, one of the critical ingredients was evaporated, thus eliminating the association force, causing a decrease in the apparent molecular weight, and consequently a decrease in viscosity or an increase in mobility. The evaporation of one ingredient can be the result of one ingredient having a lower boiling point, or the decomposition of one ingredient during heating. A strong association force is desired to allow this acid-base combination approach to work. In this work, the volatile ingredient approach was less effective than a decomposable ingredient approach, presumably due to the formation of a bigger association cluster from the decomposable ingredient. Accordingly, the decomposable ingredient was the best approach to lower flux viscosity after reflow.
{"title":"FLUXES WITH DECREASED VISCOSITY AFTER REFLOW FOR FLIP-CHIP AND SIP ASSEMBLY","authors":"R. Mao, Fen Chen, N. Lee","doi":"10.4071/2380-4505-2019.1.000127","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000127","url":null,"abstract":"\u0000 A series of flux systems have been developed which would result in a reduced viscosity after reflow. This enables a high viscosity, high tack flux to be used to secure components at the component placement and reflow stage, but ends up with a low viscosity flux residue after reflow, thus facilitating the flux residue to be cleaned. A technique for forming such special fluxes is to establish a temporary association force within the materials themselves, such as an acid-base association. This kind of association force can increase the apparent molecular weight and cause material viscosity to increase. After a heating process, one of the critical ingredients was evaporated, thus eliminating the association force, causing a decrease in the apparent molecular weight, and consequently a decrease in viscosity or an increase in mobility. The evaporation of one ingredient can be the result of one ingredient having a lower boiling point, or the decomposition of one ingredient during heating. A strong association force is desired to allow this acid-base combination approach to work. In this work, the volatile ingredient approach was less effective than a decomposable ingredient approach, presumably due to the formation of a bigger association cluster from the decomposable ingredient. Accordingly, the decomposable ingredient was the best approach to lower flux viscosity after reflow.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"54 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79365252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000470
Aparna Aravelli, Michael Thompson, D. McDaniel, Mathew Krutch, M. McNEILLY, K. Imrich, B. Wiersma
Nuclear waste sites across the United States and other countries store, transfer and vitrify nuclear waste. These sites often require transfer pipelines for high and low level radioactive wastes in the form of solids/slurries, fluids including chemicals. Since, these pipelines deal with harmful nuclear wastes, structural health monitoring is of utmost importance. Pipelines are continuously monitored to enhance the safety of the people and environment around the facilities. Monitoring may involve leak, crack detection and wear (in the form of corrosion or thinning). Current research builds on author's previous work on sensors for erosion and thermal monitoring in pipes and plates [1, 2, and 3]. Present work involves a) validation and monitoring of a novel advanced Fiber Optic Sensor System to detect cracks and leaks in carbon steel pipes and b) the use of Ultrasonic (UT) sensors to detect thinning in pipe sections due to erosion-corrosion using small coupons. The fiber optic sensors developed by CEL [4], are used in conducting engineering scale testing on an in-house designed and assembled erosion pipe flow loop. The loop consists of 2 and 3 inch straight and elbow sections of carbon steel replicating the pipelines at the sites. Three fiber optic sensors are placed at critical locations around the loop. The equipment also includes a communication box and a laptop device for data acquisition. The sensor system uses a combination of fiber optic and acoustic technologies to accurately identify the location of a pipeline leak or crack. Sensors capture the changes in pressure caused by the fluid/slurry flowing through the loop. A “zone” is defined as the distance between any two sensor points. When any two sensors simultaneously detect a leak, a determination can be made as to how far from each sensor the activity is occurring and “zero in” on the event. A number of zones may be linked together to manage vast expanses of pipeline. Sensors provide instantaneous event data to the hardware (the interrogator), and the interrogator may be located great distances from the actual pipeline in secure, environmentally protected areas. Multiple Interrogators may be linked together that are simultaneously streaming real-time data to the command and control software. Event notifications may then be managed from the customer's control room, or immediately “pushed” to a variety of mobile devices to alert personnel of the situation [5]. Additionally, Ultrasonic (UT) sensors are used for thickness measurements in pipes. The objective is to measure the wear in pipelines due to erosion-corrosion using small scale erosion coupons. These erosion coupons are made of carbon steel with ½ inch in diameter and 1 inch height. The method involves insertion of the coupons into holes drilled in the pipe sections of the erosion loop. This process ensures that the coupons are in contact with the flow stream and hence eroded in a minute scale over a period of time. The coupons have
{"title":"Advanced Fiber Optic and Ultrasonic Sensor Systems for Structural Health Monitoring of Pipes in Nuclear Waste Sites","authors":"Aparna Aravelli, Michael Thompson, D. McDaniel, Mathew Krutch, M. McNEILLY, K. Imrich, B. Wiersma","doi":"10.4071/2380-4505-2019.1.000470","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000470","url":null,"abstract":"\u0000 Nuclear waste sites across the United States and other countries store, transfer and vitrify nuclear waste. These sites often require transfer pipelines for high and low level radioactive wastes in the form of solids/slurries, fluids including chemicals. Since, these pipelines deal with harmful nuclear wastes, structural health monitoring is of utmost importance. Pipelines are continuously monitored to enhance the safety of the people and environment around the facilities. Monitoring may involve leak, crack detection and wear (in the form of corrosion or thinning). Current research builds on author's previous work on sensors for erosion and thermal monitoring in pipes and plates [1, 2, and 3]. Present work involves a) validation and monitoring of a novel advanced Fiber Optic Sensor System to detect cracks and leaks in carbon steel pipes and b) the use of Ultrasonic (UT) sensors to detect thinning in pipe sections due to erosion-corrosion using small coupons. The fiber optic sensors developed by CEL [4], are used in conducting engineering scale testing on an in-house designed and assembled erosion pipe flow loop. The loop consists of 2 and 3 inch straight and elbow sections of carbon steel replicating the pipelines at the sites. Three fiber optic sensors are placed at critical locations around the loop. The equipment also includes a communication box and a laptop device for data acquisition. The sensor system uses a combination of fiber optic and acoustic technologies to accurately identify the location of a pipeline leak or crack. Sensors capture the changes in pressure caused by the fluid/slurry flowing through the loop. A “zone” is defined as the distance between any two sensor points. When any two sensors simultaneously detect a leak, a determination can be made as to how far from each sensor the activity is occurring and “zero in” on the event. A number of zones may be linked together to manage vast expanses of pipeline. Sensors provide instantaneous event data to the hardware (the interrogator), and the interrogator may be located great distances from the actual pipeline in secure, environmentally protected areas. Multiple Interrogators may be linked together that are simultaneously streaming real-time data to the command and control software. Event notifications may then be managed from the customer's control room, or immediately “pushed” to a variety of mobile devices to alert personnel of the situation [5]. Additionally, Ultrasonic (UT) sensors are used for thickness measurements in pipes. The objective is to measure the wear in pipelines due to erosion-corrosion using small scale erosion coupons. These erosion coupons are made of carbon steel with ½ inch in diameter and 1 inch height. The method involves insertion of the coupons into holes drilled in the pipe sections of the erosion loop. This process ensures that the coupons are in contact with the flow stream and hence eroded in a minute scale over a period of time. The coupons have ","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"14 3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72986286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000103
T. Hisada, T. Aoki, Eiji Nakamura, S. Kohara, H. Mori
IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.
{"title":"Flip Chip Joining with Quaternary Low Melting Temperature Solder Bump Fabricated with Injection Molded Solder","authors":"T. Hisada, T. Aoki, Eiji Nakamura, S. Kohara, H. Mori","doi":"10.4071/2380-4505-2019.1.000103","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000103","url":null,"abstract":"\u0000 IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"30 2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73188924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000344
Evan A. Hueners, Richard D. Hueners, Anthony D. F. O' Sullivan, M. Zin
Energy & Eco-Sustainability using Pressureless Silver Sintering for RF Power Electronics A virtually void free die attach was successfully achieved using a fixed but critical volume of Ag sinter paste by a process of pressureless sintering on a multi-axis cartesian style bonder, retro-fitted with with a high-speed jetting dispenser. While this process potentially offered an ideal combination of cost-effectiveness, control and speed, it required the development of additional software protocols to secure the level of performance demanded of the dispenser to meet exacting technical requirements. This proprietary adaptation we term “Fixed BLT” software, and over five test pieces we were consistently able to deliver a fixed height bond-line of circa 70% of bond height, translating as 50 um before sinter and 30 um after. In each case the result was a virtually bond free void secured in a timely, repeatable, commercially effective manner. The absence of voids was verified through industry standard non-destructive analysis utilizing confocal scanning acoustic microscopy (CSAM).
{"title":"Energy and Eco-Sustainability using Pressure-less Silver Sintering for RF Power Electronics","authors":"Evan A. Hueners, Richard D. Hueners, Anthony D. F. O' Sullivan, M. Zin","doi":"10.4071/2380-4505-2019.1.000344","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000344","url":null,"abstract":"\u0000 Energy & Eco-Sustainability using Pressureless Silver Sintering for RF Power Electronics\u0000 A virtually void free die attach was successfully achieved using a fixed but critical volume of Ag sinter paste by a process of pressureless sintering on a multi-axis cartesian style bonder, retro-fitted with with a high-speed jetting dispenser. While this process potentially offered an ideal combination of cost-effectiveness, control and speed, it required the development of additional software protocols to secure the level of performance demanded of the dispenser to meet exacting technical requirements. This proprietary adaptation we term “Fixed BLT” software, and over five test pieces we were consistently able to deliver a fixed height bond-line of circa 70% of bond height, translating as 50 um before sinter and 30 um after. In each case the result was a virtually bond free void secured in a timely, repeatable, commercially effective manner. The absence of voids was verified through industry standard non-destructive analysis utilizing confocal scanning acoustic microscopy (CSAM).","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"29 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88108420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000530
Jessica Richter, A. Steenmann, Benjamin Schellscheidt, T. Licht
In this paper, we present a conceptual design of an on-chip solder stack to connect silicon devices faster and more reliable. Almost all electronic devices rely on solder layers to provide electrical, mechanical, and thermal connections between components. We improve the solder connection with industry-standard solder parameters of 300°C and some minutes of soldering time. An ideal solder connection is composed of intermetallic phases (IMPs) at the interfaces between device and solder, and substrate and solder. Typically, a thin region of Sn-based solder remains between the two IMP layers at the interfaces. IMPs of copper (Cu) and tin (Sn) are Cu6Sn5 and Cu3Sn. The formation of IMPs is decisive for a good mechanical connection because of their high melting point and mechanical stability. To achieve these requirements, we implement the solder stack as a transient liquid phase bonding (TLPB) system. To realize durable interconnections, we use the diffusion of a high-melting first component in a second component, which is liquid at solder process temperature. Ongoing diffusion leads to the formation of IMPs with a melting point above process temperature, resulting in a solidification of the connection at constant temperature. By this isothermal solidification, the solder connection becomes more durable against mechanical and thermal load and is usable at temperatures exceeding 300°C.
{"title":"On-Chip Diffusion Bonding creates Stable Interconnections Usable at Temperatures over 300°C","authors":"Jessica Richter, A. Steenmann, Benjamin Schellscheidt, T. Licht","doi":"10.4071/2380-4505-2019.1.000530","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000530","url":null,"abstract":"\u0000 In this paper, we present a conceptual design of an on-chip solder stack to connect silicon devices faster and more reliable. Almost all electronic devices rely on solder layers to provide electrical, mechanical, and thermal connections between components. We improve the solder connection with industry-standard solder parameters of 300°C and some minutes of soldering time.\u0000 An ideal solder connection is composed of intermetallic phases (IMPs) at the interfaces between device and solder, and substrate and solder. Typically, a thin region of Sn-based solder remains between the two IMP layers at the interfaces. IMPs of copper (Cu) and tin (Sn) are Cu6Sn5 and Cu3Sn. The formation of IMPs is decisive for a good mechanical connection because of their high melting point and mechanical stability. To achieve these requirements, we implement the solder stack as a transient liquid phase bonding (TLPB) system. To realize durable interconnections, we use the diffusion of a high-melting first component in a second component, which is liquid at solder process temperature. Ongoing diffusion leads to the formation of IMPs with a melting point above process temperature, resulting in a solidification of the connection at constant temperature. By this isothermal solidification, the solder connection becomes more durable against mechanical and thermal load and is usable at temperatures exceeding 300°C.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"20 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85470285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000444
D. Alliata, N. Anderson, M. Durand de Gevigney, I. Bergoend, P. Gastaldo
Process control solutions to secure the High-Volume Manufacturing of Gallium Nitride (GaN) devices for power applications are a must today. Unity recently developed and introduced on the market a total control solution that address both defectivity and metrology needs of GaN industry. Proprietary technologies like Phase Shift Deflectometry, darkfield inspection, confocal chromatic imaging and infrared interferometry are here explored to detect killer defects potentially affecting the gallium nitride wafer. More in detail, we characterized Gallium nitride on Silicon substrate before and after the fabrication of the final device and demonstrated how the fabrication process can be optimized.
{"title":"How to secure the fabrication of Gallium Nitride on Si wafers","authors":"D. Alliata, N. Anderson, M. Durand de Gevigney, I. Bergoend, P. Gastaldo","doi":"10.4071/2380-4505-2019.1.000444","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000444","url":null,"abstract":"\u0000 Process control solutions to secure the High-Volume Manufacturing of Gallium Nitride (GaN) devices for power applications are a must today. Unity recently developed and introduced on the market a total control solution that address both defectivity and metrology needs of GaN industry. Proprietary technologies like Phase Shift Deflectometry, darkfield inspection, confocal chromatic imaging and infrared interferometry are here explored to detect killer defects potentially affecting the gallium nitride wafer. More in detail, we characterized Gallium nitride on Silicon substrate before and after the fabrication of the final device and demonstrated how the fabrication process can be optimized.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"52 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91515654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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