Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000568
Jonas Strobelt, J. Bauer, M. Dreissigacker, O. Hoelck, T. Braun, K. Becker, M. Schneider-Ramelow, K. Lang
In microelectronic packaging, encapsulation by compression and transfer molding is a crucial process block to ensure device reliability. Material properties of encapsulants, highly filled systems of reactive epoxy molding compounds (EMC), strongly depend on process conditions in a complex manner and vary over time. Shear-thinning behavior, as well as time- and temperature-dependent conversion strongly impact the viscosity of the polymer melt. In all fields of application, such as automotive or IoT, demands towards miniaturization, lifetime and environmental conditions increase. Thus, detailed understanding of the complex material behavior is of vital importance. Typically, shear-thinning behavior of polymer melts is characterized using a conventional rheometer in oscillation mode under varying shear-rates and temperatures. Limitations of this approach are, that measurements at process temperature typically cannot be performed due to the high reactivity of the encapsulant at these temperatures (e.g. 175 °C for transfer molding). Therefore extrapolation to the correct temperature range is required. Furthermore, measurements in oscillation mode cannot necessarily be transferred to real process conditions, where a continuous flow is present. To overcome these limitations the inline viscometer can be used, a specially designed measurement tool for a transfer molding machine developed by Fico/Besi. The polymer melt is pressed through a narrow slit under known volumetric flow at process temperature. By measuring the pressure difference before and after the slit, the viscosity can be calculated. In order to better understand and also predict material behavior, inline viscosimetry is combined with rheometer measurements. This allows to maintain the advantages of conventional rheometry regarding material consumption and large shear-rate measuring range. At the same time, the inline approach provides relevant data under process conditions. The synthesis of both approaches yields a correction of the rheometer measurements, ultimately improving viscosity modeling and being an improved basis for process simulation.
{"title":"COMBINING ADVANTAGES OF RHEOMETRY AND INLINE VISCOMETRY FOR IMPROVED VISCOSITY MODELING","authors":"Jonas Strobelt, J. Bauer, M. Dreissigacker, O. Hoelck, T. Braun, K. Becker, M. Schneider-Ramelow, K. Lang","doi":"10.4071/2380-4505-2019.1.000568","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000568","url":null,"abstract":"\u0000 In microelectronic packaging, encapsulation by compression and transfer molding is a crucial process block to ensure device reliability. Material properties of encapsulants, highly filled systems of reactive epoxy molding compounds (EMC), strongly depend on process conditions in a complex manner and vary over time. Shear-thinning behavior, as well as time- and temperature-dependent conversion strongly impact the viscosity of the polymer melt. In all fields of application, such as automotive or IoT, demands towards miniaturization, lifetime and environmental conditions increase. Thus, detailed understanding of the complex material behavior is of vital importance.\u0000 Typically, shear-thinning behavior of polymer melts is characterized using a conventional rheometer in oscillation mode under varying shear-rates and temperatures. Limitations of this approach are, that measurements at process temperature typically cannot be performed due to the high reactivity of the encapsulant at these temperatures (e.g. 175 °C for transfer molding). Therefore extrapolation to the correct temperature range is required. Furthermore, measurements in oscillation mode cannot necessarily be transferred to real process conditions, where a continuous flow is present.\u0000 To overcome these limitations the inline viscometer can be used, a specially designed measurement tool for a transfer molding machine developed by Fico/Besi. The polymer melt is pressed through a narrow slit under known volumetric flow at process temperature. By measuring the pressure difference before and after the slit, the viscosity can be calculated.\u0000 In order to better understand and also predict material behavior, inline viscosimetry is combined with rheometer measurements. This allows to maintain the advantages of conventional rheometry regarding material consumption and large shear-rate measuring range. At the same time, the inline approach provides relevant data under process conditions. The synthesis of both approaches yields a correction of the rheometer measurements, ultimately improving viscosity modeling and being an improved basis for process simulation.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86871510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000373
Stephanie Edwards, R. Persons, S. Feltham, Jeff Howerton, Geoffrey A. Lott, D. Macko
Thick film customers who require fine line resolution for their circuitry typically utilize wet chemical etching as a means to reduce conductor's lines and spaces when fine line definition cannot be reliably attained with screen printing alone. Wet chemical etching typically has the means to reduce conductor line widths from a printed definition of 3 mil (75 μm) to as low as 1 mil (25 μm) lines and spaces. The process of performing this chemical etching is time consuming and costly when factoring in the necessary process limitations. With the issues presented by wet chemical etching, thick film customers are presented with a high process cost, yield loss due to the imaging process, and costly wastewater/environmental treatment regulations. Therefore, laser etching will be presented as an alternative method to wet chemical etching for various thick film conductor products. For many years, specialized gold formulations have been etched using typical wet chemical etching processes. Standard and less costly conductor alloys that typically would not be suitable for wet chemical etching will be explored, possibly opening the doors for a wide variety of different applications which would benefit from utilizing this laser etching method. By being able to utilize different conductor alloys (Ag, Cu, etc.), laser etching offers alternative solutions for some of these applications with the added benefit of improved cost and increased throughput. As an example, wet chemical processing of silver conductors has proven to be very challenging in some cases due to the metal form-factor and specialized glasses required. By having the option of laser ablating the silver, a potentially advantageous and cost-effective option would now be possible. Taking into account that laser etching of thick film conductors on ceramic is a relatively new method, this paper will concentrate on some of the opportunities/advantages it can offer. It will illustrate the boundaries of laser etching and how it compares to wet chemical etching while determining/comparing the impact on several properties including adhesion, signal propagation, line definition, and other important defining characteristics of the fired film in the final application.
对于需要细线分辨率的厚膜客户，当仅通过丝网印刷无法可靠地获得细线清晰度时，通常使用湿化学蚀刻作为减少导体线路和空间的手段。湿化学蚀刻通常具有将导体线宽度从印刷定义的3 mil (75 μm)减少到低至1 mil (25 μm)的线和空间的方法。当考虑到必要的工艺限制时，执行这种化学蚀刻的过程是耗时和昂贵的。由于湿法化学蚀刻所带来的问题，厚膜客户面临着高工艺成本、成像过程造成的产量损失，以及昂贵的废水/环境处理法规。因此，激光刻蚀将成为各种厚膜导体产品湿法化学刻蚀的替代方法。多年来，专门的金配方已经蚀刻使用典型的湿化学蚀刻工艺。将探索通常不适合湿化学蚀刻的标准和成本较低的导体合金，可能为各种不同的应用打开大门，这些应用将受益于利用这种激光蚀刻方法。通过能够利用不同的导体合金(Ag, Cu等)，激光蚀刻为其中一些应用提供了替代解决方案，具有降低成本和提高吞吐量的额外好处。例如，由于金属形状因素和需要专用玻璃，在某些情况下，银导体的湿化学处理已被证明是非常具有挑战性的。通过选择激光烧蚀银，一个潜在的优势和成本效益的选择现在是可能的。考虑到陶瓷上厚膜导体的激光蚀刻是一种相对较新的方法，本文将集中讨论它可以提供的一些机会/优势。它将说明激光蚀刻的边界，以及它与湿化学蚀刻的比较，同时确定/比较对几个特性的影响，包括附着力，信号传播，线条定义，以及最终应用中烧制膜的其他重要定义特性。
{"title":"Laser Etching of Gold Conductors for RF Applications","authors":"Stephanie Edwards, R. Persons, S. Feltham, Jeff Howerton, Geoffrey A. Lott, D. Macko","doi":"10.4071/2380-4505-2019.1.000373","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000373","url":null,"abstract":"\u0000 Thick film customers who require fine line resolution for their circuitry typically utilize wet chemical etching as a means to reduce conductor's lines and spaces when fine line definition cannot be reliably attained with screen printing alone. Wet chemical etching typically has the means to reduce conductor line widths from a printed definition of 3 mil (75 μm) to as low as 1 mil (25 μm) lines and spaces. The process of performing this chemical etching is time consuming and costly when factoring in the necessary process limitations.\u0000 With the issues presented by wet chemical etching, thick film customers are presented with a high process cost, yield loss due to the imaging process, and costly wastewater/environmental treatment regulations. Therefore, laser etching will be presented as an alternative method to wet chemical etching for various thick film conductor products.\u0000 For many years, specialized gold formulations have been etched using typical wet chemical etching processes. Standard and less costly conductor alloys that typically would not be suitable for wet chemical etching will be explored, possibly opening the doors for a wide variety of different applications which would benefit from utilizing this laser etching method. By being able to utilize different conductor alloys (Ag, Cu, etc.), laser etching offers alternative solutions for some of these applications with the added benefit of improved cost and increased throughput. As an example, wet chemical processing of silver conductors has proven to be very challenging in some cases due to the metal form-factor and specialized glasses required. By having the option of laser ablating the silver, a potentially advantageous and cost-effective option would now be possible.\u0000 Taking into account that laser etching of thick film conductors on ceramic is a relatively new method, this paper will concentrate on some of the opportunities/advantages it can offer. It will illustrate the boundaries of laser etching and how it compares to wet chemical etching while determining/comparing the impact on several properties including adhesion, signal propagation, line definition, and other important defining characteristics of the fired film in the final application.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"38 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79647706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000223
S. Bulumulla, K. Ramachandran
Ceramic substrates have traditionally been used in RF and microwave packaging applications because of the electrical properties at high frequencies. However, there is significant interest in using organic laminates due to its tighter wiring ground rules for high density packaging and lower cost of fabrication. The high frequency performance of interconnection from die to PCB using an organic packaging substrate has not yet been studied in detail. In this work, the interconnect performance of die to organic laminate to PCB up to 50 GHz was modeled and characterized using a test vehicle assembly. The test vehicle was specifically designed with test pads to characterize the interconnect performance at multiple levels of interconnection. A comparison study using a ceramic package substrate was also carried out. The modeling and hardware testing results from this study showed −3dB bandwidth of more than 50GHz for printed circuit board (PCB) to organic laminate and a bandwidth of 40GHz for the die to organic laminate to PCB interconnection. The results from this study showed that the organic laminate demonstrated a high frequency performance comparable to that of the ceramic substrate, which makes it suitable as a packaging substrate material for high frequency applications.
{"title":"Evaluation of die to organic laminate to PCB interconnects up to 50GHz","authors":"S. Bulumulla, K. Ramachandran","doi":"10.4071/2380-4505-2019.1.000223","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000223","url":null,"abstract":"\u0000 Ceramic substrates have traditionally been used in RF and microwave packaging applications because of the electrical properties at high frequencies. However, there is significant interest in using organic laminates due to its tighter wiring ground rules for high density packaging and lower cost of fabrication. The high frequency performance of interconnection from die to PCB using an organic packaging substrate has not yet been studied in detail. In this work, the interconnect performance of die to organic laminate to PCB up to 50 GHz was modeled and characterized using a test vehicle assembly. The test vehicle was specifically designed with test pads to characterize the interconnect performance at multiple levels of interconnection. A comparison study using a ceramic package substrate was also carried out. The modeling and hardware testing results from this study showed −3dB bandwidth of more than 50GHz for printed circuit board (PCB) to organic laminate and a bandwidth of 40GHz for the die to organic laminate to PCB interconnection. The results from this study showed that the organic laminate demonstrated a high frequency performance comparable to that of the ceramic substrate, which makes it suitable as a packaging substrate material for high frequency applications.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"11 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88731498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000100
B. Rosario, J. Holyoak, Mohsen Haji-Rahim, Gene Lambird, Y. Wang, Kendra Lyons, T. Johnson, P. Makowenskyj, Brian T. Myers, S. Pan
Cu pillar flip-chip die technology has proved reliable and is widely used in chip-to-package mobile module products. There was a time when customers considered 500ppm (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50ppm. This high customer expectation drove this in-depth research and problem solve. Our main work includes: 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE) and ultimately improved yield.
{"title":"Study to Lower Cu Pillar Flip-Chip Failure Rate","authors":"B. Rosario, J. Holyoak, Mohsen Haji-Rahim, Gene Lambird, Y. Wang, Kendra Lyons, T. Johnson, P. Makowenskyj, Brian T. Myers, S. Pan","doi":"10.4071/2380-4505-2019.1.000100","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000100","url":null,"abstract":"\u0000 Cu pillar flip-chip die technology has proved reliable and is widely used in chip-to-package mobile module products. There was a time when customers considered 500ppm (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50ppm. This high customer expectation drove this in-depth research and problem solve. Our main work includes: 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE) and ultimately improved yield.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"48 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79555078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000169
C. Klewer, F. Kuechenmeister, J. Paul, D. Breuer, B. Boehme, J. Cho, S. Capecchi, Michael Thiele
This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.
{"title":"Package Qualification Envelope for 22FDX® Technology","authors":"C. Klewer, F. Kuechenmeister, J. Paul, D. Breuer, B. Boehme, J. Cho, S. Capecchi, Michael Thiele","doi":"10.4071/2380-4505-2019.1.000169","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000169","url":null,"abstract":"\u0000 This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV.\u0000 Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91310549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000183
Riya Paul, A. Deshpande, F. Luo
The device within a power electronics module package will fail if the maximum junction temperature is not within the device's permissible maximum temperature rating specified by the manufacturer. Modern electronic miniaturization demands multi-chip module (MCM) packaging providing different semiconductor technology integration, reduced number of component interconnects, and lower power supply. But the huge amount of heat generated by each chip produces thermal coupling among devices, leading to an increase in the junction temperature. The power device specifications in the datasheet assume the devices being mounted on a suitable heatsink. Wide bandgap (WBG) devices like silicon carbide (SiC) devices can generally sustain a maximum junction temperature of about 175 °C – 200 °C. The junction temperature of the WBG devices becomes severe in a high-density high-power module. This highlights the need for a thermal management system to limit the maximum junction temperature within the device's permissible range. As a result, the power module needs to be connected to a heatsink to effectively increase the surface area of the heat dissipation junctions. A high conductivity material based heatsink extracts heat effectively from the module as the thermal resistance value remains low. In this paper, preliminary thermal analysis is done for a high density high-power module where the high in-plane thermal conductivity of thermal pyrolytic graphite (TPG) is exploited in substrate as well as heatsink designs. TPG brings down the junction temperature to a considerably lower level, leading to a safer power module functioning. This paper focuses on the design and proper alignment of the substrate and heatsink with respect to the module layout so that maximum junction temperature is reduced by proper heat extraction far below the operating temperature of the devices and also extent of reduction of the thermal coupling among the power devices placed next to each other on the same plane within the power module.
{"title":"Thermal Decoupling in Power Electronics Modules Using Thermal Pyrolytic Graphite","authors":"Riya Paul, A. Deshpande, F. Luo","doi":"10.4071/2380-4505-2019.1.000183","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000183","url":null,"abstract":"\u0000 The device within a power electronics module package will fail if the maximum junction temperature is not within the device's permissible maximum temperature rating specified by the manufacturer. Modern electronic miniaturization demands multi-chip module (MCM) packaging providing different semiconductor technology integration, reduced number of component interconnects, and lower power supply. But the huge amount of heat generated by each chip produces thermal coupling among devices, leading to an increase in the junction temperature. The power device specifications in the datasheet assume the devices being mounted on a suitable heatsink. Wide bandgap (WBG) devices like silicon carbide (SiC) devices can generally sustain a maximum junction temperature of about 175 °C – 200 °C. The junction temperature of the WBG devices becomes severe in a high-density high-power module. This highlights the need for a thermal management system to limit the maximum junction temperature within the device's permissible range. As a result, the power module needs to be connected to a heatsink to effectively increase the surface area of the heat dissipation junctions. A high conductivity material based heatsink extracts heat effectively from the module as the thermal resistance value remains low. In this paper, preliminary thermal analysis is done for a high density high-power module where the high in-plane thermal conductivity of thermal pyrolytic graphite (TPG) is exploited in substrate as well as heatsink designs. TPG brings down the junction temperature to a considerably lower level, leading to a safer power module functioning. This paper focuses on the design and proper alignment of the substrate and heatsink with respect to the module layout so that maximum junction temperature is reduced by proper heat extraction far below the operating temperature of the devices and also extent of reduction of the thermal coupling among the power devices placed next to each other on the same plane within the power module.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"117 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89677412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000216
Chien Chun-Hsien, Chien-Chou Chen, Wen-Liang Yeh, Wei Lin, Wu Cheng-Hui, Chen Fu-yang, Yi-Cheng Lin, Po-Chiang Wang, J. Li, Bo Cheng Lin, Yu-Hua Chen, T. Tseng
In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.
1965年，英特尔的联合创始人戈登·e·摩尔(Gordon E. Moore)表示，芯片上的晶体管数量每18个月就会翻一番，他的理论被称为摩尔定律。50多年来，该定律一直是芯片设计的指导原则。集成电路代工厂的技术规模正在迅速扩大。例如，台积电宣布其5nm翅片场效应晶体管(FinFET)工艺技术针对移动和高性能计算应用进行了优化。该项目计划于2019年下半年开始风险生产纵观半导体供应链，包括IC代工、晶圆碰撞、IC载体、PCB(印刷电路板)和OSAT(海外组装和测试)等，由于传统产业的诸多原因，IC载体和PCB技术的尺寸缩放远远落后于IC代工。在下一代互连中，业界需要各种各样的突破方法来扩大通带线的规模。传统的有机衬底在制造和高密度I/ o中面临许多翘曲，表面粗糙度和材料尺寸稳定性问题，具有非常精细的线互连。为了突破这些挑战，对玻璃载体材料、新型光成像介质(PID)和先进设备进行了细线和细孔互连的评价。在本文中，对许多PID和非PID材料进行了调查和比较，用于细通孔(< 10μm)互连或高频低损耗应用。第一个候选材料被选择用于再分配层(RDL)的制造，使用370mm × 470mm的玻璃板。采用半添加工艺(SAP)对不同介电材料的玻璃板进行直接金属化，形成菊花链试验车。雏菊链的工艺、制造集成和电学测量结果表明，雏菊链在玻璃板衬底中具有良好的连续性和电阻性。本研究还对热循环试验(TCT)和高加速应力试验(HAST)的可靠性进行了评价。
{"title":"Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection","authors":"Chien Chun-Hsien, Chien-Chou Chen, Wen-Liang Yeh, Wei Lin, Wu Cheng-Hui, Chen Fu-yang, Yi-Cheng Lin, Po-Chiang Wang, J. Li, Bo Cheng Lin, Yu-Hua Chen, T. Tseng","doi":"10.4071/2380-4505-2019.1.000216","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000216","url":null,"abstract":"\u0000 In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"90 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74643996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000492
T. Bernhard, L. Gregoriades, S. Branagan, L. Stamp, E. Steinhäuser, R. Schulz, F. Brüning
A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.
{"title":"Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study","authors":"T. Bernhard, L. Gregoriades, S. Branagan, L. Stamp, E. Steinhäuser, R. Schulz, F. Brüning","doi":"10.4071/2380-4505-2019.1.000492","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000492","url":null,"abstract":"\u0000 A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83156985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000120
Zhi Yang, K. Rivera, J. G. Patel, E. Tremble, David B. Stone, K. Choi, E. Blackshear
Laminates or sequential build-up (SBU) laminate comprised of dielectric materials, metal traces, and metal vias not only serve as the mechanical support for the silicon integrated circuits (ICs), but also electrically connect ICs to ball grid array (BGA); by way of an embedded power delivery structure. Electrical current required to power the ICs is carried through spatially distributed metal traces and vias. The non-uniformity in the power distribution may induce hotspots due to parasitic Ohmic heating; especially in regions with high current density. Electrical packaging engineers need effective tools to identify, quantify, and mitigate hot spots in the laminate. Thermoelectrical multiphysical simulation provides a robust platform integrating the electrical, and thermal analyses for the study of joule heating in a complex design. Conventional simulations simplify detailed laminate wiring layout as a single planar with effective orthogonal material properties. Such simplification provides a solution to the inherent simulation challenges encountered with a complex design (i.e. tiny characteristic lengths, high aspect ratios, excessive computational time and resources). However, simplification comes with a price. Information required to optimize the detail trace and via wiring physical design is unavailable in a solution incorporating an effective laminate; laminate joule heating as well as non-uniform trace wiring are left out. The laminate temperature profile is averaged based on effective material properties. Without accurate joule heating evaluation, the hotspots cannot be identified or quantified. Overheating inside the laminate compromises signal speed and integrity, raises reliability concerns, and may even trigger catastrophic damage of dielectric material breakdown. This work introduces an iterative approach integrating the detailed laminate electrical computer aided design (ECAD) and package design to simulate the joule heating with minimum simplification. The iterative loop enables constant update of temperature (thru thermal simulation platform) and power distribution (thru electrical simulation platform) in each trace layer and via. An accurate temperature dependent Joule Heating assessment is achieved upon convergence. The solution captures the dependence on temperature of the material properties and of the Joule heating itself. The package level structure including an IC with a power map is incorporated to simulate in-situ package operating condition. After thorough investigation and analyses of laminate joule heating phenomena under different conditions, a predictive curve for maximum temperature rise percentage has been proposed to guide laminate wiring layout physical design and optimization. A ratio exceeding 4–5% joule heating to IC power is recommended as the check point for simulation to assess laminate overheating issues with detailed trace layout information.
{"title":"4-2-4 Laminate hotspot identification and joule heating effect assessment via thermoelectrical simulation","authors":"Zhi Yang, K. Rivera, J. G. Patel, E. Tremble, David B. Stone, K. Choi, E. Blackshear","doi":"10.4071/2380-4505-2019.1.000120","DOIUrl":"https://doi.org/10.4071/2380-4505-2019.1.000120","url":null,"abstract":"\u0000 Laminates or sequential build-up (SBU) laminate comprised of dielectric materials, metal traces, and metal vias not only serve as the mechanical support for the silicon integrated circuits (ICs), but also electrically connect ICs to ball grid array (BGA); by way of an embedded power delivery structure. Electrical current required to power the ICs is carried through spatially distributed metal traces and vias. The non-uniformity in the power distribution may induce hotspots due to parasitic Ohmic heating; especially in regions with high current density. Electrical packaging engineers need effective tools to identify, quantify, and mitigate hot spots in the laminate. Thermoelectrical multiphysical simulation provides a robust platform integrating the electrical, and thermal analyses for the study of joule heating in a complex design. Conventional simulations simplify detailed laminate wiring layout as a single planar with effective orthogonal material properties. Such simplification provides a solution to the inherent simulation challenges encountered with a complex design (i.e. tiny characteristic lengths, high aspect ratios, excessive computational time and resources). However, simplification comes with a price. Information required to optimize the detail trace and via wiring physical design is unavailable in a solution incorporating an effective laminate; laminate joule heating as well as non-uniform trace wiring are left out. The laminate temperature profile is averaged based on effective material properties. Without accurate joule heating evaluation, the hotspots cannot be identified or quantified. Overheating inside the laminate compromises signal speed and integrity, raises reliability concerns, and may even trigger catastrophic damage of dielectric material breakdown.\u0000 This work introduces an iterative approach integrating the detailed laminate electrical computer aided design (ECAD) and package design to simulate the joule heating with minimum simplification. The iterative loop enables constant update of temperature (thru thermal simulation platform) and power distribution (thru electrical simulation platform) in each trace layer and via. An accurate temperature dependent Joule Heating assessment is achieved upon convergence. The solution captures the dependence on temperature of the material properties and of the Joule heating itself. The package level structure including an IC with a power map is incorporated to simulate in-situ package operating condition. After thorough investigation and analyses of laminate joule heating phenomena under different conditions, a predictive curve for maximum temperature rise percentage has been proposed to guide laminate wiring layout physical design and optimization. A ratio exceeding 4–5% joule heating to IC power is recommended as the check point for simulation to assess laminate overheating issues with detailed trace layout information.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"214 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77491301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-12-16DOI: 10.4071/2380-4505-2019.1.000480
L. Wentlent, J. Wilcox, Xuanyi Ding
As the electronics industry continues to evolve a concerted effort has developed to implement lower melting point solders. The ability to minimize the thermal exposure that an assembly is subjected to affords significant benefits with respect to both the reliability and the materials that can be used. One of the most popular low melt solder alloys currently being investigated by the industry is the Bi-Sn eutectic system, which has a melting point of 139°C. The BiSn system itself is not particularly novel as it was posited as a SAC alternative during the initial shift from Pb based solders. While a body of knowledge currently exists regarding this system, and the near eutectic variant BiSnAg, there are still concerns regarding its ductility, especially as a function of thermal exposure and strain rate. Bismuth is widely acknowledged as a brittle element and its presence in such quantities raises concerns of not just Cu6Sn5 embrittlement but also solder fragility in high strain rate types of environments. A challenge with regards to near term implementation is that most packages are not available with BiSn solder bumps. Therefore, it will be necessary to use components already balled with SAC 305 solder. This means that the resulting solder interconnect, reflowed below conventional SAC reflow temperatures, will form a type of mixed hybrid microstructure. This non-equilibrium microstructure will be composed of two regions, one Bi-rich region which is well past saturation and a second region which is Bi-deficient. It is of specific industrial interest then to not just investigate the BiSn solder system but also within the context of a realistic mixed interconnect. Recent work by several researchers has shown that this hybrid microstructure is unstable and quite active with respect to the movement and localized concentration of the Bismuth. The degree of mixing of these two regions has been shown to be highly dependent upon reflow temperature and the paste to ball volume ratio. Mixed SAC-BiSn solder joints were formed by placing SAC 305 spheres on BiSn paste deposits for a paste to ball volume ratio of .18. These samples were then reflowed at either 175°C or 200°C. SAC 305 control samples were also made using a conventional Pb-free reflow profile with a peak temperature of 247°C. A 22 mil Cu-OSP pad on a 1.0 mm thick FR4 substrate was used for all samples. A selection of the solder joints were then isothermally aged at 90°C for 200 hours. Using a joint level micromechanical tester, ball shear tests were conducted at a range of strain rates for samples in the as-reflowed and aged state. Using this information, the strain rate sensitivity of the interconnects was mapped and correlated with the observed failure modes. Investigations into the fracture mechanisms were conducted by examining the shear fracture surface with optical and scanning electron microscopy. Additionally, the evolution of the microstructure was characterized. Results showed a clea
随着电子工业的不断发展，一种协调一致的努力已经发展到实施低熔点焊料。能够最大限度地减少组件的热暴露，在可靠性和可使用的材料方面都有显著的好处。目前业界正在研究的最流行的低熔点焊料合金之一是Bi-Sn共晶系统，其熔点为139°C。BiSn系统本身并不是特别新颖，因为在最初从Pb基焊料转变为SAC的过程中，它被认为是SAC的替代品。虽然目前已有关于该体系和近共晶型BiSnAg的知识体系，但其延展性，特别是作为热暴露和应变率的函数，仍然令人担忧。铋被广泛认为是一种脆性元素，它的大量存在不仅引起了Cu6Sn5脆化的担忧，而且引起了高应变率环境下焊料的易损性。关于近期实现的一个挑战是，大多数封装不具有BiSn焊料凸起。因此，有必要使用已经用SAC 305焊料球化的组件。这意味着所得到的焊料互连，再流低于常规SAC再流温度，将形成一种混合的混合微观结构。这种非平衡微观结构将由两个区域组成，一个是远超过饱和的富bi区域，另一个是缺bi区域。因此，不仅要研究BiSn焊料系统，而且要在实际混合互连的背景下进行研究，这是具有特定工业利益的。最近几位研究人员的工作表明，这种杂化微观结构是不稳定的，并且在铋的运动和局部浓度方面相当活跃。这两个区域的混合程度已被证明高度依赖于回流温度和膏体与球的体积比。通过将SAC 305球体放置在BiSn膏体沉积层上，形成SAC-BiSn混合焊点，膏体与球的体积比为0.18。然后将这些样品在175°C或200°C下回流。SAC 305对照样品也采用传统的无铅回流曲线，峰值温度为247°C。所有样品均使用1.0 mm厚FR4衬底上的22 mil Cu-OSP衬垫。然后选择焊点在90°C下等温时效200小时。采用节理级微力学试验机，对试样在回流状态和时效状态下进行了不同应变速率下的球剪试验。利用这些信息，绘制了互连的应变率灵敏度，并将其与观察到的破坏模式相关联。利用光学显微镜和扫描电镜对剪切断口进行了断裂机理研究。此外，还对微观组织的演变进行了表征。结果表明，在较高的应变速率下，从延展性焊接失效到脆性分离失效有明显的转变。
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