Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000181
C. Farnum, K. Rahim
To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance. In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (Gallium Nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using 150μm pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, with both an ENIG (Electroless Nickel Immersion Gold) and eutectic tin-lead solder pad finish evaluated. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths, a flux stamping investigation, and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).
{"title":"Fine-pitch Copper Pillar Flip Chips in High Reliability Applications","authors":"C. Farnum, K. Rahim","doi":"10.4071/1085-8024-2021.1.000181","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000181","url":null,"abstract":"\u0000 To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance.\u0000 In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (Gallium Nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using 150μm pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, with both an ENIG (Electroless Nickel Immersion Gold) and eutectic tin-lead solder pad finish evaluated. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths, a flux stamping investigation, and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"14 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90280108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000362
Evan Griffith, S. Lim
The semiconductor industry is quickly adopting heterogeneous integration as a solution to allow a large number of dies to be packed onto smaller components, improving cost-performance while expanding functionality. As such, the printing of solder paste formulated for System in Package (SiP) applications is becoming more difficult, with many depositions designed at one point as extremes during testing becoming the norm in industry. This paper will first briefly discuss the evolution of soldering material for heterogeneous integration, as some aspects of solder paste manufacturing, such as powder size, differ significantly from larger scale soldering applications. The objective of this study is to illustrate critical parameters for the printing of SiP paste. Multiple parameters that are important for SiP paste printing applications will be discussed, such as the metal load optimization, paste rheology, and metal powder size, type, and quality.
{"title":"Evolution and Applications of Fine-Feature Solder Paste Printing for Heterogeneous Integration","authors":"Evan Griffith, S. Lim","doi":"10.4071/1085-8024-2021.1.000362","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000362","url":null,"abstract":"\u0000 The semiconductor industry is quickly adopting heterogeneous integration as a solution to allow a large number of dies to be packed onto smaller components, improving cost-performance while expanding functionality. As such, the printing of solder paste formulated for System in Package (SiP) applications is becoming more difficult, with many depositions designed at one point as extremes during testing becoming the norm in industry. This paper will first briefly discuss the evolution of soldering material for heterogeneous integration, as some aspects of solder paste manufacturing, such as powder size, differ significantly from larger scale soldering applications. The objective of this study is to illustrate critical parameters for the printing of SiP paste. Multiple parameters that are important for SiP paste printing applications will be discussed, such as the metal load optimization, paste rheology, and metal powder size, type, and quality.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"10 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87915431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000103
Jay Zhang, Indy Dutta, J. Brueckner, Katsumi Bono
Glass carrier wafers are used in many temporary bonding and debonding applications such as wafer thinning and fan-out wafer level packaging. For light-based debonding, a UV light source is often chosen for one or more of the following reasons: limiting light penetration into the sensitive die area; providing uniform light beam energy distribution; minimizing heat problems; maximizing overall process throughput. Corning has recently developed high UV transmission glass carrier wafers in response to market demand. In this paper, we will discuss the benefits of using such glass wafers for 308nm excimer laser debonding as well as a shorter wavelength UV lamp debonding cases.
{"title":"High UV Transmission Glass Carriers for Advanced Packaging","authors":"Jay Zhang, Indy Dutta, J. Brueckner, Katsumi Bono","doi":"10.4071/1085-8024-2021.1.000103","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000103","url":null,"abstract":"\u0000 Glass carrier wafers are used in many temporary bonding and debonding applications such as wafer thinning and fan-out wafer level packaging. For light-based debonding, a UV light source is often chosen for one or more of the following reasons: limiting light penetration into the sensitive die area; providing uniform light beam energy distribution; minimizing heat problems; maximizing overall process throughput. Corning has recently developed high UV transmission glass carrier wafers in response to market demand. In this paper, we will discuss the benefits of using such glass wafers for 308nm excimer laser debonding as well as a shorter wavelength UV lamp debonding cases.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83595210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000228
Yu-Hsiang Chang, Bing-Yuan Huang, Hung-Hsien Huang, Dao-Long Chen, D. Tarng, C. Hung
With the advent of the 5G era, major package and testing plants have been taking frequent action recently. Obviously, with higher and higher performance requirements, SiP is a functional package integrated multiple functional chips, including processor, memory into one package. However, thermal design is an important issue to be addressed at this time. This paper mainly presents a 3D SiP structure based on the combination of two substrates, integrating 4 components in a single package, total power consumption is 30 Watt. To address thermal management difficulties of this 3D SiP, a method is designed to increase the thermal path between the two boards. The Effects of the structure, number of via, and changing location of components aspects of the thermal performance are studied. The thermal vias was designed in between the two boards provide are direct heat dissipation, connecting the metal studs above passive components to improve thermal performance. Thermal performance with 240 vias is improved by 0.4%, while the number of vias increases from 240 to 912, the temperature decreases only 1.0%, 0.6% respectively. The difference of thermal resistance (θJB) comparison is 1.9%, 1.5% and 1.0%. There are limits to the improvement of vias, the effect of increasing the number of via is not as good as expected. However, increasing the thermal conduction path may have an effect on the void of mold flow. s 3D mold flow modeling of the transfer molding process with molded underfill (MUF) using Moldex3D is applied to optimize design and process parameters that can reduce device defects. There is one important challenge that faced air voids entrapment in molding area. Generally, the experiments involve a lot of design of experiment (DOE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP, which can reduce development cycle time before mass production. From the mold flow simulation results, when the number of plunger segments increases and the tail flow rate decreases, the void issues can be effectively improved.
{"title":"Optimization of Thermal Design and Mold Flow Process for 3D SiP Structure","authors":"Yu-Hsiang Chang, Bing-Yuan Huang, Hung-Hsien Huang, Dao-Long Chen, D. Tarng, C. Hung","doi":"10.4071/1085-8024-2021.1.000228","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000228","url":null,"abstract":"\u0000 With the advent of the 5G era, major package and testing plants have been taking frequent action recently. Obviously, with higher and higher performance requirements, SiP is a functional package integrated multiple functional chips, including processor, memory into one package. However, thermal design is an important issue to be addressed at this time. This paper mainly presents a 3D SiP structure based on the combination of two substrates, integrating 4 components in a single package, total power consumption is 30 Watt. To address thermal management difficulties of this 3D SiP, a method is designed to increase the thermal path between the two boards. The Effects of the structure, number of via, and changing location of components aspects of the thermal performance are studied. The thermal vias was designed in between the two boards provide are direct heat dissipation, connecting the metal studs above passive components to improve thermal performance. Thermal performance with 240 vias is improved by 0.4%, while the number of vias increases from 240 to 912, the temperature decreases only 1.0%, 0.6% respectively. The difference of thermal resistance (θJB) comparison is 1.9%, 1.5% and 1.0%. There are limits to the improvement of vias, the effect of increasing the number of via is not as good as expected. However, increasing the thermal conduction path may have an effect on the void of mold flow. s\u0000 3D mold flow modeling of the transfer molding process with molded underfill (MUF) using Moldex3D is applied to optimize design and process parameters that can reduce device defects. There is one important challenge that faced air voids entrapment in molding area. Generally, the experiments involve a lot of design of experiment (DOE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP, which can reduce development cycle time before mass production. From the mold flow simulation results, when the number of plunger segments increases and the tail flow rate decreases, the void issues can be effectively improved.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"319 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86462629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000195
Aimee M. Morey, S. Popelar, Julie Hook
The experimental study described herein investigates thermomigration of both eutectic Sn/Pb and lead free Sn/Ag/Cu solder joints, with the additional focus on the development of an Arrhenius failure model of time-to- failure as a function of temperature. Flip chip test vehicles were assembled with daisy chain die, with and without underfill, attached to ceramic and organic package substrates, using standard reflow processes. Three different under bump metallurgy technologies were investigated: sputtered thin film Al/NiV/Cu, thick electroplated nickel, and thick electroplated copper (i.e., copper pillars). The test vehicles were subjected to unbiased high temperature storage (HTS) testing with temperatures ranging from 125°C to 200°C. Failure was determined from continuity testing at regular intervals until an open circuit or high resistivity was detected. The results demonstrate the robustness of Al/NiV/Cu UBM at temperatures less than 130°C, and of the thick electroplated UBM at temperatures of 150°C. Based on the HTS test results, and corresponding analyses, a thermomigration failure model was generated for eutectic Sn/Pb and lead free Sn/Ag/Cu solder alloys using an Arrhenius-like fit to the failure data.
{"title":"An Investigation into Thermomigration Failure of Flip Chip Solder Joint Interconnects used in High Reliability Applications","authors":"Aimee M. Morey, S. Popelar, Julie Hook","doi":"10.4071/1085-8024-2021.1.000195","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000195","url":null,"abstract":"\u0000 The experimental study described herein investigates thermomigration of both eutectic Sn/Pb and lead free Sn/Ag/Cu solder joints, with the additional focus on the development of an Arrhenius failure model of time-to- failure as a function of temperature. Flip chip test vehicles were assembled with daisy chain die, with and without underfill, attached to ceramic and organic package substrates, using standard reflow processes. Three different under bump metallurgy technologies were investigated: sputtered thin film Al/NiV/Cu, thick electroplated nickel, and thick electroplated copper (i.e., copper pillars). The test vehicles were subjected to unbiased high temperature storage (HTS) testing with temperatures ranging from 125°C to 200°C. Failure was determined from continuity testing at regular intervals until an open circuit or high resistivity was detected. The results demonstrate the robustness of Al/NiV/Cu UBM at temperatures less than 130°C, and of the thick electroplated UBM at temperatures of 150°C. Based on the HTS test results, and corresponding analyses, a thermomigration failure model was generated for eutectic Sn/Pb and lead free Sn/Ag/Cu solder alloys using an Arrhenius-like fit to the failure data.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"97 3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83983914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000149
Tim LeClair, S. Martin
Enhanced electronic substrate design objectives for higher frequency products (5G telecom systems) can now be achieved with the use of novel coaxial-thru-via configurations in glass (TGVs). When compared with standard pillar filled thru-vias in glass, coaxial-thru-vias exhibit greater than 40dB improvement in via-to-via crosstalk isolation and 0.5dB improvement in insertion loss both at 30 GHz. Coaxial-Thru-Vias provide precise unadjusted 50 Ohm impedance matching device designs at the 5G product frequencies. The coaxial dielectric core chemistry is modifiable to tune electrical parameters to meet specific design requirements. This paper summarizes all designs, simulations, and modeling performed to date. The superior properties of coaxial vias in glass and fused silica over standard pillar vias are documented and captured in sweeps to 100 GHz. Via and pitch dimensions of 100/200 and 50/100 um have been assessed. Manufacturing methods have been demonstrated using thick film conductor materials in prototype designs. Coaxial vias can optionally be fabricated as dual-purpose configurations reducing thru-via count requirements, substrate footprints, and package/module costs.
{"title":"Design of Coaxial TGV Substrates; Enhancing RF Via to Via Isolation","authors":"Tim LeClair, S. Martin","doi":"10.4071/1085-8024-2021.1.000149","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000149","url":null,"abstract":"\u0000 Enhanced electronic substrate design objectives for higher frequency products (5G telecom systems) can now be achieved with the use of novel coaxial-thru-via configurations in glass (TGVs). When compared with standard pillar filled thru-vias in glass, coaxial-thru-vias exhibit greater than 40dB improvement in via-to-via crosstalk isolation and 0.5dB improvement in insertion loss both at 30 GHz. Coaxial-Thru-Vias provide precise unadjusted 50 Ohm impedance matching device designs at the 5G product frequencies. The coaxial dielectric core chemistry is modifiable to tune electrical parameters to meet specific design requirements.\u0000 This paper summarizes all designs, simulations, and modeling performed to date. The superior properties of coaxial vias in glass and fused silica over standard pillar vias are documented and captured in sweeps to 100 GHz. Via and pitch dimensions of 100/200 and 50/100 um have been assessed. Manufacturing methods have been demonstrated using thick film conductor materials in prototype designs. Coaxial vias can optionally be fabricated as dual-purpose configurations reducing thru-via count requirements, substrate footprints, and package/module costs.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"33 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82374645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000303
Motohiro Negishi, T. Shibata, Xinrong Li, N. Suzuki
In order to form a compartmental EMI shielding structure for radio frequency (RF) modules, we have proposed the new process named ”imprint-Through Mold Via (i-TMV)”, which could be fabricated by imprinting with a silicon master and filling with conductive paste. In this work, a test coupon was fabricated and EMI shielding effect of the i-TMV was actually evaluated by measurement of the electric field strength that leaked through from via array. As a result, it was found that the shielding effect was 23.6 dB at 4 GHz, which was close to the completely shielded value with a metal cap (25.6 dB). This result indicated that the i-TMV was significantly effective as a compartmental EMI shielding for the Sub-6 band application.
{"title":"Verification of Compartmental Electromagnetic Interference Shielding Effect with imprint-Through Mold Via (i-TMV) for RF modules","authors":"Motohiro Negishi, T. Shibata, Xinrong Li, N. Suzuki","doi":"10.4071/1085-8024-2021.1.000303","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000303","url":null,"abstract":"\u0000 In order to form a compartmental EMI shielding structure for radio frequency (RF) modules, we have proposed the new process named ”imprint-Through Mold Via (i-TMV)”, which could be fabricated by imprinting with a silicon master and filling with conductive paste. In this work, a test coupon was fabricated and EMI shielding effect of the i-TMV was actually evaluated by measurement of the electric field strength that leaked through from via array. As a result, it was found that the shielding effect was 23.6 dB at 4 GHz, which was close to the completely shielded value with a metal cap (25.6 dB). This result indicated that the i-TMV was significantly effective as a compartmental EMI shielding for the Sub-6 band application.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"7 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82691824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000001
Rich Rochford, Craig Blanchette
High value devices used in microwave modules and other microelectronic assemblies have become increasingly thin and susceptible to “Component Out Of Pocket” (COOP) conditions that can occur during packaging, shipping, and customer handling. This defect condition is especially problematic for automated assembly which strives to be touch-free and efficient with orderly device presentation. COOP is a major contributor to “Cost Of Poor Quality” (COPQ) within the business. A funded study into COOP conditions was conducted and a dozen root causes were identified. It was discovered that traditional “waffle packs” have mechanical issues related to flatness tolerances with respect to the waffle tray and lid. The addition of a standard clip further contributes to the issue, both of which are key root causes of the costly “Component Out Of Pocket” (COOP) condition. A novel Lid-Clip System (LCS2) was engineered to compensate for those mechanical issues, bringing robust captivation and preservation of devices in waffle tray pockets. Static dissipative material for lid and clip was selected to provide unparalleled ESD Class 000 protection for high value devices with the lowest voltage susceptibility thresholds.
{"title":"Eliminate Costly Component Out Of Pocket Defect Condition during Microelectronic Component Packaging/Shipping/Handling","authors":"Rich Rochford, Craig Blanchette","doi":"10.4071/1085-8024-2021.1.000001","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000001","url":null,"abstract":"\u0000 High value devices used in microwave modules and other microelectronic assemblies have become increasingly thin and susceptible to “Component Out Of Pocket” (COOP) conditions that can occur during packaging, shipping, and customer handling. This defect condition is especially problematic for automated assembly which strives to be touch-free and efficient with orderly device presentation.\u0000 COOP is a major contributor to “Cost Of Poor Quality” (COPQ) within the business. A funded study into COOP conditions was conducted and a dozen root causes were identified.\u0000 It was discovered that traditional “waffle packs” have mechanical issues related to flatness tolerances with respect to the waffle tray and lid. The addition of a standard clip further contributes to the issue, both of which are key root causes of the costly “Component Out Of Pocket” (COOP) condition.\u0000 A novel Lid-Clip System (LCS2) was engineered to compensate for those mechanical issues, bringing robust captivation and preservation of devices in waffle tray pockets. Static dissipative material for lid and clip was selected to provide unparalleled ESD Class 000 protection for high value devices with the lowest voltage susceptibility thresholds.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"43 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83616219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.4071/1085-8024-2021.1.000265
R. Dohle, Gerold Henning, Maximilian Wallrodt, C. Gréus, C. Neumeyr
In this paper we present an optimized manufacturing technique for special long-wavelength 1-dimensional and 2-dimensional Vertical Cavity Surface Emitting Laser Diode (VCSEL) arrays with focus on die bonding and a special wire bonding process as well as additional possibilities to make the manufacturing more productive and to increase the product quality, reliability, and life time. VCSEL arrays have a very broad application potential. Objective of this paper is the development of an assembly technology for long-wavelength VCSEL arrays with high positioning accuracy for automated production with high total yield, using gold-based conductive glue (because silver migration is a concern) securing high yield and extremely high reliability and lifetime. Due to special customer requirements, a final thickness of the conductive glue of 35 micron with low standard deviation is necessary. For highest reliability, gold wire bonding of the top side contact of the VCSEL to a silicon substrate with gold metallization has been a customer requirement. With the described technique we develop and produce customer specific products with dedicated wavelength, performance, and packaging options. Bases on our findings, very flexible and scalable solutions are possible, matching many different applications. Finally, we will present an overview of our results on the physical and electro-optical characterization of the VCSEL devices. This yielded a very productive manufacturing technique, meeting the requirements mentioned above. Special design features of the VCSEL ensure that the relatively high thermal resistance of the cured conductive glue layer does not impair the electro-optical properties or the lifetime of the VCSELs. For the interconnection of the top side contact we used gold wire with 20 microns diameter, using ball-wedge, Stand-Off Stich Bond process with special loop geometry, required by the customer. Due to the properties of the semiconductor material of the VCSELs a low bonding temperature is required, enabled by our special wire bonding process. Gold wire bonding delivered excellent results, by far exceeding the customer specification. The optical spectrum of the VCSELs and other measurements indicate that the assembly processes do not harm the laser diodes or their electro-optical properties. All customer requirements for the 1-dimensional and 2-dimensional VCSEL arrays have been met. The electro-optical and burn-in data furnished proof of the quality of the engineered assembly technology. The technologies developed for low current as well as high current laser arrays will enable new devices for a huge amount of new applications because of the novel manufacturing processes as well as innovative packaging of the VCSEL arrays.
{"title":"Advanced Packaging Technology for Novel 1-dimensional and 2-dimensional VCSEL Arrays","authors":"R. Dohle, Gerold Henning, Maximilian Wallrodt, C. Gréus, C. Neumeyr","doi":"10.4071/1085-8024-2021.1.000265","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000265","url":null,"abstract":"\u0000 In this paper we present an optimized manufacturing technique for special long-wavelength 1-dimensional and 2-dimensional Vertical Cavity Surface Emitting Laser Diode (VCSEL) arrays with focus on die bonding and a special wire bonding process as well as additional possibilities to make the manufacturing more productive and to increase the product quality, reliability, and life time. VCSEL arrays have a very broad application potential. Objective of this paper is the development of an assembly technology for long-wavelength VCSEL arrays with high positioning accuracy for automated production with high total yield, using gold-based conductive glue (because silver migration is a concern) securing high yield and extremely high reliability and lifetime. Due to special customer requirements, a final thickness of the conductive glue of 35 micron with low standard deviation is necessary. For highest reliability, gold wire bonding of the top side contact of the VCSEL to a silicon substrate with gold metallization has been a customer requirement. With the described technique we develop and produce customer specific products with dedicated wavelength, performance, and packaging options. Bases on our findings, very flexible and scalable solutions are possible, matching many different applications. Finally, we will present an overview of our results on the physical and electro-optical characterization of the VCSEL devices. This yielded a very productive manufacturing technique, meeting the requirements mentioned above. Special design features of the VCSEL ensure that the relatively high thermal resistance of the cured conductive glue layer does not impair the electro-optical properties or the lifetime of the VCSELs. For the interconnection of the top side contact we used gold wire with 20 microns diameter, using ball-wedge, Stand-Off Stich Bond process with special loop geometry, required by the customer. Due to the properties of the semiconductor material of the VCSELs a low bonding temperature is required, enabled by our special wire bonding process. Gold wire bonding delivered excellent results, by far exceeding the customer specification. The optical spectrum of the VCSELs and other measurements indicate that the assembly processes do not harm the laser diodes or their electro-optical properties. All customer requirements for the 1-dimensional and 2-dimensional VCSEL arrays have been met. The electro-optical and burn-in data furnished proof of the quality of the engineered assembly technology. The technologies developed for low current as well as high current laser arrays will enable new devices for a huge amount of new applications because of the novel manufacturing processes as well as innovative packaging of the VCSEL arrays.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72638883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we developed novel low temperature curable (around 200~250 °C) low Dk (2.7) & Df (0.002) polyimide with high glass transition temperature (170 °C) and elongation (100%). We also developed negative tone photosensitive polyimide with low Dk (3.0) & Df (0.007) by photo initiator and cross linker. Material types of them are liquid or B-stage sheet materials. Patterning methods of the non-photosensitive polyimides were imprint and UV laser ablation. Resolution of those process were 10um via and 30um via respectively. Photosensitive polyimide was patterned by photolithographic tool. We fabricated fine patterned polyimide of photosensitive polyimide by photolithography. We investigated the frequency dependence of the novel low Dk & Df polyimide up to 95 GHz, and confirmed that Df gradually increased from 0.002 to 0.005 as the frequency increased. To confirm effect of the novel polyimide, insertion loss of micro-strip line whose length was 10 mm were measured using the new developed polyimide. Insertion loss (S21 parameter) of the novel polyimide was 0.8 and that was less than half of conventional polyimide. RDL structure was fabricated by novel low Dk and Df polyimide and we tested bump shear strength after thermal cycle test. All shear mode were ductile solder failure without polyimide delamination. Because our novel polyimides show excellent dielectric, thermal and mechanical properties, they are suitable to insulator of RDL for FO-AiP.
{"title":"Low Temperature Curable Low Dk & Df Polyimide for Antenna in Package","authors":"Hitoshi Araki, Akira Shimada, Hisashi Ogasawara, Masaya Jukei, T. Fujiwara, Masao Tomikawa","doi":"10.4071/1085-8024-2021.1.000130","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000130","url":null,"abstract":"\u0000 In this paper, we developed novel low temperature curable (around 200~250 °C) low Dk (2.7) & Df (0.002) polyimide with high glass transition temperature (170 °C) and elongation (100%). We also developed negative tone photosensitive polyimide with low Dk (3.0) & Df (0.007) by photo initiator and cross linker. Material types of them are liquid or B-stage sheet materials. Patterning methods of the non-photosensitive polyimides were imprint and UV laser ablation. Resolution of those process were 10um via and 30um via respectively. Photosensitive polyimide was patterned by photolithographic tool. We fabricated fine patterned polyimide of photosensitive polyimide by photolithography. We investigated the frequency dependence of the novel low Dk & Df polyimide up to 95 GHz, and confirmed that Df gradually increased from 0.002 to 0.005 as the frequency increased. To confirm effect of the novel polyimide, insertion loss of micro-strip line whose length was 10 mm were measured using the new developed polyimide. Insertion loss (S21 parameter) of the novel polyimide was 0.8 and that was less than half of conventional polyimide. RDL structure was fabricated by novel low Dk and Df polyimide and we tested bump shear strength after thermal cycle test. All shear mode were ductile solder failure without polyimide delamination. Because our novel polyimides show excellent dielectric, thermal and mechanical properties, they are suitable to insulator of RDL for FO-AiP.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"35 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89778300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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