Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441072
N. Das
Si-based photodetectors play key role in the performance of Si-photonic Devices. Design of high performance Si-detectors for optical communication system is a challenging task. Drawbacks arising from low absorption efficiency due to indirect nature of the band-gap in Si, strain in Ge/Si heterointerfaces, etc are to be overcome with suitable structure/design of the detectors. In this paper, a brief review is given on Si-detectors, such as Si-CMOS, SiGe and Ge-on-Si photodetectors including their fabrication techniques, performance trend with some aspects of modeling.
{"title":"Si-based photodetectors in optical communication","authors":"N. Das","doi":"10.1109/ELECTRO.2009.5441072","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441072","url":null,"abstract":"Si-based photodetectors play key role in the performance of Si-photonic Devices. Design of high performance Si-detectors for optical communication system is a challenging task. Drawbacks arising from low absorption efficiency due to indirect nature of the band-gap in Si, strain in Ge/Si heterointerfaces, etc are to be overcome with suitable structure/design of the detectors. In this paper, a brief review is given on Si-detectors, such as Si-CMOS, SiGe and Ge-on-Si photodetectors including their fabrication techniques, performance trend with some aspects of modeling.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133155697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441043
R. Moriwaki, Minoru Watanabe
Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers. However, such high-power lasers increase power consumption and package size. In the worst case, they might require a cooling system. For that reason, this paper proposes a negative logic implementation method by which optical configurations can be accelerated without ORGA architecture modification and any increase of laser power. This time, the method was demonstrated on a dynamic optically reconfigurable gate array architecture. Based on the experimental results, this paper clarifies the acceleration method's effectiveness.
{"title":"An optical configuration acceleration method using negative logic implementation","authors":"R. Moriwaki, Minoru Watanabe","doi":"10.1109/ELECTRO.2009.5441043","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441043","url":null,"abstract":"Up to now, as one of multi-context devices, an optically reconfigurable gate array (ORGA) has been developed to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers. However, such high-power lasers increase power consumption and package size. In the worst case, they might require a cooling system. For that reason, this paper proposes a negative logic implementation method by which optical configurations can be accelerated without ORGA architecture modification and any increase of laser power. This time, the method was demonstrated on a dynamic optically reconfigurable gate array architecture. Based on the experimental results, this paper clarifies the acceleration method's effectiveness.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441164
H. Gupta, R. Parmar, R. Dave
Low Voltage Differential Signaling (LVDS) is a method used for high-speed transmission of binary data over copper cable. In the earlier remote sensing payload camera electronics, the multi-port parallel data were provided to spacecraft base-band system, requiring large number of I/O connectors and associated harnesses. This multi-port parallel data can be multiplexed, serialized and transmitted to other subsystems using LVDS interface thereby reducing the number of I/Os, cabling and associated weight of interface hardware. This work presents the design, simulation and analysis of I/O interface circuits for high speed operation which is fully compliant with the IEEE STD 1596.3 (LVDS). A common mode feedback (CMFB) circuitry is utilized in the LVDS transmitter to stabilize the common mode voltage in a pre-defined range. In most of the previous designs [1] output cells utilize voltage divider circuit composed of two large resistors (≈MΩ) between output pads and center is taped as feedback. These resistors may be off-chip discrete components (due to stringent stability and large die area requirement). The modified common mode feedback circuit has been designed and analyzed with appropriate transistor geometry and evaluated. Its performance is also compared with conventional CMFB design.
{"title":"High speed LVDS driver for SERDES","authors":"H. Gupta, R. Parmar, R. Dave","doi":"10.1109/ELECTRO.2009.5441164","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441164","url":null,"abstract":"Low Voltage Differential Signaling (LVDS) is a method used for high-speed transmission of binary data over copper cable. In the earlier remote sensing payload camera electronics, the multi-port parallel data were provided to spacecraft base-band system, requiring large number of I/O connectors and associated harnesses. This multi-port parallel data can be multiplexed, serialized and transmitted to other subsystems using LVDS interface thereby reducing the number of I/Os, cabling and associated weight of interface hardware. This work presents the design, simulation and analysis of I/O interface circuits for high speed operation which is fully compliant with the IEEE STD 1596.3 (LVDS). A common mode feedback (CMFB) circuitry is utilized in the LVDS transmitter to stabilize the common mode voltage in a pre-defined range. In most of the previous designs [1] output cells utilize voltage divider circuit composed of two large resistors (≈MΩ) between output pads and center is taped as feedback. These resistors may be off-chip discrete components (due to stringent stability and large die area requirement). The modified common mode feedback circuit has been designed and analyzed with appropriate transistor geometry and evaluated. Its performance is also compared with conventional CMFB design.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114464377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441035
Sanjay Mishra, D. Mohan, A. K. Gupta, M. K. Mridha
Study of singular phases is important for analyzing the wavefront deterioration of laser beams while propagating through strong atmospheric turbulence. Such study is useful to the applications involving the laser propagation and the phase detection systems. Few laser cavity modes inherently possess singular behavior. We report the study of detection of single and multiple phase singularities embedded in the fundamental laser mode. Numerically these vortices have been produced and two interferometric methods were used for the detection. Alternatively singularities could also be detected by measuring local slopes of wavefront employing Shack-Hartmann principle. Comparison of these methods was also discussed.
{"title":"Study of singular phases in laser cavity modes","authors":"Sanjay Mishra, D. Mohan, A. K. Gupta, M. K. Mridha","doi":"10.1109/ELECTRO.2009.5441035","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441035","url":null,"abstract":"Study of singular phases is important for analyzing the wavefront deterioration of laser beams while propagating through strong atmospheric turbulence. Such study is useful to the applications involving the laser propagation and the phase detection systems. Few laser cavity modes inherently possess singular behavior. We report the study of detection of single and multiple phase singularities embedded in the fundamental laser mode. Numerically these vortices have been produced and two interferometric methods were used for the detection. Alternatively singularities could also be detected by measuring local slopes of wavefront employing Shack-Hartmann principle. Comparison of these methods was also discussed.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115157036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441178
S. Bhattacherjee, A. Biswas
In this paper, analytical models for threshold voltage Vt and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting Vt and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate Vt, S and drain induced barrier lowering (DIBL) of DG MOSFETs with different gate dielectrics for various values of effective oxide thickness (EOT). Also the effect of sidewall spacers on Vt has been predicted. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the reported simulated data.
{"title":"Impact of high-k dielectrics and spacer layers on the elctrical performance of symmetrical double gate MOSFETs","authors":"S. Bhattacherjee, A. Biswas","doi":"10.1109/ELECTRO.2009.5441178","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441178","url":null,"abstract":"In this paper, analytical models for threshold voltage Vt and subthreshold slope S for symmetric double gate MOSFETs with high-k dielectrics are proposed. Analytical approaches for predicting Vt and S are developed by considering effects of fringing electric field, interface trap charge density and sidewall spacers. The proposed model has been employed to calculate Vt, S and drain induced barrier lowering (DIBL) of DG MOSFETs with different gate dielectrics for various values of effective oxide thickness (EOT). Also the effect of sidewall spacers on Vt has been predicted. Accuracy of models has been verified by comparing analytical results obtained from proposed models with the reported simulated data.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122985113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441084
S. Sankaralingam, B. Gupta
A natural progression from the Personal Area Network (PAN) concept is the Body Area Network (BAN). A wearable antenna is an essential part of any Wireless BAN. A microstrip patch radiator is chosen as an example of low-profile wearable antenna, as it can be made conformal for integration into clothing. In this paper, a textile microstrip circular disk antenna for such body centered Wireless Local Area Network (WLAN) has been developed and tested. The conductive combined cotton (65∶35) fabric has been chosen as its substrate material. Thus the suitability of fabric substrate materials for the development of microstrip patch antennas is well demonstrated.
{"title":"A textile antenna for WLAN applications","authors":"S. Sankaralingam, B. Gupta","doi":"10.1109/ELECTRO.2009.5441084","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441084","url":null,"abstract":"A natural progression from the Personal Area Network (PAN) concept is the Body Area Network (BAN). A wearable antenna is an essential part of any Wireless BAN. A microstrip patch radiator is chosen as an example of low-profile wearable antenna, as it can be made conformal for integration into clothing. In this paper, a textile microstrip circular disk antenna for such body centered Wireless Local Area Network (WLAN) has been developed and tested. The conductive combined cotton (65∶35) fabric has been chosen as its substrate material. Thus the suitability of fabric substrate materials for the development of microstrip patch antennas is well demonstrated.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441139
Sudip Dogra, S. Manna, Aritra Banik, S. Maiti, S. Sarkar
Every year lot of properties and lives are lost in fires. When the firefighters start extinguishing fires, they have to enter the fire affected region, but the main problem is that in most cases the firefighters don't have an overall knowledge of inside scenario of progress of fire. Sometime it can lead to death of firemen. As for example nationwide, of the roughly 100 firefighters who die on duty each year, a quarter loses their lives in fires, according to the U.S. fire administration [1].Nearly half the deaths are the result of heart attacks or other health-related problems. So, when a firefighter loses his life in the line of duty, it is a reminder of the complexity and peril of the profession, despite a dedication to improved equipment and training in recent years. So, if the firefighters have a prior knowledge about the nature of progress of fire within the building/premises, they can plan their action and movement accordingly. In this paper we have proposed a scheme for planning of fire fighting that will help the firefighters to extinguish the fire more effectively.
{"title":"A novel approach for RFID based fire protection","authors":"Sudip Dogra, S. Manna, Aritra Banik, S. Maiti, S. Sarkar","doi":"10.1109/ELECTRO.2009.5441139","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441139","url":null,"abstract":"Every year lot of properties and lives are lost in fires. When the firefighters start extinguishing fires, they have to enter the fire affected region, but the main problem is that in most cases the firefighters don't have an overall knowledge of inside scenario of progress of fire. Sometime it can lead to death of firemen. As for example nationwide, of the roughly 100 firefighters who die on duty each year, a quarter loses their lives in fires, according to the U.S. fire administration [1].Nearly half the deaths are the result of heart attacks or other health-related problems. So, when a firefighter loses his life in the line of duty, it is a reminder of the complexity and peril of the profession, despite a dedication to improved equipment and training in recent years. So, if the firefighters have a prior knowledge about the nature of progress of fire within the building/premises, they can plan their action and movement accordingly. In this paper we have proposed a scheme for planning of fire fighting that will help the firefighters to extinguish the fire more effectively.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123895982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441175
M. Dey, S. Chattopadhyay
In this paper, a comparative study has been performed on the locations of charge centroid and quantized carrier distributions for conventional and strained-Si MOS capacitors. The induced channel strain has been observed to modify surface quantization effect significantly. The position of charge centroid and the relevant carrier distribution have been studied for the variation of gate dielectric layer thickness, substrate doping concentration, and induced strain in the epitaxial layer. Position of charge centroid and peak carrier density modifies the measured oxide thickness, leading to the extraction of erroneous device parametric values. Therefore, a correction factor for the measured thickness of ultra thin gate dielectric layer has also been developed for the MOS capacitors with quantized surface.
{"title":"A comparative study of surface quantization effects in Si and strained-Si MOS structures with ultrathin gate oxides","authors":"M. Dey, S. Chattopadhyay","doi":"10.1109/ELECTRO.2009.5441175","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441175","url":null,"abstract":"In this paper, a comparative study has been performed on the locations of charge centroid and quantized carrier distributions for conventional and strained-Si MOS capacitors. The induced channel strain has been observed to modify surface quantization effect significantly. The position of charge centroid and the relevant carrier distribution have been studied for the variation of gate dielectric layer thickness, substrate doping concentration, and induced strain in the epitaxial layer. Position of charge centroid and peak carrier density modifies the measured oxide thickness, leading to the extraction of erroneous device parametric values. Therefore, a correction factor for the measured thickness of ultra thin gate dielectric layer has also been developed for the MOS capacitors with quantized surface.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128548997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441045
Xiaoguang Gao, Shuping Li, Jingping Zhu, Yuzhou Sun, T. Tang
The properties of tapered-cladding single-mode hemispherical fiber micro-lenses whose radius is larger than twice of the core radius of the fiber are investigated by Monte Carlo simulation. The radial field distribution of the fiber is expressed as a Gaussian distribution. Simulation results show that the least confusion spots and the maximum axial intensity spots are not located at the focal plane of the hemispherical micro-lenses. The influence of the spherical aberration of the lenses on the spot size can not be neglected for micro-lenses with small curvature radius, and the Gaussian beam model typically used in the calculation of fiber micro-lenses is valid only when the radius of the refractive surface is larger than triple of the fiber core radius.
{"title":"Focusing property simulation of tapered-cladding single-mode hemispherical fiber micro-lenses","authors":"Xiaoguang Gao, Shuping Li, Jingping Zhu, Yuzhou Sun, T. Tang","doi":"10.1109/ELECTRO.2009.5441045","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441045","url":null,"abstract":"The properties of tapered-cladding single-mode hemispherical fiber micro-lenses whose radius is larger than twice of the core radius of the fiber are investigated by Monte Carlo simulation. The radial field distribution of the fiber is expressed as a Gaussian distribution. Simulation results show that the least confusion spots and the maximum axial intensity spots are not located at the focal plane of the hemispherical micro-lenses. The influence of the spherical aberration of the lenses on the spot size can not be neglected for micro-lenses with small curvature radius, and the Gaussian beam model typically used in the calculation of fiber micro-lenses is valid only when the radius of the refractive surface is larger than triple of the fiber core radius.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122013798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ELECTRO.2009.5441171
B. N. Kumar, Gaurav Srivastava, A. Verma, K. M. Bhat, S. Chaturvedi, G. Saravanan, R. Muralidharan
This paper describes the study of effect of variation of topological changes on parameters of pseudomorphic HEMTs. Devices with 2 gate fingers, having gate width of 150 µm, source-drain spacing of 4 µm and 3 µm, and with two different gate structures, viz., π and T types were fabricated. On-wafer measurement of S-parameters for different devices was done from 100 MHz to 40 GHz under different bias conditions. Using this data, all the Equivalent Circuit Parameters (ECPs) were then extracted for each device. This method was then used for the calculation of the ECPs of 4 µm and 3 µm spacings, and trends of various parameters were analyzed.
{"title":"Effect of variation of topological changes on the Equivalent Circuit Parameters of pseudomorphic HEMTs","authors":"B. N. Kumar, Gaurav Srivastava, A. Verma, K. M. Bhat, S. Chaturvedi, G. Saravanan, R. Muralidharan","doi":"10.1109/ELECTRO.2009.5441171","DOIUrl":"https://doi.org/10.1109/ELECTRO.2009.5441171","url":null,"abstract":"This paper describes the study of effect of variation of topological changes on parameters of pseudomorphic HEMTs. Devices with 2 gate fingers, having gate width of 150 µm, source-drain spacing of 4 µm and 3 µm, and with two different gate structures, viz., π and T types were fabricated. On-wafer measurement of S-parameters for different devices was done from 100 MHz to 40 GHz under different bias conditions. Using this data, all the Equivalent Circuit Parameters (ECPs) were then extracted for each device. This method was then used for the calculation of the ECPs of 4 µm and 3 µm spacings, and trends of various parameters were analyzed.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116126400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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