Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507800
Pyung Moon, C. E. Kim, Dongjo Kim, Jooho Moon, I. Yun
Inkjet printing process is recently interested in semiconductor display industry because of the advantages such as low-cost, ease of manufacture and diversity of applications. In this paper, the models of inkjet printing process for color filter using displays are investigated using the error back propagation neural networks. The input factors are extracted by prescreening among controlled process variables. The drop diameter and drop velocity are extracted as the output responses to characterize inkjet printing process. The modeling results for the drop diameter and the drop velocity are investigated based on the training and the testing errors. The proposed neural network models are then analyzed using the response surface plot.
{"title":"Ink-jet printing process modeling using neural networks","authors":"Pyung Moon, C. E. Kim, Dongjo Kim, Jooho Moon, I. Yun","doi":"10.1109/IEMT.2008.5507800","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507800","url":null,"abstract":"Inkjet printing process is recently interested in semiconductor display industry because of the advantages such as low-cost, ease of manufacture and diversity of applications. In this paper, the models of inkjet printing process for color filter using displays are investigated using the error back propagation neural networks. The input factors are extracted by prescreening among controlled process variables. The drop diameter and drop velocity are extracted as the output responses to characterize inkjet printing process. The modeling results for the drop diameter and the drop velocity are investigated based on the training and the testing errors. The proposed neural network models are then analyzed using the response surface plot.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507895
K. Cheong, M. C. Ng, A. B. Ismail, L. B. Hussain
This research work investigates the effect of 0.5 wt%, 1.0 wt% and 1.5 wt% Sb addition in 96.8 wt% Sn 2.5 wt% Ag 0.7 wt% Cu. Addition of Sb has shown significant effect on metallography, wettability (using ZnCl2 as flux), thermal properties as well as mechanical properties of the SnAgCu solder. The wettability test has been carried out using Cu as substrate by varying the solder temperature. A good wettability profile has been obtained at 280°C. Differential scanning calorimetry and thermogravimetric analysis have been performed on the solders to determine the melting temperature, melting behaviour and thermal stability of the solders. Results show that Sb addition has not reduced the melting temperature of SnAgCu. The solders show no significant weight loss after heating up to 300°C. Tensile and shear tests have been carried out on soldered copper substrates and all of the solders tested show a ductile fracture mode. The strength of the solder joint is actually a competition in between the ductility of the solder and also the percentage of voids formed in the joint.
{"title":"Effects of Sb on SnAgCu lead-free solder","authors":"K. Cheong, M. C. Ng, A. B. Ismail, L. B. Hussain","doi":"10.1109/IEMT.2008.5507895","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507895","url":null,"abstract":"This research work investigates the effect of 0.5 wt%, 1.0 wt% and 1.5 wt% Sb addition in 96.8 wt% Sn 2.5 wt% Ag 0.7 wt% Cu. Addition of Sb has shown significant effect on metallography, wettability (using ZnCl2 as flux), thermal properties as well as mechanical properties of the SnAgCu solder. The wettability test has been carried out using Cu as substrate by varying the solder temperature. A good wettability profile has been obtained at 280°C. Differential scanning calorimetry and thermogravimetric analysis have been performed on the solders to determine the melting temperature, melting behaviour and thermal stability of the solders. Results show that Sb addition has not reduced the melting temperature of SnAgCu. The solders show no significant weight loss after heating up to 300°C. Tensile and shear tests have been carried out on soldered copper substrates and all of the solders tested show a ductile fracture mode. The strength of the solder joint is actually a competition in between the ductility of the solder and also the percentage of voids formed in the joint.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"315 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133719346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507795
K. Boey, K. Yap, Wai Mun Nq
Today's at-speed testing methodology of the Universal Serial Bus(USB) 2.0 functionality cannot be readily achieved, unless high cost testers are used. Even if high cost testers are used, the success of at-speed testing cannot be guaranteed because of the high-speed interfacing between the off-chip memory, tester and the Device-Under-Test, i.e. the USB2.0. This paper presents a methodology that bridges the gap of the near-end and external loopback methods. The logic built in self test (BIST) proposed encompasses solution to test USB2.0 at-speed, single port and full functional with a low cost tester.
{"title":"Serial interface logic built in self test methodology","authors":"K. Boey, K. Yap, Wai Mun Nq","doi":"10.1109/IEMT.2008.5507795","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507795","url":null,"abstract":"Today's at-speed testing methodology of the Universal Serial Bus(USB) 2.0 functionality cannot be readily achieved, unless high cost testers are used. Even if high cost testers are used, the success of at-speed testing cannot be guaranteed because of the high-speed interfacing between the off-chip memory, tester and the Device-Under-Test, i.e. the USB2.0. This paper presents a methodology that bridges the gap of the near-end and external loopback methods. The logic built in self test (BIST) proposed encompasses solution to test USB2.0 at-speed, single port and full functional with a low cost tester.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507885
New Chin-Ee, T. N. Kumar
This paper presents a new methodology for achieving an exhaustive testing and diagnosis of one of the main FPGA resources, which is the look-up table (LUT). The proposed methodology utilizes a total of log2(2N+2) Walsh configurations to achieve a 100% fault coverage, including all possible stuck-at and bridging faults for N-input LUTs. The Walsh configurations are derived by using Walsh vectors to construct truth tables for the LUT. A fault compression method has been used in order to test more LUTs in parallel and that is designed in combination of Walsh configurations and with a parallel-in-serial-out (PISO) shift register. This method of fault compression also enables fault diagnosis, where the faulty LUTs can be identified. The proposed methodology was implemented on Spartan series FPGAs via an automated approach utilizing a PC through a parallel port communication. The automation program has been written in PERL and C and by utilising Xilinx tools. It is shown from the test results that total testing time required to exhaustively test 200 LUTs for all possible faults is 7.5 minutes. Moreover this method uses minimal input output blocks (IOBs) and provides 100% fault coverage.
{"title":"An approach for exhaustive self testing of LUTs in an FPGA using Walsh configurations","authors":"New Chin-Ee, T. N. Kumar","doi":"10.1109/IEMT.2008.5507885","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507885","url":null,"abstract":"This paper presents a new methodology for achieving an exhaustive testing and diagnosis of one of the main FPGA resources, which is the look-up table (LUT). The proposed methodology utilizes a total of log2(2N+2) Walsh configurations to achieve a 100% fault coverage, including all possible stuck-at and bridging faults for N-input LUTs. The Walsh configurations are derived by using Walsh vectors to construct truth tables for the LUT. A fault compression method has been used in order to test more LUTs in parallel and that is designed in combination of Walsh configurations and with a parallel-in-serial-out (PISO) shift register. This method of fault compression also enables fault diagnosis, where the faulty LUTs can be identified. The proposed methodology was implemented on Spartan series FPGAs via an automated approach utilizing a PC through a parallel port communication. The automation program has been written in PERL and C and by utilising Xilinx tools. It is shown from the test results that total testing time required to exhaustively test 200 LUTs for all possible faults is 7.5 minutes. Moreover this method uses minimal input output blocks (IOBs) and provides 100% fault coverage.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133179056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507842
Wai Ling Lee, Hoon Ngik Low, Hong Shi
In this Paper, we propose a Quick Crosstalk Estimation Methodology by using Crosstalk Superposition Theory. An existing FPGA device package was chosen as the real test case for this study. For both microstrip and stripline, the designs were modeled by using Ansoft SI2D extractor, and the mutual matrix models extracted were used in crosstalk simulation conducted by using Agilent Advance Design System (ADS). The crosstalk simulation results were then compared with the crosstalk results calculated by using the new crosstalk estimation method. We summarize this paper by evaluate the effectiveness and applicability of this proposed methodology in FPGA package with high IO density.
本文提出了一种基于串扰叠加理论的快速串扰估计方法。本研究选择了一个现有的FPGA器件封装作为实际测试用例。采用Ansoft SI2D提取器对微带线和带状线的设计进行建模，并将提取的互矩阵模型用于Agilent Advance Design System (ADS)的串扰仿真。然后将串扰仿真结果与采用新串扰估计方法计算的串扰结果进行了比较。我们通过评估该方法在高IO密度FPGA封装中的有效性和适用性来总结本文。
{"title":"Effective method to simulate Crosstalk between high density IO traces in high performance FPGA packages","authors":"Wai Ling Lee, Hoon Ngik Low, Hong Shi","doi":"10.1109/IEMT.2008.5507842","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507842","url":null,"abstract":"In this Paper, we propose a Quick Crosstalk Estimation Methodology by using Crosstalk Superposition Theory. An existing FPGA device package was chosen as the real test case for this study. For both microstrip and stripline, the designs were modeled by using Ansoft SI2D extractor, and the mutual matrix models extracted were used in crosstalk simulation conducted by using Agilent Advance Design System (ADS). The crosstalk simulation results were then compared with the crosstalk results calculated by using the new crosstalk estimation method. We summarize this paper by evaluate the effectiveness and applicability of this proposed methodology in FPGA package with high IO density.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133814220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507789
Lau Seng Heng, Loh Lee Jeng, Dennis C. Yborde
Cu wire bonding technology has been introduced in semiconductor manufacturing as early as 1980's. Several studies were conducted to resolve the issues and challenges it poses during wire bonding process. Currently, Cu wire interconnect is gaining momentum towards mass adoption from semiconductor manufacturers as the industry has realized its cost benefits as compared to Au wire interconnect. This technology has now improved and matured on low I/O and power devices. With this significant turnaround, Cu wire interconnect is no longer foreign even to devices with fine pitch wire bonding application. This paper discusses the issues and challenges encountered during the development and implementation phases of Cu wire bonding on a high pin count MLP device using high density lead frame with fine pitch application and thin aluminum pad top metallization thickness. It covers the optimization done to eliminate the pad crack damage after crater test and pull test, and the investigations of forming gas settings to eliminate the oxidation of Cu wire. This paper also tackles the challenges and improvement activity done during the pre-production stage. The statistical tools and techniques were used extensively during the wire bond process parameters characterization and optimization while other problem solving techniques were explored in order to understand the risk encountered and mitigate its effects. These efforts have yielded favorable results in addressing the problems encountered during the development and implementation phases. To date, Carsem Malaysia has successfully implemented Cu wire bonding with no problem under proven volume production.
{"title":"Fine pitch Cu wire bonding on thin pad metallization","authors":"Lau Seng Heng, Loh Lee Jeng, Dennis C. Yborde","doi":"10.1109/IEMT.2008.5507789","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507789","url":null,"abstract":"Cu wire bonding technology has been introduced in semiconductor manufacturing as early as 1980's. Several studies were conducted to resolve the issues and challenges it poses during wire bonding process. Currently, Cu wire interconnect is gaining momentum towards mass adoption from semiconductor manufacturers as the industry has realized its cost benefits as compared to Au wire interconnect. This technology has now improved and matured on low I/O and power devices. With this significant turnaround, Cu wire interconnect is no longer foreign even to devices with fine pitch wire bonding application. This paper discusses the issues and challenges encountered during the development and implementation phases of Cu wire bonding on a high pin count MLP device using high density lead frame with fine pitch application and thin aluminum pad top metallization thickness. It covers the optimization done to eliminate the pad crack damage after crater test and pull test, and the investigations of forming gas settings to eliminate the oxidation of Cu wire. This paper also tackles the challenges and improvement activity done during the pre-production stage. The statistical tools and techniques were used extensively during the wire bond process parameters characterization and optimization while other problem solving techniques were explored in order to understand the risk encountered and mitigate its effects. These efforts have yielded favorable results in addressing the problems encountered during the development and implementation phases. To date, Carsem Malaysia has successfully implemented Cu wire bonding with no problem under proven volume production.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507792
Lee Chee How, Thong Kai Choh, L. Guan, L. Khor
The continuous need for higher levels of integration, lower costs and a growing awareness of complete system configuration is the main driving factor behind the System In Package (SIP) solutions. System In Package today has moved from merely multiple dies into a complete fully functional sub-system that contain a combination of multiple die, passive components, Inductors and IC packages. All these are package into a standard IC package format. QFN-SIP package is introduced as a potential alternative to 2 layer substrate based SIP. Its main advantage being lower cost. Assembly processes for SIP is a combination of what used to be strictly SMT and that of conventional semiconductor processes. These process combinations coupled with layout complexity leads to new process challenges and a consideration at it is applied on the QFN package. This paper discusses in detail the overall process challenges and possible solutions that must be taken into account in order to build a QFN-SIP package that is able to withstand a minimum of MSL3 @ 260?C reflow and the rest of the environmental stress tests as required of an IC package.
{"title":"An introduction of QFN-SIP package: Process challenges and technical issues","authors":"Lee Chee How, Thong Kai Choh, L. Guan, L. Khor","doi":"10.1109/IEMT.2008.5507792","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507792","url":null,"abstract":"The continuous need for higher levels of integration, lower costs and a growing awareness of complete system configuration is the main driving factor behind the System In Package (SIP) solutions. System In Package today has moved from merely multiple dies into a complete fully functional sub-system that contain a combination of multiple die, passive components, Inductors and IC packages. All these are package into a standard IC package format. QFN-SIP package is introduced as a potential alternative to 2 layer substrate based SIP. Its main advantage being lower cost. Assembly processes for SIP is a combination of what used to be strictly SMT and that of conventional semiconductor processes. These process combinations coupled with layout complexity leads to new process challenges and a consideration at it is applied on the QFN package. This paper discusses in detail the overall process challenges and possible solutions that must be taken into account in order to build a QFN-SIP package that is able to withstand a minimum of MSL3 @ 260?C reflow and the rest of the environmental stress tests as required of an IC package.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123584781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507812
M. Ong, X. Zhao, B. Zee, P. P. Joman, J. Chin, R. Master
This paper studied the factors causing adhesion failure between lid and adhesive. Adhesive curing mechanism has been experimentally investigated in combination of surface behaviour analysis on lid by using FTIR and XPS. The results showed residue on lid surface caused by low water rinse flow can affect the curing condition.
{"title":"Root cause study on lid adhesion failure","authors":"M. Ong, X. Zhao, B. Zee, P. P. Joman, J. Chin, R. Master","doi":"10.1109/IEMT.2008.5507812","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507812","url":null,"abstract":"This paper studied the factors causing adhesion failure between lid and adhesive. Adhesive curing mechanism has been experimentally investigated in combination of surface behaviour analysis on lid by using FTIR and XPS. The results showed residue on lid surface caused by low water rinse flow can affect the curing condition.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126167424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507882
Shinji Takei, Masaaki Koyama, T. Goto, K. Yasuda
The chip-on-chip (COC) package in which a controller IC chip is adhered to a power MOSFET chip with a polyimide film is described. In the heat cycle test, the polyimide film showed a good performance but the mold resin used was delaminated from the IC chip surface. From the experimental and the thermal stress simulation, we demonstrate that the resin delamination is prevented by the polyimide film with a small thermal expansion coefficient. Thus we have successfully developed the high reliable COC package promising for automotive application.
{"title":"Influence of die adhesion properties on delamination of stacked chip interconnection encapsulated in plastic package","authors":"Shinji Takei, Masaaki Koyama, T. Goto, K. Yasuda","doi":"10.1109/IEMT.2008.5507882","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507882","url":null,"abstract":"The chip-on-chip (COC) package in which a controller IC chip is adhered to a power MOSFET chip with a polyimide film is described. In the heat cycle test, the polyimide film showed a good performance but the mold resin used was delaminated from the IC chip surface. From the experimental and the thermal stress simulation, we demonstrate that the resin delamination is prevented by the polyimide film with a small thermal expansion coefficient. Thus we have successfully developed the high reliable COC package promising for automotive application.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129465444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507878
Koushi Ohta, Masao Toya, K. Yasuda, M. Matsushima, K. Fujimoto
A novel assembly method for electronic devices replacing conventional methods is demanded. Self-organization assembly method using resin containing solder fillers has the possibilities to replace them. The method enables us to form reliable interconnects equal to that of solder bump method with underfilling, through low cost process like that using Anisotropic Conductive Adhesives (ACAs) with flexibility against design change. The process of this method is based on movement, coalescence, and wetting phenomena of the solder fillers. And the coalescence phenomena were focused on. Activator is contained in the resin to eliminate the oxide films around the solder fillers. The particle-size distribution after heating process ensured the effects of the oxides and the activator on the coalescence, which is essential for forming of conductive paths. In-situ observations and temporal change of coalescence frequency revealed that 110°C pre-heating for 4 minutes make the activator eliminate the oxide film enough before melting of the fillers, enables fillers to coalesce well.
{"title":"Observation of solder fillers coalescence in resin for development of self-organization assembly process","authors":"Koushi Ohta, Masao Toya, K. Yasuda, M. Matsushima, K. Fujimoto","doi":"10.1109/IEMT.2008.5507878","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507878","url":null,"abstract":"A novel assembly method for electronic devices replacing conventional methods is demanded. Self-organization assembly method using resin containing solder fillers has the possibilities to replace them. The method enables us to form reliable interconnects equal to that of solder bump method with underfilling, through low cost process like that using Anisotropic Conductive Adhesives (ACAs) with flexibility against design change. The process of this method is based on movement, coalescence, and wetting phenomena of the solder fillers. And the coalescence phenomena were focused on. Activator is contained in the resin to eliminate the oxide films around the solder fillers. The particle-size distribution after heating process ensured the effects of the oxides and the activator on the coalescence, which is essential for forming of conductive paths. In-situ observations and temporal change of coalescence frequency revealed that 110°C pre-heating for 4 minutes make the activator eliminate the oxide film enough before melting of the fillers, enables fillers to coalesce well.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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