Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131488
Sourish S. Sinha, Tzu-Hsuan Cheng, Keval Parmar, D. Hopkins
Extracting the potential of Wide Bandgap (WBG) semiconductor devices needs enhanced electrical and thermal packaging. This paper presents a half-bridge GaN-based Integrated Power Module (IPM) with inclusive gate drivers, driver caps, and decoupling caps for a 500kHz/0.8kW converter application. Presented are the design, fabrication, and experimental characterization of a dense, double-side cooled IPM utilizing an advanced epoxy-resin insulated metal substrate (eIMS) with 120µm thin dielectric for 400V/ 8.3ns high edge-rate switching (i.e. with $dv/dt$ of highest frequency of interest (HFI)). The common mode (CM) capacitance has been optimized. The thermal performance of the module was validated through ANSYS simulation, and the symmetry of the sandwiched substrate structure ensured for symmetric temperature distribution and stress management. An experimental Double Pulse Test (DPT) board with low isolation capacitance was developed to characterize the maximum dynamic performance. Finally, the CM effects on a full-bridge converter application are evaluated to show the efficacy of thin-substrate packaging for application at industrial power levels.
{"title":"Advanced GaN IPM for High-Frequency Converter Applications Enabled with Thin-Substrates","authors":"Sourish S. Sinha, Tzu-Hsuan Cheng, Keval Parmar, D. Hopkins","doi":"10.1109/APEC43580.2023.10131488","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131488","url":null,"abstract":"Extracting the potential of Wide Bandgap (WBG) semiconductor devices needs enhanced electrical and thermal packaging. This paper presents a half-bridge GaN-based Integrated Power Module (IPM) with inclusive gate drivers, driver caps, and decoupling caps for a 500kHz/0.8kW converter application. Presented are the design, fabrication, and experimental characterization of a dense, double-side cooled IPM utilizing an advanced epoxy-resin insulated metal substrate (eIMS) with 120µm thin dielectric for 400V/ 8.3ns high edge-rate switching (i.e. with $dv/dt$ of highest frequency of interest (HFI)). The common mode (CM) capacitance has been optimized. The thermal performance of the module was validated through ANSYS simulation, and the symmetry of the sandwiched substrate structure ensured for symmetric temperature distribution and stress management. An experimental Double Pulse Test (DPT) board with low isolation capacitance was developed to characterize the maximum dynamic performance. Finally, the CM effects on a full-bridge converter application are evaluated to show the efficacy of thin-substrate packaging for application at industrial power levels.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124624061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131557
M. Agredano-Torres, Q. Xu, Mengfan Zhang, L. Söder, A. Cornell
The increase in hydrogen production to support the energy transition in different sectors, such as the steel industry, leads to the utilization of large scale electrolyzers. These electrolyzers have the ability to become a fundamental tool for grid stability providing grid services, especially frequency regulation, for power grids with a high share of renewable energy sources. Alkaline electrolyzers (AELs) have low cost and long lifetime, but their slow dynamics make them unsuitable for fast frequency regulation, especially in case of contingencies. Proton Exchange Membrane electrolyzers (PEMELs) have fast dynamic response to provide grid services, but they have higher costs. This paper proposes a dynamic power allocation control strategy for hybrid electrolyzer systems to provide frequency regulation with reduced cost, making use of advantages of AELs and PEMELs. Simulations and experiments are conducted to verify the proposed control strategy.
{"title":"Dynamic power allocation control for frequency regulation using hybrid electrolyzer systems","authors":"M. Agredano-Torres, Q. Xu, Mengfan Zhang, L. Söder, A. Cornell","doi":"10.1109/APEC43580.2023.10131557","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131557","url":null,"abstract":"The increase in hydrogen production to support the energy transition in different sectors, such as the steel industry, leads to the utilization of large scale electrolyzers. These electrolyzers have the ability to become a fundamental tool for grid stability providing grid services, especially frequency regulation, for power grids with a high share of renewable energy sources. Alkaline electrolyzers (AELs) have low cost and long lifetime, but their slow dynamics make them unsuitable for fast frequency regulation, especially in case of contingencies. Proton Exchange Membrane electrolyzers (PEMELs) have fast dynamic response to provide grid services, but they have higher costs. This paper proposes a dynamic power allocation control strategy for hybrid electrolyzer systems to provide frequency regulation with reduced cost, making use of advantages of AELs and PEMELs. Simulations and experiments are conducted to verify the proposed control strategy.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131601
Feng Jin, Ahmed Nabih, Qiang Li
The planar transformer shows excellent benefits when applied in a high efficiency and high power density LLC converter with increased common-mode (CM) noise caused by the large interwinding capacitances. For the shielding design of a half-bridge (HB) LLC converter with a full-bridge rectifier(FBR), it is essential to find the static-electric-potential (SEP) point in the physical primary or secondary windings. With the proper design of the ground connection of shielding winding, the voltage potential difference between shielding winding and primary/secondary windings is minimized, and the net displacement CM current diminishes. In this paper, the analysis of the SEP point of different transformers for the HBLLC converter with a FBR was discussed, and the net CM current under different ground connection strategies of shielding winding was compared. The CM noises of different strategies are measured based on a 1.5kW HBLLC converter with FBR hardware platform. The EMI measurement results show that it can attenuate the CM noise by 20 dB or more with proper shielding design.
{"title":"Shielding Technique of Planar Transformers to Suppress Common-Mode EMI Noise for LLC Converter with Full Bridge Rectifier","authors":"Feng Jin, Ahmed Nabih, Qiang Li","doi":"10.1109/APEC43580.2023.10131601","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131601","url":null,"abstract":"The planar transformer shows excellent benefits when applied in a high efficiency and high power density LLC converter with increased common-mode (CM) noise caused by the large interwinding capacitances. For the shielding design of a half-bridge (HB) LLC converter with a full-bridge rectifier(FBR), it is essential to find the static-electric-potential (SEP) point in the physical primary or secondary windings. With the proper design of the ground connection of shielding winding, the voltage potential difference between shielding winding and primary/secondary windings is minimized, and the net displacement CM current diminishes. In this paper, the analysis of the SEP point of different transformers for the HBLLC converter with a FBR was discussed, and the net CM current under different ground connection strategies of shielding winding was compared. The CM noises of different strategies are measured based on a 1.5kW HBLLC converter with FBR hardware platform. The EMI measurement results show that it can attenuate the CM noise by 20 dB or more with proper shielding design.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128442270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131589
E. Serban, Cosmin Pondiche, M. Ordonez
Product developments and requirements for wide operational voltage range of bidirectional power converters represent a technical challenge. To overcome the limitations of the current state-of-the-art, the proposed DAB-based converter topology employs a switch combination for parallel-series bridges configuration. The switching nodes of the low-voltage (LV) bridges are separately connected at the two transformer terminals. The dc ports of the two LV-bridges are interconnected through a switch interface which allows them to operate in a parallel-series fashion. The DAB-based converter with the switch interface doubles the voltage utilization range, which enables a broad range of applications for batteries (e.g., 48-V, 120-V). The MOSFET power devices within the DAB-based converter are used within their safe operation specification, while the proposed architecture allows flexible voltage configuration for different types of batteries. Furthermore, the proposed DAB-based converter extends the power capability of the converter to advantageously facilitate applications for energy storage systems (ESS). The experimental results have been performed using a 5kW nominal power DAB-based converter with silicon carbide (SiC) and silicon power MOSFET devices.
{"title":"DAB-based Energy Storage System with Flexible Voltage Configuration and Extended Power Capability","authors":"E. Serban, Cosmin Pondiche, M. Ordonez","doi":"10.1109/APEC43580.2023.10131589","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131589","url":null,"abstract":"Product developments and requirements for wide operational voltage range of bidirectional power converters represent a technical challenge. To overcome the limitations of the current state-of-the-art, the proposed DAB-based converter topology employs a switch combination for parallel-series bridges configuration. The switching nodes of the low-voltage (LV) bridges are separately connected at the two transformer terminals. The dc ports of the two LV-bridges are interconnected through a switch interface which allows them to operate in a parallel-series fashion. The DAB-based converter with the switch interface doubles the voltage utilization range, which enables a broad range of applications for batteries (e.g., 48-V, 120-V). The MOSFET power devices within the DAB-based converter are used within their safe operation specification, while the proposed architecture allows flexible voltage configuration for different types of batteries. Furthermore, the proposed DAB-based converter extends the power capability of the converter to advantageously facilitate applications for energy storage systems (ESS). The experimental results have been performed using a 5kW nominal power DAB-based converter with silicon carbide (SiC) and silicon power MOSFET devices.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131193
Young-Min Go, June-Seok Lee
This paper proposes discontinuous Pulse-Width Modulation (DPWM) method for Vienna rectifier with mitigation of the voltage unbalance in the neutral-point. Vienna rectifier is greatly stable and well-established topology for high power transmission system. However, since Vienna rectifier has the circuit structure that each phase leg and mid-point of dc-link capacitor are connected, DC and AC voltage unbalance can occur at the neutral-point. In the proposed method, fluctuation of the neutral-point voltage is analyzed based on space-vector diagram. Based on the analysis, one of the three-phase reference voltages is selected as clamped phase for suppressing the AC voltage unbalance. Furthermore, DC unbalance can be suppressed by applying the modulation method which considers the difference between dc-link top voltage and bottom voltage. In addition, mathematical prediction of the neutral-point voltage fluctuation is presented for applicating the proposed method regardless of the accuracy of the dc-link voltage sensor. The performance and validity of the proposed method is verified by simulations.
{"title":"Novel DPWM Method with Suppression of the Voltage Unbalance in the Neutral-Point for Vienna Rectifier","authors":"Young-Min Go, June-Seok Lee","doi":"10.1109/APEC43580.2023.10131193","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131193","url":null,"abstract":"This paper proposes discontinuous Pulse-Width Modulation (DPWM) method for Vienna rectifier with mitigation of the voltage unbalance in the neutral-point. Vienna rectifier is greatly stable and well-established topology for high power transmission system. However, since Vienna rectifier has the circuit structure that each phase leg and mid-point of dc-link capacitor are connected, DC and AC voltage unbalance can occur at the neutral-point. In the proposed method, fluctuation of the neutral-point voltage is analyzed based on space-vector diagram. Based on the analysis, one of the three-phase reference voltages is selected as clamped phase for suppressing the AC voltage unbalance. Furthermore, DC unbalance can be suppressed by applying the modulation method which considers the difference between dc-link top voltage and bottom voltage. In addition, mathematical prediction of the neutral-point voltage fluctuation is presented for applicating the proposed method regardless of the accuracy of the dc-link voltage sensor. The performance and validity of the proposed method is verified by simulations.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127272042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131595
K. Neumaier, Vaclav Valenta, Jonathan Chu, Yunpeng Xiao, S. Benczkowski, Bob Marquis, Sameer Yadav, Jonathan Harper, O. Picha, Rajani Thirukoluri, Roveendra Paul, Leon Zhang, Levan Bidzishvili, Thierry Bordignon, J. Victory
This paper describes a holistic design and simulation tool deployed for virtual prototyping of SiC power modules. The power module designer proceeds from concept to virtual prototype in a logical and comprehensive flow. Starting with a simple 2D DXF of the Direct Bond Copper (DBC), the module is designed through die selection and placement, layer and material property declaration, electrical connectivity, and external port definition. Automated 3D model generation is carried out through advanced Ansys scripting techniques. Multiple levels of simulation and model generation are executed through Ansys Icepak, Ansys Q3D, and SPICE. The tool has been validated on multiple onsemi SiC industrial and automotive traction power modules.
{"title":"A Virtual Prototyping System for Silicon-Carbide Power Modules","authors":"K. Neumaier, Vaclav Valenta, Jonathan Chu, Yunpeng Xiao, S. Benczkowski, Bob Marquis, Sameer Yadav, Jonathan Harper, O. Picha, Rajani Thirukoluri, Roveendra Paul, Leon Zhang, Levan Bidzishvili, Thierry Bordignon, J. Victory","doi":"10.1109/APEC43580.2023.10131595","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131595","url":null,"abstract":"This paper describes a holistic design and simulation tool deployed for virtual prototyping of SiC power modules. The power module designer proceeds from concept to virtual prototype in a logical and comprehensive flow. Starting with a simple 2D DXF of the Direct Bond Copper (DBC), the module is designed through die selection and placement, layer and material property declaration, electrical connectivity, and external port definition. Automated 3D model generation is carried out through advanced Ansys scripting techniques. Multiple levels of simulation and model generation are executed through Ansys Icepak, Ansys Q3D, and SPICE. The tool has been validated on multiple onsemi SiC industrial and automotive traction power modules.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127370201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131230
Mohane Selvaraj, A. Dekka, D. Ronanki, A. R. Beig
The advanced multilevel inverters are designed with floating capacitors to increase their output voltage levels. For a reliable operation, these inverters require an efficient voltage balancing algorithm to control the voltage of floating capacitors at rated values. Typically, the balancing algorithm uses redundancy states and is implemented with the conventional multi-carrier pulse width modulation schemes. However, the inverter structure and load power factor affect the balancing ability of the conventional methods. In this article, the balancing algorithm based on a modified multi-carrier based modulation technique is proposed for a new five-level multilevel inverter. In the proposed modified approach, the carriers are distributed non-uniformly throughout the carrier space leading to an output voltage with overlapped voltage steps. With this philosophy, the redundancy states can be utilized effectively in achieving the balancing of floating capacitor voltages under a wide range of power factors. Also, the floating capacitor voltage ripples are minimized compared with the conventional methods. The performance comparison of the proposed and conventional methodologies at different load power factors are presented using the simulation tools.
{"title":"Voltage Balancing of a New Five-Level Multilevel Inverter with a Modified Carrier Pulse Width Modulation Scheme","authors":"Mohane Selvaraj, A. Dekka, D. Ronanki, A. R. Beig","doi":"10.1109/APEC43580.2023.10131230","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131230","url":null,"abstract":"The advanced multilevel inverters are designed with floating capacitors to increase their output voltage levels. For a reliable operation, these inverters require an efficient voltage balancing algorithm to control the voltage of floating capacitors at rated values. Typically, the balancing algorithm uses redundancy states and is implemented with the conventional multi-carrier pulse width modulation schemes. However, the inverter structure and load power factor affect the balancing ability of the conventional methods. In this article, the balancing algorithm based on a modified multi-carrier based modulation technique is proposed for a new five-level multilevel inverter. In the proposed modified approach, the carriers are distributed non-uniformly throughout the carrier space leading to an output voltage with overlapped voltage steps. With this philosophy, the redundancy states can be utilized effectively in achieving the balancing of floating capacitor voltages under a wide range of power factors. Also, the floating capacitor voltage ripples are minimized compared with the conventional methods. The performance comparison of the proposed and conventional methodologies at different load power factors are presented using the simulation tools.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131160
Hemanth Varun Betha, M. Odavic, K. Atallah
Silicon Carbide devices enable high power density power electronic converters due to their lower junction capacitances and higher thermal conductivity. Analytical models of these devices help in estimating the switching dynamics, losses and current/voltage stresses on the devices. The dynamics of SiC MOSFET current during turn ON is impacted by the drain voltage it is switched at, due to the drain induced barrier lowering (DIBL) effect. This is however ignored in the existing analytical models available in the literature. This paper thus proposes and develops a new analytical modelling approach that models this effect by relying only on the datasheet parameters, thereby avoiding the need for expensive and time-consuming experimental methods. Dynamic channel resistance is also modelled as a function of drain voltage. The analysis reveals the impact of drain voltage on damping time of high frequency drain current oscillations during turn ON. An experimental double pulse test (DPT) setup using 1.2kV SiC MOSFET (C3MOOI0602K) and Schottky diode (C4D40120D) is built to verify the findings. Further, the accuracy of the proposed model is compared against the most detailed existing model in the literature.
碳化硅器件由于其较低的结电容和较高的导热性，使高功率密度的电力电子变换器成为可能。这些器件的分析模型有助于估计器件上的开关动力学、损耗和电流/电压应力。由于漏极诱导势垒降低(DIBL)效应，SiC MOSFET在导通过程中的电流动态受到开关处漏极电压的影响。然而，在文献中现有的分析模型中忽略了这一点。因此，本文提出并开发了一种新的分析建模方法，该方法仅依靠数据表参数来模拟这种效应，从而避免了昂贵且耗时的实验方法。动态通道电阻也被建模为漏极电压的函数。分析了漏极电压对高频漏极电流在导通过程中振荡衰减时间的影响。利用1.2kV SiC MOSFET (C3MOOI0602K)和肖特基二极管(C4D40120D)建立了实验双脉冲测试(DPT)装置来验证研究结果。此外，将所提出模型的准确性与文献中最详细的现有模型进行了比较。
{"title":"Analytical modelling of SiC MOSFET based on datasheet parameters considering the dynamic transfer characteristics and channel resistance dependency on the drain voltage","authors":"Hemanth Varun Betha, M. Odavic, K. Atallah","doi":"10.1109/APEC43580.2023.10131160","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131160","url":null,"abstract":"Silicon Carbide devices enable high power density power electronic converters due to their lower junction capacitances and higher thermal conductivity. Analytical models of these devices help in estimating the switching dynamics, losses and current/voltage stresses on the devices. The dynamics of SiC MOSFET current during turn ON is impacted by the drain voltage it is switched at, due to the drain induced barrier lowering (DIBL) effect. This is however ignored in the existing analytical models available in the literature. This paper thus proposes and develops a new analytical modelling approach that models this effect by relying only on the datasheet parameters, thereby avoiding the need for expensive and time-consuming experimental methods. Dynamic channel resistance is also modelled as a function of drain voltage. The analysis reveals the impact of drain voltage on damping time of high frequency drain current oscillations during turn ON. An experimental double pulse test (DPT) setup using 1.2kV SiC MOSFET (C3MOOI0602K) and Schottky diode (C4D40120D) is built to verify the findings. Further, the accuracy of the proposed model is compared against the most detailed existing model in the literature.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131025626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131326
Xiucheng Huang, Yingchuan Lei, Yun Zhou, W. Du, Jason Zhang
With ever increasing demands of smaller size, lighter weight for all forms of consumer electronics, efficient power conversion has always been pursued rigorously. This paper demonstrates an ultra-high efficiency and high power density design of power factor correction (PFC) and asymmetrical half-bridge (AHB) Flyback converter for adapter application. The design procedures, including the optimization of PFC output voltage, AHB flyback transformer, and synchronous rectifier power supply circuit, are presented in detail. A 140W PD3.1 prototype is developed to verify the feasibility of the system design. The prototype achieves 94.5% efficiency at 90Vac and 95.8% at 230Vac which is 1∼2% higher than the state of art product. The power density (exclude case) is more than 35W/in3.
{"title":"An Ultra-High Efficiency High Power Density 140W PD3.1 AC-DC Adapter Using GaN Power ICs","authors":"Xiucheng Huang, Yingchuan Lei, Yun Zhou, W. Du, Jason Zhang","doi":"10.1109/APEC43580.2023.10131326","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131326","url":null,"abstract":"With ever increasing demands of smaller size, lighter weight for all forms of consumer electronics, efficient power conversion has always been pursued rigorously. This paper demonstrates an ultra-high efficiency and high power density design of power factor correction (PFC) and asymmetrical half-bridge (AHB) Flyback converter for adapter application. The design procedures, including the optimization of PFC output voltage, AHB flyback transformer, and synchronous rectifier power supply circuit, are presented in detail. A 140W PD3.1 prototype is developed to verify the feasibility of the system design. The prototype achieves 94.5% efficiency at 90Vac and 95.8% at 230Vac which is 1∼2% higher than the state of art product. The power density (exclude case) is more than 35W/in3.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130653689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-19DOI: 10.1109/APEC43580.2023.10131309
Ahmad Al-Hmoud, Ahmed H. Ismail, Yue Zhao
This work presents the design and development of a high density 200-kW three-phase inverter for traction applications with elevated DC bus voltage, e.g., up to 1.2 kV. A state-of-the-art six-pack 1.7-kV silicon carbide (SiC) power module is used in this design. To achieve a compact system integration and ultra-low power loop inductance, the custom laminated bussing structure is optimized with the detailed design along the method of estimating the parasitic inductance presented in this work. The designs of other key components, such as a compact six-channel gate driver board, are also presented. The inverter prototype was tested at different switching frequencies and dead times to investigate their effect on the performance. The inverter achieved a peak efficiency of 99.3% at 10kHz, and a 43kW/L power density.
{"title":"A High-Density 200-kW All Silicon Carbide Three-Phase Inverter for Traction Applications","authors":"Ahmad Al-Hmoud, Ahmed H. Ismail, Yue Zhao","doi":"10.1109/APEC43580.2023.10131309","DOIUrl":"https://doi.org/10.1109/APEC43580.2023.10131309","url":null,"abstract":"This work presents the design and development of a high density 200-kW three-phase inverter for traction applications with elevated DC bus voltage, e.g., up to 1.2 kV. A state-of-the-art six-pack 1.7-kV silicon carbide (SiC) power module is used in this design. To achieve a compact system integration and ultra-low power loop inductance, the custom laminated bussing structure is optimized with the detailed design along the method of estimating the parasitic inductance presented in this work. The designs of other key components, such as a compact six-channel gate driver board, are also presented. The inverter prototype was tested at different switching frequencies and dead times to investigate their effect on the performance. The inverter achieved a peak efficiency of 99.3% at 10kHz, and a 43kW/L power density.","PeriodicalId":151216,"journal":{"name":"2023 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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