Calvin Ling, Taufik Azahari, M. A. Abas, Fei Chong Ng
This paper investigates voiding issues in the underfilling process of ball grid array (BGA) chip packages under various parameter settings such as chip conveyor speed, valve pressure, temperature, and dispense pattern complicate. The study identifies valve pressure as the primary cause of voiding in large quantity BGA chips, achieving 88.9% in accuracy, supported with the deformation of the valve nozzle. Additionally, the findings reveal that racing effects occurs due to asymmetry of the solder ball array arrangement with percentage difference between the TSAM BGA chips experiments and its simulation counterparts in the range of 0.089% to 3.65%.
{"title":"Correlation Study On Voiding in Underfill of Large Quantity Ball Grid Array Chip Using Machine Learning","authors":"Calvin Ling, Taufik Azahari, M. A. Abas, Fei Chong Ng","doi":"10.1115/1.4065077","DOIUrl":"https://doi.org/10.1115/1.4065077","url":null,"abstract":"\u0000 This paper investigates voiding issues in the underfilling process of ball grid array (BGA) chip packages under various parameter settings such as chip conveyor speed, valve pressure, temperature, and dispense pattern complicate. The study identifies valve pressure as the primary cause of voiding in large quantity BGA chips, achieving 88.9% in accuracy, supported with the deformation of the valve nozzle. Additionally, the findings reveal that racing effects occurs due to asymmetry of the solder ball array arrangement with percentage difference between the TSAM BGA chips experiments and its simulation counterparts in the range of 0.089% to 3.65%.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140236153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hybrid bonding is the technology for interchip ultra-high density interconnect at pitch smaller than 10µm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub 0.5µm has been demonstrated with scaling limitations under exploration beyond sub-0.4µm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly over-viewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing sigulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.
{"title":"Hybrid Bonding for Ultra-High-Density Interconnect","authors":"Mei-Chien Lu","doi":"10.1115/1.4064750","DOIUrl":"https://doi.org/10.1115/1.4064750","url":null,"abstract":"\u0000 Hybrid bonding is the technology for interchip ultra-high density interconnect at pitch smaller than 10µm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub 0.5µm has been demonstrated with scaling limitations under exploration beyond sub-0.4µm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly over-viewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing sigulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139783544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern electronics reliability prediction models require materials-specific failure data across a range of conditions. For solder creep data, Garofalo models are preferred due to their ability to accurately predict performance over a wide temperature range. However, Garofalo data on intermediate solders is sparse, especially regarding performance at cold temperatures. Here, we report on creep phenomena of 83Pb/10Sb/5Sn2Ag (Indalloy 236) and 91.5Sn/8.5Sb (Indalloy 264). Indalloy 236 creep exhibits an activation energy of 83.6 kJ/mol, n=4.46 and a=0.0673, while Indalloy 264 exhibits an activation energy of 57.59 kJ/mol, n=5.89 and a=0.0306 from -20°C to 175°C. X-ray diffraction (XRD), scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) were used to characterize the changes in the alloy phases as a result of the creep. Microstructural analysis indicates that Indalloy 236 experiences void coalescence with high diffusion rates while Indalloy 264 precipitates antimony-rich phases on the grain broundaries.
{"title":"Constant Strain-Rate Garofalo Creep Behavior of Intermediate 83Pb/10Sb/5Sn2Ag and 91.5Sn/8.5Sb Solder Materials","authors":"Eric Stang, Cherish Lesko, Henry Young","doi":"10.1115/1.4064751","DOIUrl":"https://doi.org/10.1115/1.4064751","url":null,"abstract":"\u0000 Modern electronics reliability prediction models require materials-specific failure data across a range of conditions. For solder creep data, Garofalo models are preferred due to their ability to accurately predict performance over a wide temperature range. However, Garofalo data on intermediate solders is sparse, especially regarding performance at cold temperatures. Here, we report on creep phenomena of 83Pb/10Sb/5Sn2Ag (Indalloy 236) and 91.5Sn/8.5Sb (Indalloy 264). Indalloy 236 creep exhibits an activation energy of 83.6 kJ/mol, n=4.46 and a=0.0673, while Indalloy 264 exhibits an activation energy of 57.59 kJ/mol, n=5.89 and a=0.0306 from -20°C to 175°C. X-ray diffraction (XRD), scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) were used to characterize the changes in the alloy phases as a result of the creep. Microstructural analysis indicates that Indalloy 236 experiences void coalescence with high diffusion rates while Indalloy 264 precipitates antimony-rich phases on the grain broundaries.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139842566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern electronics reliability prediction models require materials-specific failure data across a range of conditions. For solder creep data, Garofalo models are preferred due to their ability to accurately predict performance over a wide temperature range. However, Garofalo data on intermediate solders is sparse, especially regarding performance at cold temperatures. Here, we report on creep phenomena of 83Pb/10Sb/5Sn2Ag (Indalloy 236) and 91.5Sn/8.5Sb (Indalloy 264). Indalloy 236 creep exhibits an activation energy of 83.6 kJ/mol, n=4.46 and a=0.0673, while Indalloy 264 exhibits an activation energy of 57.59 kJ/mol, n=5.89 and a=0.0306 from -20°C to 175°C. X-ray diffraction (XRD), scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) were used to characterize the changes in the alloy phases as a result of the creep. Microstructural analysis indicates that Indalloy 236 experiences void coalescence with high diffusion rates while Indalloy 264 precipitates antimony-rich phases on the grain broundaries.
{"title":"Constant Strain-Rate Garofalo Creep Behavior of Intermediate 83Pb/10Sb/5Sn2Ag and 91.5Sn/8.5Sb Solder Materials","authors":"Eric Stang, Cherish Lesko, Henry Young","doi":"10.1115/1.4064751","DOIUrl":"https://doi.org/10.1115/1.4064751","url":null,"abstract":"\u0000 Modern electronics reliability prediction models require materials-specific failure data across a range of conditions. For solder creep data, Garofalo models are preferred due to their ability to accurately predict performance over a wide temperature range. However, Garofalo data on intermediate solders is sparse, especially regarding performance at cold temperatures. Here, we report on creep phenomena of 83Pb/10Sb/5Sn2Ag (Indalloy 236) and 91.5Sn/8.5Sb (Indalloy 264). Indalloy 236 creep exhibits an activation energy of 83.6 kJ/mol, n=4.46 and a=0.0673, while Indalloy 264 exhibits an activation energy of 57.59 kJ/mol, n=5.89 and a=0.0306 from -20°C to 175°C. X-ray diffraction (XRD), scanning electron microscopy (SEM), and energy dispersive spectroscopy (EDS) were used to characterize the changes in the alloy phases as a result of the creep. Microstructural analysis indicates that Indalloy 236 experiences void coalescence with high diffusion rates while Indalloy 264 precipitates antimony-rich phases on the grain broundaries.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139782657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hybrid bonding is the technology for interchip ultra-high density interconnect at pitch smaller than 10µm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub 0.5µm has been demonstrated with scaling limitations under exploration beyond sub-0.4µm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly over-viewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing sigulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.
{"title":"Hybrid Bonding for Ultra-High-Density Interconnect","authors":"Mei-Chien Lu","doi":"10.1115/1.4064750","DOIUrl":"https://doi.org/10.1115/1.4064750","url":null,"abstract":"\u0000 Hybrid bonding is the technology for interchip ultra-high density interconnect at pitch smaller than 10µm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub 0.5µm has been demonstrated with scaling limitations under exploration beyond sub-0.4µm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly over-viewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing sigulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139843426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To meet the requirements of high-precision motion control for optoelectronic packaging platforms, we propose an improved particle swarm optimization and backpropagation (IPSO-BP) neural network for solving the forward kinematics problem (FKP) of platforms. The focus of this paper is the 6-pss flexible parallel platform commonly used in optoelectronic packaging. First, a platform inverse kinematics problem (IKP) based on a flexibility matrix is solved using geometric and vector analysis. The conventional PSO-BP network is then optimized utilizing uniform design (UD), a random learning strategy, and space reduction techniques in FKP. Finally, simulations and experiments demonstrate that the proposed IPSO-BP network for solving the FKP on high-precision optoelectronic packaging platforms is feasible. Compared to BP and PSO-BP, this network has a higher resolution, faster convergence speed, and error control at the submicron level, which satisfies the motion control requirements of the platform at the micron level. This study lays a solid foundation for the production of high-quality devices in optoelectronic packaging.
{"title":"Forward Kinematics Analysis of High-Precision Optoelectronic Packaging Platform","authors":"Ziyang Wang, Haibo Zhou, Linjiao Xiao, Lian Duan","doi":"10.1115/1.4064704","DOIUrl":"https://doi.org/10.1115/1.4064704","url":null,"abstract":"\u0000 To meet the requirements of high-precision motion control for optoelectronic packaging platforms, we propose an improved particle swarm optimization and backpropagation (IPSO-BP) neural network for solving the forward kinematics problem (FKP) of platforms. The focus of this paper is the 6-pss flexible parallel platform commonly used in optoelectronic packaging. First, a platform inverse kinematics problem (IKP) based on a flexibility matrix is solved using geometric and vector analysis. The conventional PSO-BP network is then optimized utilizing uniform design (UD), a random learning strategy, and space reduction techniques in FKP. Finally, simulations and experiments demonstrate that the proposed IPSO-BP network for solving the FKP on high-precision optoelectronic packaging platforms is feasible. Compared to BP and PSO-BP, this network has a higher resolution, faster convergence speed, and error control at the submicron level, which satisfies the motion control requirements of the platform at the micron level. This study lays a solid foundation for the production of high-quality devices in optoelectronic packaging.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139789646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yue Huang, Shangshu Li, Yanpei Gao, Haibin Zhu, Gaoyin He, Xiaohui Xie, Chun Lin
For the first time, finite element analysis (FEA) is applied to the thermal-compression flip-chip process in microelectronics. By adding the bump height non-uniformity and the morphology variance, a common basal line is established. Although the experiment confirms the rate-dependence of indium, an approximation is made to derive the material properties in FEA. The relative standard deviation (RSD) of deformation between the FEA model and the reality is around 1% when predicting the misaligned flip-chip specimen. Besides, the modeled bump characteristic with misalignment coincides with the cross-sectional scanning electron microscope (SEM) picture. The model could be served as a powerful tool to guide the manufacturing process.
{"title":"Modeling the Thermal-Compression Flip-Chip Process by Finite Element Analysis","authors":"Yue Huang, Shangshu Li, Yanpei Gao, Haibin Zhu, Gaoyin He, Xiaohui Xie, Chun Lin","doi":"10.1115/1.4064703","DOIUrl":"https://doi.org/10.1115/1.4064703","url":null,"abstract":"\u0000 For the first time, finite element analysis (FEA) is applied to the thermal-compression flip-chip process in microelectronics. By adding the bump height non-uniformity and the morphology variance, a common basal line is established. Although the experiment confirms the rate-dependence of indium, an approximation is made to derive the material properties in FEA. The relative standard deviation (RSD) of deformation between the FEA model and the reality is around 1% when predicting the misaligned flip-chip specimen. Besides, the modeled bump characteristic with misalignment coincides with the cross-sectional scanning electron microscope (SEM) picture. The model could be served as a powerful tool to guide the manufacturing process.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139790726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yue Huang, Shangshu Li, Yanpei Gao, Haibin Zhu, Gaoyin He, Xiaohui Xie, Chun Lin
For the first time, finite element analysis (FEA) is applied to the thermal-compression flip-chip process in microelectronics. By adding the bump height non-uniformity and the morphology variance, a common basal line is established. Although the experiment confirms the rate-dependence of indium, an approximation is made to derive the material properties in FEA. The relative standard deviation (RSD) of deformation between the FEA model and the reality is around 1% when predicting the misaligned flip-chip specimen. Besides, the modeled bump characteristic with misalignment coincides with the cross-sectional scanning electron microscope (SEM) picture. The model could be served as a powerful tool to guide the manufacturing process.
{"title":"Modeling the Thermal-Compression Flip-Chip Process by Finite Element Analysis","authors":"Yue Huang, Shangshu Li, Yanpei Gao, Haibin Zhu, Gaoyin He, Xiaohui Xie, Chun Lin","doi":"10.1115/1.4064703","DOIUrl":"https://doi.org/10.1115/1.4064703","url":null,"abstract":"\u0000 For the first time, finite element analysis (FEA) is applied to the thermal-compression flip-chip process in microelectronics. By adding the bump height non-uniformity and the morphology variance, a common basal line is established. Although the experiment confirms the rate-dependence of indium, an approximation is made to derive the material properties in FEA. The relative standard deviation (RSD) of deformation between the FEA model and the reality is around 1% when predicting the misaligned flip-chip specimen. Besides, the modeled bump characteristic with misalignment coincides with the cross-sectional scanning electron microscope (SEM) picture. The model could be served as a powerful tool to guide the manufacturing process.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139850361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To meet the requirements of high-precision motion control for optoelectronic packaging platforms, we propose an improved particle swarm optimization and backpropagation (IPSO-BP) neural network for solving the forward kinematics problem (FKP) of platforms. The focus of this paper is the 6-pss flexible parallel platform commonly used in optoelectronic packaging. First, a platform inverse kinematics problem (IKP) based on a flexibility matrix is solved using geometric and vector analysis. The conventional PSO-BP network is then optimized utilizing uniform design (UD), a random learning strategy, and space reduction techniques in FKP. Finally, simulations and experiments demonstrate that the proposed IPSO-BP network for solving the FKP on high-precision optoelectronic packaging platforms is feasible. Compared to BP and PSO-BP, this network has a higher resolution, faster convergence speed, and error control at the submicron level, which satisfies the motion control requirements of the platform at the micron level. This study lays a solid foundation for the production of high-quality devices in optoelectronic packaging.
{"title":"Forward Kinematics Analysis of High-Precision Optoelectronic Packaging Platform","authors":"Ziyang Wang, Haibo Zhou, Linjiao Xiao, Lian Duan","doi":"10.1115/1.4064704","DOIUrl":"https://doi.org/10.1115/1.4064704","url":null,"abstract":"\u0000 To meet the requirements of high-precision motion control for optoelectronic packaging platforms, we propose an improved particle swarm optimization and backpropagation (IPSO-BP) neural network for solving the forward kinematics problem (FKP) of platforms. The focus of this paper is the 6-pss flexible parallel platform commonly used in optoelectronic packaging. First, a platform inverse kinematics problem (IKP) based on a flexibility matrix is solved using geometric and vector analysis. The conventional PSO-BP network is then optimized utilizing uniform design (UD), a random learning strategy, and space reduction techniques in FKP. Finally, simulations and experiments demonstrate that the proposed IPSO-BP network for solving the FKP on high-precision optoelectronic packaging platforms is feasible. Compared to BP and PSO-BP, this network has a higher resolution, faster convergence speed, and error control at the submicron level, which satisfies the motion control requirements of the platform at the micron level. This study lays a solid foundation for the production of high-quality devices in optoelectronic packaging.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139849567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The survivability and reliability of commercial electronic components under very high thermo-mechanical loads are improved using underfilling and potting methods. Potting protects from operating conditions such as moisture, water, or corrosive agents. Furthermore, potting offers damping against shock and vibrations, heat dissipation, and structural support. Being one of the most cost-efficient methods, potting greatly increases reliability and therefore reduces costs for replacements and repairs. It also addresses trapped hot air issues better than other restraint technologies. In potted electronic assemblies, interfacial delamination at the epoxy and PCB interface has been one of the major failure modes. Interfacial delamination happens at the epoxy/PCB interface under dynamic shock loads, which leads to failures at the solder interconnects of the electronic components. Sustained operation and storage at elevated temperatures change the interfacial characteristics at the epoxy/PCB interface. This research is focused on interfacial failure mechanics at epoxy/PCB interfaces with high-temperature isothermal aging. In the selection of epoxy potting material and the reliability assessments of the supplemental restraint systems, fracture parameters such as steady-state strain energy release rate stress and fracture toughness are critical. Rectangular beam specimens of the epoxy/PCB interface are fabricated for different potting compounds and the fracture behavior is studied under quasi-static monotonic three-point and four-point bend loads. One of the main differences between three-point and four-point bend loading is that the maximum bending stress occurs at the midpoint under the point of loading of the specimen in three-point bending, whereas the peak stress is distributed over the section of the specimen between the loading points in four-point bending. Four different potting compounds with diverse properties have been studied. The recommended curing schedule from the manufacturer has been chosen and followed for all the potting compounds. The epoxy/PCB interfacial samples are aged at a high temperature of 100°C for 30 to 180 days. Damage has been assumed to happen at the epoxy/PCB interface under dynamic loads. The critical load of crack initiation for the epoxy/PCB interface has been determined from the experimental findings, and it is used in the computation of fracture toughness values. The fracture toughness values are compared for the various epoxy/PCB systems based on the number of days of thermal aging and the method of flexure testing. A cohesive zone model has been constructed for predominantly mode-I delamination with four-point bend stress to predict the interfacial delamination behavior at the epoxy/PCB interfaces. It has been assumed that the bulk material is linear elastic during the bending load. The cohesive zone has been modeled at the interface, where the interfacial fracture has been assumed to occur. The fracture behavior in
{"title":"Epoxy-PCB Interfacial Fracture Reliability under Three-Point and Four-Point Bend Loading After Sustained Elevated Temperature Exposure","authors":"P. Lall, A. Pandurangan, K. Blecker","doi":"10.1115/1.4064604","DOIUrl":"https://doi.org/10.1115/1.4064604","url":null,"abstract":"\u0000 The survivability and reliability of commercial electronic components under very high thermo-mechanical loads are improved using underfilling and potting methods. Potting protects from operating conditions such as moisture, water, or corrosive agents. Furthermore, potting offers damping against shock and vibrations, heat dissipation, and structural support. Being one of the most cost-efficient methods, potting greatly increases reliability and therefore reduces costs for replacements and repairs. It also addresses trapped hot air issues better than other restraint technologies. In potted electronic assemblies, interfacial delamination at the epoxy and PCB interface has been one of the major failure modes. Interfacial delamination happens at the epoxy/PCB interface under dynamic shock loads, which leads to failures at the solder interconnects of the electronic components. Sustained operation and storage at elevated temperatures change the interfacial characteristics at the epoxy/PCB interface. This research is focused on interfacial failure mechanics at epoxy/PCB interfaces with high-temperature isothermal aging. In the selection of epoxy potting material and the reliability assessments of the supplemental restraint systems, fracture parameters such as steady-state strain energy release rate stress and fracture toughness are critical. Rectangular beam specimens of the epoxy/PCB interface are fabricated for different potting compounds and the fracture behavior is studied under quasi-static monotonic three-point and four-point bend loads. One of the main differences between three-point and four-point bend loading is that the maximum bending stress occurs at the midpoint under the point of loading of the specimen in three-point bending, whereas the peak stress is distributed over the section of the specimen between the loading points in four-point bending. Four different potting compounds with diverse properties have been studied. The recommended curing schedule from the manufacturer has been chosen and followed for all the potting compounds. The epoxy/PCB interfacial samples are aged at a high temperature of 100°C for 30 to 180 days. Damage has been assumed to happen at the epoxy/PCB interface under dynamic loads. The critical load of crack initiation for the epoxy/PCB interface has been determined from the experimental findings, and it is used in the computation of fracture toughness values. The fracture toughness values are compared for the various epoxy/PCB systems based on the number of days of thermal aging and the method of flexure testing. A cohesive zone model has been constructed for predominantly mode-I delamination with four-point bend stress to predict the interfacial delamination behavior at the epoxy/PCB interfaces. It has been assumed that the bulk material is linear elastic during the bending load. The cohesive zone has been modeled at the interface, where the interfacial fracture has been assumed to occur. The fracture behavior in","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139887947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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