Yujui Lin, Tiwei Wei, Wyatt Jason Moy, Hao Chen, M. Gupta, M. Degner, M. Asheghi, A. Mantooth, K. Goodson
A microchannel heat sink integrated with a three-dimensional manifold using Direct Bonded Copper (DBC) is promising for high power density electronics due to the combination of low thermal resistance and reduced pressure drop. However, this requires much progress on the fabrication and high-quality point-contact bonding processes of the microchannel substrate and 3D manifold DBCs. In this study, we have developed processing techniques for surface preparations and high-quality point-contact solder bonding between the two DBC substrates. We utilized chemical polishing followed by electroless plating to prevent excess solder from blocking the microchannels. We performed a parametric study to investigate the impact of bonding time and surface roughness on the tensile strength of the bonding interface. The bonding strength increased from 1.8 MPa to 2.3 MPa as the bonding time increased from 10 to 30 minutes while reducing the surface roughness from Rz = 0.21 to 0.05 µm, resulting in increasing the bonding strength from 0.16 MPa to 2.07 MPa. We successfully tested the microcooler up to the inlet pressure of 70 kPa and pressure drop of 30 kPa, which translates to the tensile strength at the bonding point contacts, which remains well below the 2.30 MPa. We achieved the junction-to-coolant thermal resistance of 0.2 cm2-K/W at chip heat flux of 590 W/cm2. Thus, our study provides an important proof-of-concept demonstration towards enabling high power density modules for power conversion applications.
{"title":"Point-Contact Bonding of Integrated 3D Manifold Microchannel Cooling within Direct Bonded Copper (DBC) Platform","authors":"Yujui Lin, Tiwei Wei, Wyatt Jason Moy, Hao Chen, M. Gupta, M. Degner, M. Asheghi, A. Mantooth, K. Goodson","doi":"10.1115/1.4062924","DOIUrl":"https://doi.org/10.1115/1.4062924","url":null,"abstract":"\u0000 A microchannel heat sink integrated with a three-dimensional manifold using Direct Bonded Copper (DBC) is promising for high power density electronics due to the combination of low thermal resistance and reduced pressure drop. However, this requires much progress on the fabrication and high-quality point-contact bonding processes of the microchannel substrate and 3D manifold DBCs. In this study, we have developed processing techniques for surface preparations and high-quality point-contact solder bonding between the two DBC substrates. We utilized chemical polishing followed by electroless plating to prevent excess solder from blocking the microchannels. We performed a parametric study to investigate the impact of bonding time and surface roughness on the tensile strength of the bonding interface. The bonding strength increased from 1.8 MPa to 2.3 MPa as the bonding time increased from 10 to 30 minutes while reducing the surface roughness from Rz = 0.21 to 0.05 µm, resulting in increasing the bonding strength from 0.16 MPa to 2.07 MPa. We successfully tested the microcooler up to the inlet pressure of 70 kPa and pressure drop of 30 kPa, which translates to the tensile strength at the bonding point contacts, which remains well below the 2.30 MPa. We achieved the junction-to-coolant thermal resistance of 0.2 cm2-K/W at chip heat flux of 590 W/cm2. Thus, our study provides an important proof-of-concept demonstration towards enabling high power density modules for power conversion applications.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42458114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Belhadi, S. Hamasha, Ali Alahmer, Xin Wei, Abdallah Alakayleh
In realistic applications, the solder joint is continually subjected to thermal-mechanical stress due to the difference in the coefficient of thermal expansion (CTE) between the printed circuit board (PCB) substrate and the electronic packaging components. Creep and fatigue processes were the most common causes of failure in electronic assemblies. Under isothermal aging, creep deformation becomes more prominent. The aged microstructure was recognized by intermetallic coarsening and the appearance of intergranular fracture generated by dynamic recrystallization in the bulk solder joint. In this study, the influence of Bi content on the creep behaviors of solder joints was investigated under various aging conditions. Three lead-free solder alloys, including SAC305, SAC-3Bi, and SAC-6Bi, are tested at room temperature. For each alloy, preliminary micro-indentation tests were conducted to define three stress levels for distinct aging conditions. After each test, displacement vs. time data was gathered. A novel approach based on an empirical model was developed to systematically examine the development of the steady state creep rate. A power dependency prediction model was developed to investigate the relationship between creep strain rate and stress levels. The steady-state creep rate of SAC305 is significantly higher than that of SAC-Bi alloys owing to the presence of bismuth (Bi) in the solid solution at room temperature. The creep properties showed less variation after 100 hours of aging. SAC-Bi alloys showed less coarsening of the IMC precipitates after aging than SAC305. In the SAC-Bi solder alloys, combinations of precipitate and solid solution hardening mechanisms were observed, while Ag3Sn particles were the dominant strengthening mechanism in the SAC305 alloy system.
{"title":"Power Law Creep Behavior Model Of 3rd Generation Lead-Free Alloys Considering Isothermal Aging","authors":"M. Belhadi, S. Hamasha, Ali Alahmer, Xin Wei, Abdallah Alakayleh","doi":"10.1115/1.4062894","DOIUrl":"https://doi.org/10.1115/1.4062894","url":null,"abstract":"\u0000 In realistic applications, the solder joint is continually subjected to thermal-mechanical stress due to the difference in the coefficient of thermal expansion (CTE) between the printed circuit board (PCB) substrate and the electronic packaging components. Creep and fatigue processes were the most common causes of failure in electronic assemblies. Under isothermal aging, creep deformation becomes more prominent. The aged microstructure was recognized by intermetallic coarsening and the appearance of intergranular fracture generated by dynamic recrystallization in the bulk solder joint. In this study, the influence of Bi content on the creep behaviors of solder joints was investigated under various aging conditions. Three lead-free solder alloys, including SAC305, SAC-3Bi, and SAC-6Bi, are tested at room temperature. For each alloy, preliminary micro-indentation tests were conducted to define three stress levels for distinct aging conditions. After each test, displacement vs. time data was gathered. A novel approach based on an empirical model was developed to systematically examine the development of the steady state creep rate. A power dependency prediction model was developed to investigate the relationship between creep strain rate and stress levels. The steady-state creep rate of SAC305 is significantly higher than that of SAC-Bi alloys owing to the presence of bismuth (Bi) in the solid solution at room temperature. The creep properties showed less variation after 100 hours of aging. SAC-Bi alloys showed less coarsening of the IMC precipitates after aging than SAC305. In the SAC-Bi solder alloys, combinations of precipitate and solid solution hardening mechanisms were observed, while Ag3Sn particles were the dominant strengthening mechanism in the SAC305 alloy system.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45946068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electronics will experience high and low working temperatures during operations, handling, and storage in severe environments applications such as download drilling, aircraft, and transportation. Temperatures in the vehicle underhood applications can range from -65 to +200 °C. Lead-free solder materials continue to evolve under varying thermal workloads. Material characteristics may deteriorate if operating conditions are harsh or heavy. Nonetheless, lead-free solders are susceptible to high strains, which can lead to electronic device failure. A better understanding of solder alloys is needed to ensure reliable operation in harsh environments. New doped solder alloys have recently been created by adding Ni, Co, Au, P, Ga, Cu, and Sb to SnAgCu (SAC) solder alloys to improve mechanical, thermal, and other qualities. SAC-Q has recently been made using Sn-Ag-Cu and the addition of Bi (SAC+Bi). It was discovered that adding dopants to SAC alloys may enhance mechanical characteristics and reduce aging damage. There is no published data on SAC solder alloys after prolonged storage at high strain rates and low functioning temperatures. The materials characterization of SAC (SAC105 and SAC-Q) solder after extended storage at low working temperatures (-65°C-0 °C) and high strain rates (10-75 per sec) is investigated in this article. To characterize the material constitutive behavior, the Anand Viscoplastic model was utilized to derive 9 Anand parameters from recorded Tensile data. The generated 9 Anand parameters were used to validate the Anand model's reliability. A strong correlation was established between experimental data and Anand's predicted data. The Anand parameters were used in a FE framework to simulate drop events for a ball-grid array package on printed circuit board assembly to calculate hysteresis loop and plastic work density. The plastic work per shock event measures the damage progression of the solder interconnects. Thermal aging effects have been studied in terms of the hysteresis loop and the evolution of PWD.
{"title":"Leadfree Sac Solder Materials Characterization At High Strain Rates At Low Test Temperatures And Drop & Shock Simulation Using Input-G Method","authors":"P. Lall, Vikas Yadav, J. Suhling, D. Locker","doi":"10.1115/1.4062868","DOIUrl":"https://doi.org/10.1115/1.4062868","url":null,"abstract":"\u0000 Electronics will experience high and low working temperatures during operations, handling, and storage in severe environments applications such as download drilling, aircraft, and transportation. Temperatures in the vehicle underhood applications can range from -65 to +200 °C. Lead-free solder materials continue to evolve under varying thermal workloads. Material characteristics may deteriorate if operating conditions are harsh or heavy. Nonetheless, lead-free solders are susceptible to high strains, which can lead to electronic device failure. A better understanding of solder alloys is needed to ensure reliable operation in harsh environments. New doped solder alloys have recently been created by adding Ni, Co, Au, P, Ga, Cu, and Sb to SnAgCu (SAC) solder alloys to improve mechanical, thermal, and other qualities. SAC-Q has recently been made using Sn-Ag-Cu and the addition of Bi (SAC+Bi). It was discovered that adding dopants to SAC alloys may enhance mechanical characteristics and reduce aging damage. There is no published data on SAC solder alloys after prolonged storage at high strain rates and low functioning temperatures. The materials characterization of SAC (SAC105 and SAC-Q) solder after extended storage at low working temperatures (-65°C-0 °C) and high strain rates (10-75 per sec) is investigated in this article. To characterize the material constitutive behavior, the Anand Viscoplastic model was utilized to derive 9 Anand parameters from recorded Tensile data. The generated 9 Anand parameters were used to validate the Anand model's reliability. A strong correlation was established between experimental data and Anand's predicted data. The Anand parameters were used in a FE framework to simulate drop events for a ball-grid array package on printed circuit board assembly to calculate hysteresis loop and plastic work density. The plastic work per shock event measures the damage progression of the solder interconnects. Thermal aging effects have been studied in terms of the hysteresis loop and the evolution of PWD.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45344709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Osman, G. Moreno, Steve Myers, J. Major, Xuhui Feng, S. Narumanchi, Y. Joshi
The next generation of integrated power electronics packages will implement wide-bandgap devices with ultrahigh device heat fluxes. Although jet impingement has received attention for power electronics thermal management, it is not used in commercial electric vehicles (EVs) because of the associated pressure drop and reliability concerns. In this paper, we present a modular thermal management system designed for automotive power electronics. The system achieves superior thermal performance to benchmarked EVs, while adhering to reliability standards and with low pumping power. The system utilizes a low-cost and lightweight plastic manifold to generate jets over an optimized heat sink, which is embedded in the direct-bonded-copper (DBC) substrate. The embedded heat sink concept leverages additive manufacturing to add elliptical pin fins to the DBC substrate. The heat sink geometry is optimized for submerged jet impingement using a unit-cell model and an exhaustive search algorithm. The model predictions are validated using unit-cell experiments. A full-scale power module model is then used to compare the DBC-embedded heat sink against direct DBC cooling and baseplate-integrated heat sinks for single-sided (SS) and double-sided (DS) cooling concepts. Using the SS and DS DBC-embedded cooling concepts, the models predict a thermal resistance that represents a reduction of 75% and 85% compared to the 2015 BMW i3, respectively, for the same water-ethylene glycol inverter flow rate. We have shown that an inverter with a 100-kilo-Watt-per-liter power density is achievable with the proposed design.
{"title":"Automotive Silicon Carbide Power Module Cooling With A Novel Modular Manifold And Embedded Heat Sink","authors":"A. Osman, G. Moreno, Steve Myers, J. Major, Xuhui Feng, S. Narumanchi, Y. Joshi","doi":"10.1115/1.4062869","DOIUrl":"https://doi.org/10.1115/1.4062869","url":null,"abstract":"\u0000 The next generation of integrated power electronics packages will implement wide-bandgap devices with ultrahigh device heat fluxes. Although jet impingement has received attention for power electronics thermal management, it is not used in commercial electric vehicles (EVs) because of the associated pressure drop and reliability concerns. In this paper, we present a modular thermal management system designed for automotive power electronics. The system achieves superior thermal performance to benchmarked EVs, while adhering to reliability standards and with low pumping power. The system utilizes a low-cost and lightweight plastic manifold to generate jets over an optimized heat sink, which is embedded in the direct-bonded-copper (DBC) substrate. The embedded heat sink concept leverages additive manufacturing to add elliptical pin fins to the DBC substrate. The heat sink geometry is optimized for submerged jet impingement using a unit-cell model and an exhaustive search algorithm. The model predictions are validated using unit-cell experiments. A full-scale power module model is then used to compare the DBC-embedded heat sink against direct DBC cooling and baseplate-integrated heat sinks for single-sided (SS) and double-sided (DS) cooling concepts. Using the SS and DS DBC-embedded cooling concepts, the models predict a thermal resistance that represents a reduction of 75% and 85% compared to the 2015 BMW i3, respectively, for the same water-ethylene glycol inverter flow rate. We have shown that an inverter with a 100-kilo-Watt-per-liter power density is achievable with the proposed design.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47551616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The present investigation delves into the failure model of cracking at the Cu/dielectric interface, specifically at the anode end of a copper interconnect that is triggered by electromigration. The study employs the continuous dislocation model to determine the stress field caused by interfacial mass diffusion that exists within and outside of the copper line. Apart from the anticipated tensile or compressive stress on the cathode or anode side, an anomalous stress singularity is identified at the interface between the dielectric layer and the anode end of the copper line. This singular stress distribution leads to cracking in the compressive portion of the dielectric layer at the anode end under the influence of electromigration. The theoretical predictions are in good agreement with experimental data, and a novel failure criterion akin to the stress intensity factor in fracture mechanics is formulated.
{"title":"Interfacial Fracture Caused by Electromigration At Copper Interconnects","authors":"Yuexing Wang, Bofeng Li, Zhifeng Yao, Yao Yao","doi":"10.1115/1.4062828","DOIUrl":"https://doi.org/10.1115/1.4062828","url":null,"abstract":"\u0000 The present investigation delves into the failure model of cracking at the Cu/dielectric interface, specifically at the anode end of a copper interconnect that is triggered by electromigration. The study employs the continuous dislocation model to determine the stress field caused by interfacial mass diffusion that exists within and outside of the copper line. Apart from the anticipated tensile or compressive stress on the cathode or anode side, an anomalous stress singularity is identified at the interface between the dielectric layer and the anode end of the copper line. This singular stress distribution leads to cracking in the compressive portion of the dielectric layer at the anode end under the influence of electromigration. The theoretical predictions are in good agreement with experimental data, and a novel failure criterion akin to the stress intensity factor in fracture mechanics is formulated.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46468616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chip junction temperature is a key factor affecting the normal operation of the chip. The development of integrated circuit technology brings about high integration and low cost, but it also puts forward higher requirements for the cooling system. This paper focuses on the air cooling of the chip, builds a hardware test platform based on MCS-52, the general name of the intel series microcontroller unit, and sets up a mathematical model of the air cooling process of the chip on the MATLAB platform based on the principle of energy conservation, heat transfer theory and finite element method. By proposing the equivalent convective heat transfer coefficient, the thermal resistance of the system can be well estimated. This model can easily realize the joint simulation of chip, heat radiator and control strategy, which overcomes the disadvantage that traditional finite element simulation software are difficult to combine with control strategy. In addition, based on the model, the proportional integral differential (PID) control parameters are automatically optimized, achieving excellent temperature control effect, and proving the feasibility of optimizing the control parameters through the model.
{"title":"Model Establishment of Chip Air Cooling Process and Its Proportional Integral Differential Tuning","authors":"Linmeng Xu, Wanying Zhao, Junhui Li","doi":"10.1115/1.4062530","DOIUrl":"https://doi.org/10.1115/1.4062530","url":null,"abstract":"\u0000 Chip junction temperature is a key factor affecting the normal operation of the chip. The development of integrated circuit technology brings about high integration and low cost, but it also puts forward higher requirements for the cooling system. This paper focuses on the air cooling of the chip, builds a hardware test platform based on MCS-52, the general name of the intel series microcontroller unit, and sets up a mathematical model of the air cooling process of the chip on the MATLAB platform based on the principle of energy conservation, heat transfer theory and finite element method. By proposing the equivalent convective heat transfer coefficient, the thermal resistance of the system can be well estimated. This model can easily realize the joint simulation of chip, heat radiator and control strategy, which overcomes the disadvantage that traditional finite element simulation software are difficult to combine with control strategy. In addition, based on the model, the proportional integral differential (PID) control parameters are automatically optimized, achieving excellent temperature control effect, and proving the feasibility of optimizing the control parameters through the model.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48972644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.
{"title":"Recent Advances And Trends In Chiplet Design And Heterogeneous Integration Packaging","authors":"J. Lau","doi":"10.1115/1.4062529","DOIUrl":"https://doi.org/10.1115/1.4062529","url":null,"abstract":"\u0000 In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48318599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ping Sun, B. Huang, Kui Li, Liang Gong, Chuan-Yong Zhu, Ying Zheng
To solve the thermal management problem in the three-dimensional integrated circuit (3D-IC) with high integration and multi-layer, this paper establishes a 3D-IC interlayer microchannel model with various embedded TSV micro-pin fins to explore the temperature distribution of chips and flow velocity distribution inside the microchannel. The sense amplifier and half adder are selected as the heat source of the memory and processor in the calculation model, and the power densities of the circuit modules are 885 kW/m2 and 1.832 MW/m2 combined with the layout size, respectively. Meanwhile, the effects of the shape and arrangement of TSV micro-pin fins on the flow and heat transfer characteristics are investigated. The result shows that the 1.2:1 diamond micro-pin fin microchannel with staggered arrangement has the best overall flow and heat transfer performance. Compared with the basic circular micro-pin fin with the in-line arrangement, the average Nusselt number of this microchannel is improved by 3.20-3.37 times, and the maximum temperature of chips is controlled at 325.92-312.43 K for Re=628-1819.
{"title":"Coupled Electrical-Thermal-Fluidic Multi-Physics Analysis Of TSV Pin Fin Microchannel In The 3D-Ic","authors":"Ping Sun, B. Huang, Kui Li, Liang Gong, Chuan-Yong Zhu, Ying Zheng","doi":"10.1115/1.4062531","DOIUrl":"https://doi.org/10.1115/1.4062531","url":null,"abstract":"\u0000 To solve the thermal management problem in the three-dimensional integrated circuit (3D-IC) with high integration and multi-layer, this paper establishes a 3D-IC interlayer microchannel model with various embedded TSV micro-pin fins to explore the temperature distribution of chips and flow velocity distribution inside the microchannel. The sense amplifier and half adder are selected as the heat source of the memory and processor in the calculation model, and the power densities of the circuit modules are 885 kW/m2 and 1.832 MW/m2 combined with the layout size, respectively. Meanwhile, the effects of the shape and arrangement of TSV micro-pin fins on the flow and heat transfer characteristics are investigated. The result shows that the 1.2:1 diamond micro-pin fin microchannel with staggered arrangement has the best overall flow and heat transfer performance. Compared with the basic circular micro-pin fin with the in-line arrangement, the average Nusselt number of this microchannel is improved by 3.20-3.37 times, and the maximum temperature of chips is controlled at 325.92-312.43 K for Re=628-1819.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45292970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study describes a novel and unconventional approach for embedding passive SMD components into printed circuit boards. Therefore, passive components whose package size is 0201 are embedded in two types of vias. On the final quality of an embedded passive component, the effects of various technological factors, including tin-lead and lead-free solder pastes, various types and dimensions of vias, various soldering techniques, and sample positions during the reflow process, have been investigated and described. The results show the impact of tin-lead solder paste and polymeric solder paste on the creation of electrical shorts in the embedding of passive components. The application of microvias for the embedding of passive components eliminates the fundamental issues, such as electrical shorts, component dislocation, and the low success rate for creating a reliable solder joint. The proposed method for miniaturizing printed circuit boards by embedding passive components in microvias was verified by experimental results. The reliability of the proposed methodology is further supported by electrical measurements. This study describes an approach suitable to PCB prototyping that makes a negligible contribution to hardware design and electronic technologies.
{"title":"A Contribution to PCBs' Miniaturization by the Vertical Embedding of Passive Components","authors":"Peter Lukacs, Tibor Rovensky, A. Otáhal","doi":"10.1115/1.4062470","DOIUrl":"https://doi.org/10.1115/1.4062470","url":null,"abstract":"\u0000 This study describes a novel and unconventional approach for embedding passive SMD components into printed circuit boards. Therefore, passive components whose package size is 0201 are embedded in two types of vias. On the final quality of an embedded passive component, the effects of various technological factors, including tin-lead and lead-free solder pastes, various types and dimensions of vias, various soldering techniques, and sample positions during the reflow process, have been investigated and described. The results show the impact of tin-lead solder paste and polymeric solder paste on the creation of electrical shorts in the embedding of passive components. The application of microvias for the embedding of passive components eliminates the fundamental issues, such as electrical shorts, component dislocation, and the low success rate for creating a reliable solder joint. The proposed method for miniaturizing printed circuit boards by embedding passive components in microvias was verified by experimental results. The reliability of the proposed methodology is further supported by electrical measurements. This study describes an approach suitable to PCB prototyping that makes a negligible contribution to hardware design and electronic technologies.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49316670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two-Phase Immersion cooling (2PIC) has been proposed as a means of economically increasing overall energy efficiency while accommodating increased chip powers and system-level power density. Designers unfamiliar with Two-phase immersion technology may be unaware of the chip-level thermal performance capabilities of the technology. This performance, in the case of a lidded processor, is quantified as a case-to-fluid thermal resistance, Rcf. This work made use of boiler assemblies comprised of copper plates to which two porous metallic boiling enhancement coatings (BECs) had been applied. These boiler assemblies were applied with conventional thermal grease to a thermal test vehicle (TTV) emulating the Skylake series of 8th Gen Intel® Xeon® CPUs and a thermal test slug (TTS) emulating the AMD EPYCTM processors. Both were tested in saturated 3MTM FluorinertTM FC-3284 fluid. The lowest Rcf=0.020 °C/W was achieved on the TTS at 350W. The paper also includes additional TTS data gathered with different boiler assemblies and Thermal Interface Materials as well as field data in the form of Rcf or junction-to-fluid thermal resistances, Rjf, for different live silicon chips.
{"title":"Chip Level Thermal Performance Measurements in Two-Phase Immersion Cooling","authors":"Jimil M. Shah, Thomas E. Crandall, P. Tuma","doi":"10.1115/1.4062403","DOIUrl":"https://doi.org/10.1115/1.4062403","url":null,"abstract":"\u0000 Two-Phase Immersion cooling (2PIC) has been proposed as a means of economically increasing overall energy efficiency while accommodating increased chip powers and system-level power density. Designers unfamiliar with Two-phase immersion technology may be unaware of the chip-level thermal performance capabilities of the technology. This performance, in the case of a lidded processor, is quantified as a case-to-fluid thermal resistance, Rcf. This work made use of boiler assemblies comprised of copper plates to which two porous metallic boiling enhancement coatings (BECs) had been applied. These boiler assemblies were applied with conventional thermal grease to a thermal test vehicle (TTV) emulating the Skylake series of 8th Gen Intel® Xeon® CPUs and a thermal test slug (TTS) emulating the AMD EPYCTM processors. Both were tested in saturated 3MTM FluorinertTM FC-3284 fluid. The lowest Rcf=0.020 °C/W was achieved on the TTS at 350W. The paper also includes additional TTS data gathered with different boiler assemblies and Thermal Interface Materials as well as field data in the form of Rcf or junction-to-fluid thermal resistances, Rjf, for different live silicon chips.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45519539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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