Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117681
C. Doyen, V. Yon, X. Garros, L. Basset, Tadeu Mota Frutuoso, C. Dagon, C. Diouf, X. Federspiel, V. Millon, F. Monsieur, C. Pribat, D. Roy
Hot carriers injection (HCI) degradation plays an important role in advanced technologies. We carried out an extensive analysis of this degradation mode on 55nm MOS transistors and showed that for large channel lengths, a stress at $V_{G}=V_{D}$ becomes more critical than at $V_{G}= V_{Gibmax}$ condition. This is imputable to an additional degradation mechanism distributed throughout the channel, which likely appears on nitrided samples.
{"title":"Insight Into HCI Reliability on I/O Nitrided Devices","authors":"C. Doyen, V. Yon, X. Garros, L. Basset, Tadeu Mota Frutuoso, C. Dagon, C. Diouf, X. Federspiel, V. Millon, F. Monsieur, C. Pribat, D. Roy","doi":"10.1109/IRPS48203.2023.10117681","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117681","url":null,"abstract":"Hot carriers injection (HCI) degradation plays an important role in advanced technologies. We carried out an extensive analysis of this degradation mode on 55nm MOS transistors and showed that for large channel lengths, a stress at $V_{G}=V_{D}$ becomes more critical than at $V_{G}= V_{Gibmax}$ condition. This is imputable to an additional degradation mechanism distributed throughout the channel, which likely appears on nitrided samples.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117582
Xinwei Yu, Chu Yan, Yaru Ding, Y. Qu, Yi Zhao
In this work, AC time-dependent dielectric breakdown (TDDB) of SOI MOSFETs was systematically investigated with considerable experimental data using various stress patterns. It is confirmed that both the time to breakdown $(mathrm{T}_{text{BD}})$ and hardness of post-breakdown could be improved at GHz frequency. Based on frequency dependence of TDDB lifetime, we propose a comprehensive defect accumulation efficiency $(xi)$ model related to pulse width, helping to predict AC TDDB lifetime. In addition, new failure mechanisms for on-state TDDB are clarified by weakening HCI coupled effect. This study is significant for lifetime estimation of logic devices under dynamic circuit operations.
{"title":"GHz AC to DC TDDB Modeling with Defect Accumulation Efficiency Model","authors":"Xinwei Yu, Chu Yan, Yaru Ding, Y. Qu, Yi Zhao","doi":"10.1109/IRPS48203.2023.10117582","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117582","url":null,"abstract":"In this work, AC time-dependent dielectric breakdown (TDDB) of SOI MOSFETs was systematically investigated with considerable experimental data using various stress patterns. It is confirmed that both the time to breakdown $(mathrm{T}_{text{BD}})$ and hardness of post-breakdown could be improved at GHz frequency. Based on frequency dependence of TDDB lifetime, we propose a comprehensive defect accumulation efficiency $(xi)$ model related to pulse width, helping to predict AC TDDB lifetime. In addition, new failure mechanisms for on-state TDDB are clarified by weakening HCI coupled effect. This study is significant for lifetime estimation of logic devices under dynamic circuit operations.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131699893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117702
E. Brunt, D. Lichtenwalner, J. H. Park, S. Ganguly, J. McPherson
This work explores the lifetime model and failure modes of the 4H-SiC MOS interface in the depletion mode. Unlike accumulation mode TDDB, shorter lifetime and a strong defect dependence are observed in the depletion mode. The 1/E model is found to be a good fit for the observed TDDB lifetime data. Despite having a shorter lifetime than accumulation mode, the modeled lifetimes are sufficient for application deployment.
{"title":"Lifetime Modeling of the 4H-SiC MOS Interface in the HTRB Condition Under the Influence of Screw Dislocations","authors":"E. Brunt, D. Lichtenwalner, J. H. Park, S. Ganguly, J. McPherson","doi":"10.1109/IRPS48203.2023.10117702","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117702","url":null,"abstract":"This work explores the lifetime model and failure modes of the 4H-SiC MOS interface in the depletion mode. Unlike accumulation mode TDDB, shorter lifetime and a strong defect dependence are observed in the depletion mode. The 1/E model is found to be a good fit for the observed TDDB lifetime data. Despite having a shorter lifetime than accumulation mode, the modeled lifetimes are sufficient for application deployment.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132568353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118078
Yishan Wu, Puyang Cai, Zhiwei Liu, P. Ren, Zhigang Ji
The advent of hafnia-based ferroelectric field-effect transistors (FeFETs) prompted the evolution of data-intensive applications, such as multi-bit content addressable memories (MCAMs). Though the identification of FeFET variation sources and the understanding of FeFET retention problems have been discussed in existing literature, the impact of these issues on the FeFET -based MCAM is still not uncovered. Herein, we carried out the investigation on the variability and reliability issues of the FeFET -based MCAM. The threshold voltage ($V_{th}$) variation due to nonuniform ferro electricity results in the long-tailed distribution of delay, thereby limiting the expansion of the MCAM array. The $V_{th}$ shift during retention leads to the accuracy decline, which is more prominent after endurance cycling. Further optimization is required for the MCAM arrays to achieve more accurate and efficient search operation.
{"title":"Towards the understanding of ferroelectric-intrinsic variability and reliability issues on MCAM","authors":"Yishan Wu, Puyang Cai, Zhiwei Liu, P. Ren, Zhigang Ji","doi":"10.1109/IRPS48203.2023.10118078","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118078","url":null,"abstract":"The advent of hafnia-based ferroelectric field-effect transistors (FeFETs) prompted the evolution of data-intensive applications, such as multi-bit content addressable memories (MCAMs). Though the identification of FeFET variation sources and the understanding of FeFET retention problems have been discussed in existing literature, the impact of these issues on the FeFET -based MCAM is still not uncovered. Herein, we carried out the investigation on the variability and reliability issues of the FeFET -based MCAM. The threshold voltage ($V_{th}$) variation due to nonuniform ferro electricity results in the long-tailed distribution of delay, thereby limiting the expansion of the MCAM array. The $V_{th}$ shift during retention leads to the accuracy decline, which is more prominent after endurance cycling. Further optimization is required for the MCAM arrays to achieve more accurate and efficient search operation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128857314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117688
Lina Qu, Shengwei Yang, Ming-Hui He, Rui Fang, Xiaojuan Zhu, Kun Han, Yi He
1/E model is found more appropriate for gate oxide time dependence dielectric breakdown (TDDB) lifetime prediction in CMOS with 6.7 nm SiO2 and poly electrode of 3D NAND technology, instead of widely used E model. It is believed that back-end-of-line process is the key factor contributing to the 1/E model, where hydrogen diffusion is originated from thick SiN and driven by final alloy. And anode hole injection (AHI) may be the dominant physic mechanism of this oxide degradation model. In addition, polarity dependency may be induced by decoupled plasma nitrogen (DPN) process and has no relation to 1/E model.
{"title":"Polarity Dependency and 1/E Model of Gate Oxide TDDB Degradation in 3D NAND","authors":"Lina Qu, Shengwei Yang, Ming-Hui He, Rui Fang, Xiaojuan Zhu, Kun Han, Yi He","doi":"10.1109/IRPS48203.2023.10117688","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117688","url":null,"abstract":"1/E model is found more appropriate for gate oxide time dependence dielectric breakdown (TDDB) lifetime prediction in CMOS with 6.7 nm SiO2 and poly electrode of 3D NAND technology, instead of widely used E model. It is believed that back-end-of-line process is the key factor contributing to the 1/E model, where hydrogen diffusion is originated from thick SiN and driven by final alloy. And anode hole injection (AHI) may be the dominant physic mechanism of this oxide degradation model. In addition, polarity dependency may be induced by decoupled plasma nitrogen (DPN) process and has no relation to 1/E model.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114428074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117908
T. Uemura, Byungjin Chung, Shin-Young Chung, Seungbae Lee, Yuchul Hwang, S. Pae
This paper evaluates alpha-induced soft error rate $boldsymbol{(alpha text{SER})}$ by alpha irradiation test in four different SRAMs and simulation. The test result shows the impact of three factors on $boldsymbol{alpha text{SER}}$: process technology, the number of fins, and fin-pitch. The process technology advancing from 7 nm to 4 nm increases the $boldsymbol{alpha text{SER}}$ by 33%, the #fin change (2-fin to 1-fin) decreases the $boldsymbol{alpha text{SER}}$ by 54%, and the fin-pitch shrinking increases the $boldsymbol{alpha text{SER}}$ by 17%. The simulation results show that the process variation does not contribute to the $boldsymbol{alpha text{SER}}$. The BEOL thickness change can increase the $boldsymbol{alpha text{SER}}$ by 1.24X. This paper also discusses the $boldsymbol{alpha text{SER}}$ trend in SRAM from 130 nm to 4 nm technologies. Overall, the study aims to investigate the impact of process technology and design parameters on $boldsymbol{alpha text{SER}}$ in SRAMs.
{"title":"Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM","authors":"T. Uemura, Byungjin Chung, Shin-Young Chung, Seungbae Lee, Yuchul Hwang, S. Pae","doi":"10.1109/IRPS48203.2023.10117908","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117908","url":null,"abstract":"This paper evaluates alpha-induced soft error rate $boldsymbol{(alpha text{SER})}$ by alpha irradiation test in four different SRAMs and simulation. The test result shows the impact of three factors on $boldsymbol{alpha text{SER}}$: process technology, the number of fins, and fin-pitch. The process technology advancing from 7 nm to 4 nm increases the $boldsymbol{alpha text{SER}}$ by 33%, the #fin change (2-fin to 1-fin) decreases the $boldsymbol{alpha text{SER}}$ by 54%, and the fin-pitch shrinking increases the $boldsymbol{alpha text{SER}}$ by 17%. The simulation results show that the process variation does not contribute to the $boldsymbol{alpha text{SER}}$. The BEOL thickness change can increase the $boldsymbol{alpha text{SER}}$ by 1.24X. This paper also discusses the $boldsymbol{alpha text{SER}}$ trend in SRAM from 130 nm to 4 nm technologies. Overall, the study aims to investigate the impact of process technology and design parameters on $boldsymbol{alpha text{SER}}$ in SRAMs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118025
B. Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, M. Smith, L. Tsau
Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7-nm process. Neutron SER tests across process corners show that the faster process corner SER is up to $2times$ higher than the slower process corner SER in 7-nm and 5-nm FinFETs. The process corner dependence of SER is attributed to differences in propagation delay and single-event transient pulse-widths.
{"title":"Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs","authors":"B. Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, M. Smith, L. Tsau","doi":"10.1109/IRPS48203.2023.10118025","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118025","url":null,"abstract":"Scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7-nm process. Neutron SER tests across process corners show that the faster process corner SER is up to $2times$ higher than the slower process corner SER in 7-nm and 5-nm FinFETs. The process corner dependence of SER is attributed to differences in propagation delay and single-event transient pulse-widths.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115079728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117832
Sara Vecchi, P. Pavan, F. Puglisi
As well known, the implementation of $text{high}-kappa$ dielectrics (e.g., $text{HfO}_{2})$ in nanoscale devices is unavoidable to cope with the device scaling required by the market. Nevertheless, due to the higher defect density compared to $text{SiO}_{2}$, hafnium oxide exhibits stronger and more complex Random Telegraph Noise (RTN), namely one of the most relevant defect-related reliability issues in ultra-thin oxides. However, depending on the device type, $text{HfO}_{2}$ can be characterized by different defect density and therefore leading to a different RTN signals. In particular, in Resistive Random Access Memory (RRAM) devices RTN arises very often but shows a high degree of complexity (e.g., multilevel, anomalous, temporary RTN) and instabilities [3], [4] which hinders its characterization. Conversely, in MOSFETs RTN has a small occurrence and it typically exhibits a simple behavior (i.e., 2-level signal) if detected. In this work, we fully analyze such phenomena in different devices providing a unified and physics-based framework which is also confirmed by experiments. The results of this study will be crucial for the design of new devices and circuits for emerging RTN-based applications, such as True Random Number Generators (TRNGs).
{"title":"A Unified Framework to Explain Random Telegraph Noise Complexity in MOSFETs and RRAMs","authors":"Sara Vecchi, P. Pavan, F. Puglisi","doi":"10.1109/IRPS48203.2023.10117832","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117832","url":null,"abstract":"As well known, the implementation of $text{high}-kappa$ dielectrics (e.g., $text{HfO}_{2})$ in nanoscale devices is unavoidable to cope with the device scaling required by the market. Nevertheless, due to the higher defect density compared to $text{SiO}_{2}$, hafnium oxide exhibits stronger and more complex Random Telegraph Noise (RTN), namely one of the most relevant defect-related reliability issues in ultra-thin oxides. However, depending on the device type, $text{HfO}_{2}$ can be characterized by different defect density and therefore leading to a different RTN signals. In particular, in Resistive Random Access Memory (RRAM) devices RTN arises very often but shows a high degree of complexity (e.g., multilevel, anomalous, temporary RTN) and instabilities [3], [4] which hinders its characterization. Conversely, in MOSFETs RTN has a small occurrence and it typically exhibits a simple behavior (i.e., 2-level signal) if detected. In this work, we fully analyze such phenomena in different devices providing a unified and physics-based framework which is also confirmed by experiments. The results of this study will be crucial for the design of new devices and circuits for emerging RTN-based applications, such as True Random Number Generators (TRNGs).","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116940032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118346
Akhil S. Kumar, M. Uren, Matthew D. Smith, Martin Kuball, J. Parke, H. G. Henry, R. Howell
Accelerated OFF -State stressing of multichannel AlGaN/GaN Superlattice Castellated Field Effect Transistors (SLCFET) with varying dielectric thickness $(d_{i})$ and fin-width $(W_{fi n})$ was studied using noise measurements. As $d_{i}$ increased, the failure mechanism changed from an abrupt breakdown to gradual time dependent dielectric breakdown (TDDB). Smaller $W_{fi n}$ is found to extend lifetime compared to wider $W_{fi n}$ under such stressing condition. Percolation theory and associated trap generation during stressing can explain the observed behavior.
{"title":"Dielectric Thickness and Fin Width Dependent OFF-State Degradation in AlGaN/GaN SLCFETs","authors":"Akhil S. Kumar, M. Uren, Matthew D. Smith, Martin Kuball, J. Parke, H. G. Henry, R. Howell","doi":"10.1109/IRPS48203.2023.10118346","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118346","url":null,"abstract":"Accelerated OFF -State stressing of multichannel AlGaN/GaN Superlattice Castellated Field Effect Transistors (SLCFET) with varying dielectric thickness $(d_{i})$ and fin-width $(W_{fi n})$ was studied using noise measurements. As $d_{i}$ increased, the failure mechanism changed from an abrupt breakdown to gradual time dependent dielectric breakdown (TDDB). Smaller $W_{fi n}$ is found to extend lifetime compared to wider $W_{fi n}$ under such stressing condition. Percolation theory and associated trap generation during stressing can explain the observed behavior.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123567600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118084
E. Mengotti, E. Bianda, D. Baumann, G. Schlottig, F. Canales
SiC-based power MOSFETs have become the major challengers for state-of-the-art Si technology in numerous power electronics applications. In ABB's portfolio, the list of examples includes motor drives, renewable energy conversion, battery energy storage systems and uninterruptable power supplies. The performance advantages of the wide-band-gap semiconductor are multiple and allow a clear size-to-cost benefit at the system level, making the introduction of SiC into selected products meaningful. To fully profit from the technology, the reliability level needs to be at least equivalent to the legacy Si-based solutions. However, the new technology requires new tests that address the relevant and novel failure mechanisms. The approach used by ABB is discussed in this paper. As part of the approach, various tests and exemplary results are presented, such as high voltage, high temperature tests, high dV / dt tests, avalanche ruggedness, repetitive surge current operation and dedicated gate oxide tests, as well as packaging related tests such as power cycling. The results show that manufacturers have gained control over some of the earlier limitations in first generation SiC devices, and that the available standards must evolve to reflect the SiC specific requirements compared to the previous semiconductor technology.
{"title":"Industrial approach to the chip and package reliability of SiC MOSFETs (Invited)","authors":"E. Mengotti, E. Bianda, D. Baumann, G. Schlottig, F. Canales","doi":"10.1109/IRPS48203.2023.10118084","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118084","url":null,"abstract":"SiC-based power MOSFETs have become the major challengers for state-of-the-art Si technology in numerous power electronics applications. In ABB's portfolio, the list of examples includes motor drives, renewable energy conversion, battery energy storage systems and uninterruptable power supplies. The performance advantages of the wide-band-gap semiconductor are multiple and allow a clear size-to-cost benefit at the system level, making the introduction of SiC into selected products meaningful. To fully profit from the technology, the reliability level needs to be at least equivalent to the legacy Si-based solutions. However, the new technology requires new tests that address the relevant and novel failure mechanisms. The approach used by ABB is discussed in this paper. As part of the approach, various tests and exemplary results are presented, such as high voltage, high temperature tests, high dV / dt tests, avalanche ruggedness, repetitive surge current operation and dedicated gate oxide tests, as well as packaging related tests such as power cycling. The results show that manufacturers have gained control over some of the earlier limitations in first generation SiC devices, and that the available standards must evolve to reflect the SiC specific requirements compared to the previous semiconductor technology.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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