Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117917
S. V. Beek, K. Cai, Kaiquan Fan, G. Talmelli, Anna Trovato, N. Jossart, S. Rao, A. Chasin, S. Couet
In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT track underneath the MTJ, causing significant heating of both the track and MTJ. At these elevated temperatures, diffusion mechanisms can cause failure of the MTJ. We find that longer tracks heat up more and can sustain less SOT current. Moreover, applying a voltage $(V_{G})$ on the MTJ during SOT stress can cause MgO breakdown before failure by diffusion occurs. With a failure model, we can predict that breakdown event. This is particularly important in multi-pillar concepts that consist of longer tracks and use $V_{G}$ for selectivity.
{"title":"MTJ degradation in multi-pillar SOT-MRAM with selective writing","authors":"S. V. Beek, K. Cai, Kaiquan Fan, G. Talmelli, Anna Trovato, N. Jossart, S. Rao, A. Chasin, S. Couet","doi":"10.1109/IRPS48203.2023.10117917","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117917","url":null,"abstract":"In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT track underneath the MTJ, causing significant heating of both the track and MTJ. At these elevated temperatures, diffusion mechanisms can cause failure of the MTJ. We find that longer tracks heat up more and can sustain less SOT current. Moreover, applying a voltage $(V_{G})$ on the MTJ during SOT stress can cause MgO breakdown before failure by diffusion occurs. With a failure model, we can predict that breakdown event. This is particularly important in multi-pillar concepts that consist of longer tracks and use $V_{G}$ for selectivity.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128235079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 13-bit radiation-hardened-by-design (RHBD) successive approximation register ADC (SAR-ADC) has been proposed with almost no area overhead. The RHBD SAR-ADC has a differential topology with a couple of radiation detectors, and these radiation detectors are assigned, one for each of the differential data paths. The ADC transforms the topology adaptively from differential to single based on the result of radiation detection for error correction or reduction. Thanks to the error correction or reduction by the Adaptive Topology Transformation (ATT), measurement results show an order of magnitude improvement in cross-section and more than 10 dB SNDR enhancement under over 106 count/cm2 irradiation condition.
{"title":"A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation","authors":"Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa","doi":"10.1109/IRPS48203.2023.10118123","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118123","url":null,"abstract":"A 13-bit radiation-hardened-by-design (RHBD) successive approximation register ADC (SAR-ADC) has been proposed with almost no area overhead. The RHBD SAR-ADC has a differential topology with a couple of radiation detectors, and these radiation detectors are assigned, one for each of the differential data paths. The ADC transforms the topology adaptively from differential to single based on the result of radiation detection for error correction or reduction. Thanks to the error correction or reduction by the Adaptive Topology Transformation (ATT), measurement results show an order of magnitude improvement in cross-section and more than 10 dB SNDR enhancement under over 106 count/cm2 irradiation condition.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127366462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118246
Chi-Wei Wang, Chet Chang, Chang-Chun Lee
Despite of the enlarged area of the fan-out panel-level packaging (FO-PLP), the process-induced warpage may cause a serious yielding problem in the subsequent process and assembly for the package. The finite element analysis (FEA) is proposed in many researches to overcome the problem of time cost. The important issue is the discontinuous model and warpage after the sawing process from panel to strip, and strip to unit package for FEA. In this research, a redistribution layer (RDL) first FO-PLP is presented with integrated multiple scale of package model in FEA analysis. The equivalent materials method and the equivalent stress-free temperature in the process-orientation simulation is applied on RDL. The chemical shrinkage of molding underfill is also concerned. The multipoint constraint method is applied on the boundary of multiple scale model to solve the multiple scale problem with panel and strip. The warpage error between the simulation and experiment are below 10 %.
{"title":"Demonstration on Warpage Estimation Approach Utilized in Fan-Out Panel-Level Packaging Enabled by Multi-Scale Process-Oriented Simulation","authors":"Chi-Wei Wang, Chet Chang, Chang-Chun Lee","doi":"10.1109/IRPS48203.2023.10118246","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118246","url":null,"abstract":"Despite of the enlarged area of the fan-out panel-level packaging (FO-PLP), the process-induced warpage may cause a serious yielding problem in the subsequent process and assembly for the package. The finite element analysis (FEA) is proposed in many researches to overcome the problem of time cost. The important issue is the discontinuous model and warpage after the sawing process from panel to strip, and strip to unit package for FEA. In this research, a redistribution layer (RDL) first FO-PLP is presented with integrated multiple scale of package model in FEA analysis. The equivalent materials method and the equivalent stress-free temperature in the process-orientation simulation is applied on RDL. The chemical shrinkage of molding underfill is also concerned. The multipoint constraint method is applied on the boundary of multiple scale model to solve the multiple scale problem with panel and strip. The warpage error between the simulation and experiment are below 10 %.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129134633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117868
Joung-June Park, G. Yoon, Donghyun Go, Donghwi Kim, Ukju An, Jongwoo Kim, Jungsik Kim, Jeong-Soo Lee
For long-term retention characteristics of 3-D NAND flash memory, a method is proposed to decompose the measured $boldsymbol{V_{T}}$ shift into several charge loss mechanisms, including lateral migration (LM), band-to-trap tunneling (BT), trap-to-band tunneling (TB), and thermal emission (TE). Based on the $Delta boldsymbol{V_{T}}$ of the E-E-E pattern (EEE) at room temperature, the LM mechanisms of the P-E-P pattern (PEP) at high temperature (120 °C) are separated into the LM caused by hole (LMH) and electron (LME), respectively. Finally, the E-P-E pattern (EPE) and PEP are successfully decomposed into LMH, LME, TE, BT, and TB of trapped charges in the nitride layer. The proposed methodology is promising to quantitatively evaluate the charge loss mechanism in 3-D NAND flash memory.
{"title":"Decomposition of Vertical and Lateral Charge Loss in Long-term Retention of 3-D NAND Flash Memory","authors":"Joung-June Park, G. Yoon, Donghyun Go, Donghwi Kim, Ukju An, Jongwoo Kim, Jungsik Kim, Jeong-Soo Lee","doi":"10.1109/IRPS48203.2023.10117868","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117868","url":null,"abstract":"For long-term retention characteristics of 3-D NAND flash memory, a method is proposed to decompose the measured $boldsymbol{V_{T}}$ shift into several charge loss mechanisms, including lateral migration (LM), band-to-trap tunneling (BT), trap-to-band tunneling (TB), and thermal emission (TE). Based on the $Delta boldsymbol{V_{T}}$ of the E-E-E pattern (EEE) at room temperature, the LM mechanisms of the P-E-P pattern (PEP) at high temperature (120 °C) are separated into the LM caused by hole (LMH) and electron (LME), respectively. Finally, the E-P-E pattern (EPE) and PEP are successfully decomposed into LMH, LME, TE, BT, and TB of trapped charges in the nitride layer. The proposed methodology is promising to quantitatively evaluate the charge loss mechanism in 3-D NAND flash memory.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117950
N. K. Kranthi, Yang Xiu, Yang Xiao, R. Sankaralingam
In this work, a unique Human Body Model (HBM) failure is presented in 5V-PMOS multi-finger structures. The failure is sensitive to the multi-bank layout, generally used to achieve higher holding voltage. Missing Transmission Line Pulse (TLP) failure current (It2) scalability is detected with pulse width, in multi-bank structures and a correlation is established with lower HBM failure. A detailed 3D- TCAD analysis approach is used to understand the PMOS turn-on in the single-bank and multi-bank structures, in turn, the It2 scalability for longer pulse width. The obtained insights are used to provide design guidelines for developing robust PMOS devices.
{"title":"Current Scalability Issues in Multi-Bank 5V PMOS ESD structures: Root cause and Design Guideline","authors":"N. K. Kranthi, Yang Xiu, Yang Xiao, R. Sankaralingam","doi":"10.1109/IRPS48203.2023.10117950","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117950","url":null,"abstract":"In this work, a unique Human Body Model (HBM) failure is presented in 5V-PMOS multi-finger structures. The failure is sensitive to the multi-bank layout, generally used to achieve higher holding voltage. Missing Transmission Line Pulse (TLP) failure current (It2) scalability is detected with pulse width, in multi-bank structures and a correlation is established with lower HBM failure. A detailed 3D- TCAD analysis approach is used to understand the PMOS turn-on in the single-bank and multi-bank structures, in turn, the It2 scalability for longer pulse width. The obtained insights are used to provide design guidelines for developing robust PMOS devices.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129266520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118047
T. Narita, D. Kikuta, K. Ito, T. Shoji, Tomohiko Mori, S. Yamaguchi, Y. Kimoto, K. Tomita, M. Kanechika, T. Kondo, T. Uesugi, Jun Kojima, J. Suda, Yoshitaka Nagasato, S. Ikeda, Hiroki Watanabe, M. Kosaki, T. Oka
We focus on reliability issues of gate oxides and $p-n$ junctions to realize vertical GaN metal-oxide-semiconductor field-effect transistors (MOSFETs). An annealed AlSiO gate oxide on GaN displayed a lifetime of over 20 years at 150 °C and suppressed positive bias instability in MOSFETs. The key to high channel mobility and stability under positive gate bias is the interface structure designed to minimize oxide border traps. We also evaluated the reliability of GaN p-n diodes (PNDs) on freestanding GaN substrates with different threading dislocation densities. The reverse leakage for PNDs involving threading dislocations was explained by variable-range hopping, while the reverse leakage for dislocation-free PNDs was dominated by band-to-band tunneling. The fabricated PNDs demonstrated excellent robustness under high-temperature reverse bias. However, after continuous forward current stress, reverse leakage pathways were formed at threading screw dislocations, which should be minimized in future GaN substrates.
{"title":"Reliability issues of gate oxides and $p-n$ junctions for vertical GaN metal–oxide–semiconductor field-effect transistors (Invited)","authors":"T. Narita, D. Kikuta, K. Ito, T. Shoji, Tomohiko Mori, S. Yamaguchi, Y. Kimoto, K. Tomita, M. Kanechika, T. Kondo, T. Uesugi, Jun Kojima, J. Suda, Yoshitaka Nagasato, S. Ikeda, Hiroki Watanabe, M. Kosaki, T. Oka","doi":"10.1109/IRPS48203.2023.10118047","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118047","url":null,"abstract":"We focus on reliability issues of gate oxides and $p-n$ junctions to realize vertical GaN metal-oxide-semiconductor field-effect transistors (MOSFETs). An annealed AlSiO gate oxide on GaN displayed a lifetime of over 20 years at 150 °C and suppressed positive bias instability in MOSFETs. The key to high channel mobility and stability under positive gate bias is the interface structure designed to minimize oxide border traps. We also evaluated the reliability of GaN p-n diodes (PNDs) on freestanding GaN substrates with different threading dislocation densities. The reverse leakage for PNDs involving threading dislocations was explained by variable-range hopping, while the reverse leakage for dislocation-free PNDs was dominated by band-to-band tunneling. The fabricated PNDs demonstrated excellent robustness under high-temperature reverse bias. However, after continuous forward current stress, reverse leakage pathways were formed at threading screw dislocations, which should be minimized in future GaN substrates.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126733223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117889
S. Lee, Nam-Hee Lee, K. W. Lee, J. H. Kim, J. Jin, Y. S. Lee, Y. Hwang, H. S. Kim, S. Pae
The reliability characterization of fabricated 14nm DDR5 DRAMs with On-die Error Correction Code (ECC) and EUV process is presented for the first time. Intrinsic reliability of FEOL and BEOL WLR showed well above 10yrs of lifetime, 125°C. The products demonstrated no fails in high temperature operating lifetime (HTOL) of 1000hrs. The On-Die ECC design improved the single bit error rate by $boldsymbol{10^{-6}}$ times (refresh time $boldsymbol{ > 4mathrm{x}}$). The failure rate, ppm of manufacturing burn-in process confirmed the healthiness of the baseline material and also effectively screen out and monitor any random defects. The presented 14nm DDR5 DRAMs are well in production for the PC segments and have been shipping and qualified for the Server segments.
{"title":"Development and Product Reliability Characterization of Advanced High Speed 14nm DDR5 DRAM with On-die ECC","authors":"S. Lee, Nam-Hee Lee, K. W. Lee, J. H. Kim, J. Jin, Y. S. Lee, Y. Hwang, H. S. Kim, S. Pae","doi":"10.1109/IRPS48203.2023.10117889","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117889","url":null,"abstract":"The reliability characterization of fabricated 14nm DDR5 DRAMs with On-die Error Correction Code (ECC) and EUV process is presented for the first time. Intrinsic reliability of FEOL and BEOL WLR showed well above 10yrs of lifetime, 125°C. The products demonstrated no fails in high temperature operating lifetime (HTOL) of 1000hrs. The On-Die ECC design improved the single bit error rate by $boldsymbol{10^{-6}}$ times (refresh time $boldsymbol{ > 4mathrm{x}}$). The failure rate, ppm of manufacturing burn-in process confirmed the healthiness of the baseline material and also effectively screen out and monitor any random defects. The presented 14nm DDR5 DRAMs are well in production for the PC segments and have been shipping and qualified for the Server segments.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126082809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118116
P. Fiorenza, F. Cordiano, M. Alessandrino, A. Russo, E. Zanetti, M. Saggio, C. Bongiorno, F. Giannazzo, F. Roccaforte
The gate oxide lifetime in 4H-SiC power MOSFETs is typically assessed at fixed and constant gate bias stress, monitoring the time-dependent dielectric breakdown (TDDB). In this work, the TDDB results obtained at three different insulator fields - either for positive and negative values - have been compared at wafer level. The TDDB was measured at 200°C under the following conditions: (i) 3 (positive or negative) gate bias values; (ii) 3 (positive or negative) gate current values; (iii) 3 different insulator fields varying the gate bias stress voltage in each device after propaedeutic capacitance measurements to determine the gate insulator thickness. The three methods gave three lifetime prediction at low oxide field (under standard device operation). The physical explanation of these findings can be found, taking into account the device design across the source-body-JFET junction and the transient trapping phenomena at the SiO2 interface.
{"title":"Consideration on the extrapolation of the low insulator field TDDB in 4H-SiC power MOSFETs","authors":"P. Fiorenza, F. Cordiano, M. Alessandrino, A. Russo, E. Zanetti, M. Saggio, C. Bongiorno, F. Giannazzo, F. Roccaforte","doi":"10.1109/IRPS48203.2023.10118116","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118116","url":null,"abstract":"The gate oxide lifetime in 4H-SiC power MOSFETs is typically assessed at fixed and constant gate bias stress, monitoring the time-dependent dielectric breakdown (TDDB). In this work, the TDDB results obtained at three different insulator fields - either for positive and negative values - have been compared at wafer level. The TDDB was measured at 200°C under the following conditions: (i) 3 (positive or negative) gate bias values; (ii) 3 (positive or negative) gate current values; (iii) 3 different insulator fields varying the gate bias stress voltage in each device after propaedeutic capacitance measurements to determine the gate insulator thickness. The three methods gave three lifetime prediction at low oxide field (under standard device operation). The physical explanation of these findings can be found, taking into account the device design across the source-body-JFET junction and the transient trapping phenomena at the SiO2 interface.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121221493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117979
Subrat Mishra, S. Venkateswarlu, B. Vermeersch, Moritz Brunion, M. Lofrano, D. Abdi, H. Oprins, D. Biswas, O. Zografos, G. Hiblot, G. V. D. Plas, P. Weckx, G. Hellings, J. Myers, F. Catthoor, J. Ryckaert
Surge in compute-demand in consumer products, mobile phones, auto mobiles, datacenters for high performance computing (HPC) applications brings in major thermal challenges. This stems from growth in transistor density over the years and the associated power density increase. Advanced packaging techniques like 2.5D and 3D integration have a compounding effect. Hitting the thermal limits, not only affects the raw performance, power but also limits reliability of the product. Therefore, it has become necessary to foresee appropriate thermal solutions for target applications early in product development phase during thermal/power planning to assess viability of technology choices. In this paper, we assess the temperature distribution & anticipate cooling needs for future thermally-limited SOCs in advanced Angstrom nodes (A14 & A5). Thermal resistance breakdown from multiple sources is carried out to decouple contributions so as to explore possibility of a co-optimization of chip-package-cooling system. Some of the insights from our analysis could aid system software to do thermal aware job scheduling.
{"title":"Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)","authors":"Subrat Mishra, S. Venkateswarlu, B. Vermeersch, Moritz Brunion, M. Lofrano, D. Abdi, H. Oprins, D. Biswas, O. Zografos, G. Hiblot, G. V. D. Plas, P. Weckx, G. Hellings, J. Myers, F. Catthoor, J. Ryckaert","doi":"10.1109/IRPS48203.2023.10117979","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117979","url":null,"abstract":"Surge in compute-demand in consumer products, mobile phones, auto mobiles, datacenters for high performance computing (HPC) applications brings in major thermal challenges. This stems from growth in transistor density over the years and the associated power density increase. Advanced packaging techniques like 2.5D and 3D integration have a compounding effect. Hitting the thermal limits, not only affects the raw performance, power but also limits reliability of the product. Therefore, it has become necessary to foresee appropriate thermal solutions for target applications early in product development phase during thermal/power planning to assess viability of technology choices. In this paper, we assess the temperature distribution & anticipate cooling needs for future thermally-limited SOCs in advanced Angstrom nodes (A14 & A5). Thermal resistance breakdown from multiple sources is carried out to decouple contributions so as to explore possibility of a co-optimization of chip-package-cooling system. Some of the insights from our analysis could aid system software to do thermal aware job scheduling.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123833337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118180
W. Vandendaele, C. Leurquin, R. Lavieville, M. Jaud, A. Viey, R. Gwoziecki, B. Mohamad, E. Nowak, A. Constant, F. Iucolano
In this paper, we review the gate reliability of the GaN MOSc-HEMT as well as the specific method to address the peculiarities of these transistors. The long term forward gate TDDB will be explored showing the impact of the gate recession and gate material on the expected maximum gate oxide field $(mathbf{E_{OX, MAX}})$ at 10 years. The gate related threshold voltage instabilities (pBTI and nBTI) are reviewed showing the interplay between epitaxy material and gate oxide process. Finally, the high drain voltage influence on Vth (HVBTI) is studied through the development of specific and dedicated setup allowing a deeper understanding of the device instabilities during operation.
{"title":"Reliability of GaN MOSc-HEMTs: From TDDB to Threshold Voltage Instabilities (Invited)","authors":"W. Vandendaele, C. Leurquin, R. Lavieville, M. Jaud, A. Viey, R. Gwoziecki, B. Mohamad, E. Nowak, A. Constant, F. Iucolano","doi":"10.1109/IRPS48203.2023.10118180","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118180","url":null,"abstract":"In this paper, we review the gate reliability of the GaN MOSc-HEMT as well as the specific method to address the peculiarities of these transistors. The long term forward gate TDDB will be explored showing the impact of the gate recession and gate material on the expected maximum gate oxide field $(mathbf{E_{OX, MAX}})$ at 10 years. The gate related threshold voltage instabilities (pBTI and nBTI) are reviewed showing the interplay between epitaxy material and gate oxide process. Finally, the high drain voltage influence on Vth (HVBTI) is studied through the development of specific and dedicated setup allowing a deeper understanding of the device instabilities during operation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124867548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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