Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118068
Y. Qu, Chu Yan, Xinwei Yu, Yaru Ding, Yi Zhao
Through tremendous experimental data, this study focuses on the cycle-to-cycle variation (CCV) in ultra-scaled FinFETs at the GHz circuit speed, which is an urgent demand for the reliability community but has seldom been reported so far. The random occupancy of traps and interface states behind CCV was investigated with the different switching speeds and full ${V_{G}, V_{D}}$ bias space. Moreover, we observed the CCV degradation during hot carrier degradation (HCD) and further explored its mechanism based on statistical datasets. This CCV study during HCD is helpful for the reliability variability-aware device/circuit co-design in advanced technology nodes.
{"title":"GHz Cycle-to-Cycle Variation in Ultra-scaled FinFETs: From the Time-Zero to the Aging States","authors":"Y. Qu, Chu Yan, Xinwei Yu, Yaru Ding, Yi Zhao","doi":"10.1109/IRPS48203.2023.10118068","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118068","url":null,"abstract":"Through tremendous experimental data, this study focuses on the cycle-to-cycle variation (CCV) in ultra-scaled FinFETs at the GHz circuit speed, which is an urgent demand for the reliability community but has seldom been reported so far. The random occupancy of traps and interface states behind CCV was investigated with the different switching speeds and full ${V_{G}, V_{D}}$ bias space. Moreover, we observed the CCV degradation during hot carrier degradation (HCD) and further explored its mechanism based on statistical datasets. This CCV study during HCD is helpful for the reliability variability-aware device/circuit co-design in advanced technology nodes.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114269856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118096
Rashmi Saikia, Aseer Ansari, Souvik Mahapatra
Charge loss mechanisms during Data retention (DR) in GAA 3D NAND devices, Inter-cell charge loss of electrons in the Charge Trap Layer (CTL), and In-cell charge loss of electrons from tunnel oxide are modeled and analyzed using a physics-based Activated Barrier Double Well Thermionic Emission (ABDWT) model. The measured data retention characteristics for Solid Pattern (SP), of various distribution, sigma $(sigma)$ of the lower tail of the Cell Voltage Distribution (CVD) has been studied and modeled for various temperatures and programming levels (PL). Checkered pattern (CP) measured long-term data retention characteristics at various temperatures and program levels are modeled for both the loss components. 10 years projection is extrapolated across temperature and programing levels.
利用基于物理的激活势垒双阱热离子发射(ABDWT)模型，对GAA 3D NAND器件中数据保留(DR)过程中的电荷损失机制、电荷阱层(CTL)中电子的胞间电荷损失以及隧道氧化物中电子的胞内电荷损失进行了建模和分析。在不同温度和编程水平(PL)下，研究了不同分布的固态模式(SP)、电池电压分布(CVD)下尾的sigma $(sigma)$的测量数据保留特性，并建立了模型。方格模式(CP)测量的长期数据保留特性在不同的温度和程序水平的损失组件建模。10年的预测是根据温度和编程水平推断出来的。
{"title":"A Physics-based Model for Long Term Data Retention Characteristics in 3D NAND Flash Memory","authors":"Rashmi Saikia, Aseer Ansari, Souvik Mahapatra","doi":"10.1109/IRPS48203.2023.10118096","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118096","url":null,"abstract":"Charge loss mechanisms during Data retention (DR) in GAA 3D NAND devices, Inter-cell charge loss of electrons in the Charge Trap Layer (CTL), and In-cell charge loss of electrons from tunnel oxide are modeled and analyzed using a physics-based Activated Barrier Double Well Thermionic Emission (ABDWT) model. The measured data retention characteristics for Solid Pattern (SP), of various distribution, sigma $(sigma)$ of the lower tail of the Cell Voltage Distribution (CVD) has been studied and modeled for various temperatures and programming levels (PL). Checkered pattern (CP) measured long-term data retention characteristics at various temperatures and program levels are modeled for both the loss components. 10 years projection is extrapolated across temperature and programing levels.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118321
H. Sarbishaei, V. Vashchenko
Degradation of ESD avalanche diodes breakdown voltage (BV) characteristics in electrical overstress (EOS) regimes is observed and studied in BCD process technology. Both walk-in and walk-out effects are studied as a function of device structure parameters. It was shown that, in constant current avalanche stress regime, the level and direction of BV degradation can be controlled by changing the RESURF poly plate. High current breakdown TLP characteristics have been analyzed for the same phenomena
{"title":"ESD Avalanche Diodes Degradation in EOS Regime","authors":"H. Sarbishaei, V. Vashchenko","doi":"10.1109/IRPS48203.2023.10118321","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118321","url":null,"abstract":"Degradation of ESD avalanche diodes breakdown voltage (BV) characteristics in electrical overstress (EOS) regimes is observed and studied in BCD process technology. Both walk-in and walk-out effects are studied as a function of device structure parameters. It was shown that, in constant current avalanche stress regime, the level and direction of BV degradation can be controlled by changing the RESURF poly plate. High current breakdown TLP characteristics have been analyzed for the same phenomena","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118255
R. R. Chaudhuri, Vipin Joshi, Amratansh Gupta, Tanmay Joshi, R. Malik, Mehak Ashraf Mir, Sayak Dutta Gupta, M. Shrivastava
Through this work, a unique substrate temperature dependent evolution of hot electron distribution is reported in GaN HEMTs on C-doped GaN buffer, and its reliability consequences are discussed. With rise in substrate temperature, significant rise in hot electron concentration, its energy, and interaction with buffer traps is observed at the drain edge, in contrast to an expected reduction in hot electron population. A mechanism based on carrier de-trapping and transport to drain is proposed and experimentally validated.
{"title":"Unique Lattice Temperature Dependent Evolution of Hot Electron Distribution in GaN HEMTs on C-doped GaN Buffer and its Reliability Consequences","authors":"R. R. Chaudhuri, Vipin Joshi, Amratansh Gupta, Tanmay Joshi, R. Malik, Mehak Ashraf Mir, Sayak Dutta Gupta, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10118255","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118255","url":null,"abstract":"Through this work, a unique substrate temperature dependent evolution of hot electron distribution is reported in GaN HEMTs on C-doped GaN buffer, and its reliability consequences are discussed. With rise in substrate temperature, significant rise in hot electron concentration, its energy, and interaction with buffer traps is observed at the drain edge, in contrast to an expected reduction in hot electron population. A mechanism based on carrier de-trapping and transport to drain is proposed and experimentally validated.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133722836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117666
D. Worledge
Embedded Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is now a standard foundry offering for embedded non-volatile memory applications at the 28 nm node and below, where it replaces embedded Flash, due to lower development costs. The switch from in-plane to perpendicularly magnetized magnetic materials enabled reliable operation and a scaling path. Write-error-rate is the key reliability challenge for STT-MRAM. While due to fundamental physics, write-error-rate of STT-MRAM can be engineered to meet even aggressive product specifications.
{"title":"Write-error-rate of Spin-Transfer-Torque MRAM (Invited)","authors":"D. Worledge","doi":"10.1109/IRPS48203.2023.10117666","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117666","url":null,"abstract":"Embedded Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is now a standard foundry offering for embedded non-volatile memory applications at the 28 nm node and below, where it replaces embedded Flash, due to lower development costs. The switch from in-plane to perpendicularly magnetized magnetic materials enabled reliable operation and a scaling path. Write-error-rate is the key reliability challenge for STT-MRAM. While due to fundamental physics, write-error-rate of STT-MRAM can be engineered to meet even aggressive product specifications.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124998388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117670
Klodjan Bidaj, Lauriane Gateka, Benjamin Ardaillon
This paper presents a reliability handling innovation for WLCSP product qualification. It improves reliability flow compared with standard chip board (CB) assembled WLCSP solutions. Evidence demonstrates that the concept works across a complete range of reliability stress conditions. Results with the new reliability proposal are confirmed to be similar to other standard CB solutions. This is verified through a full qualification plan on three diffusion lots using reliability trials under different environmental and bias conditions.
{"title":"Innovative reliability solution for WLCSP packages","authors":"Klodjan Bidaj, Lauriane Gateka, Benjamin Ardaillon","doi":"10.1109/IRPS48203.2023.10117670","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117670","url":null,"abstract":"This paper presents a reliability handling innovation for WLCSP product qualification. It improves reliability flow compared with standard chip board (CB) assembled WLCSP solutions. Evidence demonstrates that the concept works across a complete range of reliability stress conditions. Results with the new reliability proposal are confirmed to be similar to other standard CB solutions. This is verified through a full qualification plan on three diffusion lots using reliability trials under different environmental and bias conditions.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133701210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10224769
Jr R. Green, A. Lelis, D. Urciuoli, E. Schroen, D. Habersat
This work describes the dynamic nature of on-resistance in SiC MOSFETs, and explains how this happens whenever large threshold-voltage instabilities occur on the time scale of standard device operation, due to the presence of large numbers of active near-interfacial oxide traps—even in previously-unstressed, as-processed devices.
{"title":"Dynamic On-State Resistance in SiC MOSFETs","authors":"Jr R. Green, A. Lelis, D. Urciuoli, E. Schroen, D. Habersat","doi":"10.1109/IRPS48203.2023.10224769","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10224769","url":null,"abstract":"This work describes the dynamic nature of on-resistance in SiC MOSFETs, and explains how this happens whenever large threshold-voltage instabilities occur on the time scale of standard device operation, due to the presence of large numbers of active near-interfacial oxide traps—even in previously-unstressed, as-processed devices.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128594158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117803
L. Panarella, B. Kaczer, Q. Smets, D. Verreck, T. Schram, D. Cott, D. Lin, S. Tyaginov, I. Asselberghs, C. J. L. Rosa, G. Kar, V. Afanas’ev
The low quality of gate dielectrics deposited on 2D channels and the resulting poor reliability of 2D FETs are major issues that need to be addressed as a high priority. In this work, we compare 300 mm integrated dual-gate WS2 FETs with two different interlayers (SiOx and AlOx) in the top HfO2 -based gate stack by means of hysteresis measurements. The collected data enable the extraction of essential properties of defects in the gate oxide, which are commonly recognized as the main cause of instability of 2D FETs. In particular, the hysteresis width is evaluated as a function of the measurement sweep rate in order to investigate the time constants of the dominant defects in both interlayers. Finally, a new measurement-simulation scheme to extract the energy distribution of defects causing hysteresis is proposed. We observe that defects in AlOx-capped devices have slower capture/emission time constants and much lower energy density approaching the conduction band minimum of the channel than those in SiOx. Therefore, A1Ox reduces hysteresis and improves reliability compared to SiOx.
{"title":"Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs","authors":"L. Panarella, B. Kaczer, Q. Smets, D. Verreck, T. Schram, D. Cott, D. Lin, S. Tyaginov, I. Asselberghs, C. J. L. Rosa, G. Kar, V. Afanas’ev","doi":"10.1109/IRPS48203.2023.10117803","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117803","url":null,"abstract":"The low quality of gate dielectrics deposited on 2D channels and the resulting poor reliability of 2D FETs are major issues that need to be addressed as a high priority. In this work, we compare 300 mm integrated dual-gate WS2 FETs with two different interlayers (SiOx and AlOx) in the top HfO2 -based gate stack by means of hysteresis measurements. The collected data enable the extraction of essential properties of defects in the gate oxide, which are commonly recognized as the main cause of instability of 2D FETs. In particular, the hysteresis width is evaluated as a function of the measurement sweep rate in order to investigate the time constants of the dominant defects in both interlayers. Finally, a new measurement-simulation scheme to extract the energy distribution of defects causing hysteresis is proposed. We observe that defects in AlOx-capped devices have slower capture/emission time constants and much lower energy density approaching the conduction band minimum of the channel than those in SiOx. Therefore, A1Ox reduces hysteresis and improves reliability compared to SiOx.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129229945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the rich internal ion dynamics, memristor-based neuromorphic computing emerges as a non-von Neumann computing paradigm to mimic biological neural networks and achieve high energy efficiency. However, to implement large-scale memristive neural networks, the reliability issue of memristive devices, including artificial synapse, dendrite, and soma, should be properly addressed. In this paper, recent works investigating the physical mechanisms and optimizations of memristive device reliability are presented. In particular, the relaxation effect of $boldsymbol{text{HfO}_{mathrm{x}}}$ -based artificial synapse is alleviated by using a ternary oxide as the thermal enhance layer, the device yield of $boldsymbol{text{TiO}_{mathrm{x}^{-}}}$ based artificial dendrite is improved by proper material selection and interface engineering, and the device variability of $boldsymbol{text{NbO}_{mathrm{x}}}$ -based artificial soma is reduced by nitrogen doping. Furthermore, a bio-inspired dendritic neural network with these three fundamental memristive devices is constructed and simulated to analyze the influence of device reliability. Using these optimized devices, the classification accuracy of the street-view house number dataset can be improved by up to $sim$ 60%. The quantitative requirements of device reliability metrics are also provided as a guideline for future neuromorphic system design and implementation.
{"title":"Reliability of Memristive Devices for High-Performance Neuromorphic Computing: (Invited Paper)","authors":"Yue Xi, Xinyi Li, Junhao Chen, Ruofei Hu, Qingtian Zhang, Zhi-Nian Jiang, Feng Xu, Jianshi Tang","doi":"10.1109/IRPS48203.2023.10118214","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118214","url":null,"abstract":"With the rich internal ion dynamics, memristor-based neuromorphic computing emerges as a non-von Neumann computing paradigm to mimic biological neural networks and achieve high energy efficiency. However, to implement large-scale memristive neural networks, the reliability issue of memristive devices, including artificial synapse, dendrite, and soma, should be properly addressed. In this paper, recent works investigating the physical mechanisms and optimizations of memristive device reliability are presented. In particular, the relaxation effect of $boldsymbol{text{HfO}_{mathrm{x}}}$ -based artificial synapse is alleviated by using a ternary oxide as the thermal enhance layer, the device yield of $boldsymbol{text{TiO}_{mathrm{x}^{-}}}$ based artificial dendrite is improved by proper material selection and interface engineering, and the device variability of $boldsymbol{text{NbO}_{mathrm{x}}}$ -based artificial soma is reduced by nitrogen doping. Furthermore, a bio-inspired dendritic neural network with these three fundamental memristive devices is constructed and simulated to analyze the influence of device reliability. Using these optimized devices, the classification accuracy of the street-view house number dataset can be improved by up to $sim$ 60%. The quantitative requirements of device reliability metrics are also provided as a guideline for future neuromorphic system design and implementation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129424733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118113
Matchima Buddhanoy, B. Ray
In this paper, we propose and experimentally evaluate an electrostatic shielding technique to protect the health of flash memory cells from ionizing radiation effects. The technique is based on pre-programming the memory module instead of irradiating it in the erase condition. We find that erased cells suffer more oxide degradation compared to programmed cells, suggesting pre-programming of memory modules before deploying in radiation-prone environments. We evaluate cell degradation by performing retention test on the irradiated memory chip which reveals significantly quicker charge loss for memory cells that were in the erased state during irradiation.
{"title":"Electrostatic Shielding of NAND Flash Memory from Ionizing Radiation","authors":"Matchima Buddhanoy, B. Ray","doi":"10.1109/IRPS48203.2023.10118113","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118113","url":null,"abstract":"In this paper, we propose and experimentally evaluate an electrostatic shielding technique to protect the health of flash memory cells from ionizing radiation effects. The technique is based on pre-programming the memory module instead of irradiating it in the erase condition. We find that erased cells suffer more oxide degradation compared to programmed cells, suggesting pre-programming of memory modules before deploying in radiation-prone environments. We evaluate cell degradation by performing retention test on the irradiated memory chip which reveals significantly quicker charge loss for memory cells that were in the erased state during irradiation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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