Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117898
M. Pešić, Bastien Beltrando, Tommaso Rollo, C. Zambelli, A. Padovani, R. Micheloni, R. Maji, Lisa Enman, M. Saly, Yang Ho Bae, Jung Bae Kim, D. Yim, L. Larcher
Continuation of the scaling and increase of the storage density of the 3D NAND requires minimization and control of variability sources. Among the various reliability challenges, cross-temperature phenomena are considered as one of the reliability limiting factors of state-of-the-art 3D NAND devices. Starting from hypothesis that cross temperature effects are dominated by polycrystalline channel and retention loss at elevated temperature, we: (1) capture and quantify cell-to-cell variability sources within the Page; (2) provide first material and device driven insight (focusing on polyslicon) and its impact on cross-temperature along the Page and String and (3) link them with fail-bits of TLC-encoded 3D NAND.
3D NAND的持续缩放和存储密度的增加需要最小化和控制可变性源。在各种可靠性挑战中，交叉温度现象被认为是最先进的3D NAND器件可靠性限制因素之一。从交叉温度效应由多晶通道和高温下的保留损失主导的假设出发，我们:(1)捕获并量化Page内细胞间的变异性来源;(2)提供第一种材料和器件驱动的见解(重点是多晶硅)及其对Page和String交叉温度的影响;(3)将它们与tlc编码的3D NAND的故障位联系起来。
{"title":"Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND","authors":"M. Pešić, Bastien Beltrando, Tommaso Rollo, C. Zambelli, A. Padovani, R. Micheloni, R. Maji, Lisa Enman, M. Saly, Yang Ho Bae, Jung Bae Kim, D. Yim, L. Larcher","doi":"10.1109/IRPS48203.2023.10117898","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117898","url":null,"abstract":"Continuation of the scaling and increase of the storage density of the 3D NAND requires minimization and control of variability sources. Among the various reliability challenges, cross-temperature phenomena are considered as one of the reliability limiting factors of state-of-the-art 3D NAND devices. Starting from hypothesis that cross temperature effects are dominated by polycrystalline channel and retention loss at elevated temperature, we: (1) capture and quantify cell-to-cell variability sources within the Page; (2) provide first material and device driven insight (focusing on polyslicon) and its impact on cross-temperature along the Page and String and (3) link them with fail-bits of TLC-encoded 3D NAND.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123996657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117723
Tiang Teck Tan, Yu-Yun Wang, J. Tan, Tian-Li Wu, N. Raghavan, K. Pey
Studies on ferroelectric (FE) device degradation are performed on “woken up” devices. The process of waking up a device is typically done by applying a logarithmically increasing number of pulsed, alternating bipolar switching voltage cycles. However, this method has low resolution in precisely achieving the wake-up state, resulting in ambiguity in the current stage of the life cycle of the device. Furthermore, ferroelectric device performance depends heavily on the spatio-temporal distribution of defects in the device stack, which are very different in the wake-up and fatigue phases of the life cycle. The standard bipolar pulsed stressing scheme as well as asymmetric device structure further complicate the analysis of the effects of voltage stressing on defect drift and subsequent device degradation. Here, we propose a new stressing methodology leveraging on an alternating stress-sense scheme using CVS/RVS and positive-up-negative-down (PUND) waveforms to better control the extent of wake-up in the device. Wake-up and the associated changes to the spatio-temporal mapping of the charged defect concentrations can be more confidently ascertained using the proposed methodology, thereby enabling better understanding of the reliability physics governing wake-up and fatigue for FE devices in the future for lifetime prediction from accelerated life tests.
{"title":"A New Methodology to Precisely Induce Wake-Up for Reliability Assessment of Ferroelectric Devices","authors":"Tiang Teck Tan, Yu-Yun Wang, J. Tan, Tian-Li Wu, N. Raghavan, K. Pey","doi":"10.1109/IRPS48203.2023.10117723","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117723","url":null,"abstract":"Studies on ferroelectric (FE) device degradation are performed on “woken up” devices. The process of waking up a device is typically done by applying a logarithmically increasing number of pulsed, alternating bipolar switching voltage cycles. However, this method has low resolution in precisely achieving the wake-up state, resulting in ambiguity in the current stage of the life cycle of the device. Furthermore, ferroelectric device performance depends heavily on the spatio-temporal distribution of defects in the device stack, which are very different in the wake-up and fatigue phases of the life cycle. The standard bipolar pulsed stressing scheme as well as asymmetric device structure further complicate the analysis of the effects of voltage stressing on defect drift and subsequent device degradation. Here, we propose a new stressing methodology leveraging on an alternating stress-sense scheme using CVS/RVS and positive-up-negative-down (PUND) waveforms to better control the extent of wake-up in the device. Wake-up and the associated changes to the spatio-temporal mapping of the charged defect concentrations can be more confidently ascertained using the proposed methodology, thereby enabling better understanding of the reliability physics governing wake-up and fatigue for FE devices in the future for lifetime prediction from accelerated life tests.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124580008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117903
C. Landon, Lei Jiang, D. Pantuso, I. Meric, K. Komeyli, J. Hicks, Daniel Schroeder
Gate-all-around (GAA) devices continue the technology trends of increased localized thermal confinement and higher performance. We describe the methodology used for localized thermal analysis and data collection of temperature rise on the transistor scale and compare GAA cell thermal resistance to Fin-FET cells. We demonstrate that the implications of GAA on device temperature are not a constraint to realizing the full technology benefits with proper thermal management.
{"title":"Localized thermal effects in Gate-all-around devices","authors":"C. Landon, Lei Jiang, D. Pantuso, I. Meric, K. Komeyli, J. Hicks, Daniel Schroeder","doi":"10.1109/IRPS48203.2023.10117903","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117903","url":null,"abstract":"Gate-all-around (GAA) devices continue the technology trends of increased localized thermal confinement and higher performance. We describe the methodology used for localized thermal analysis and data collection of temperature rise on the transistor scale and compare GAA cell thermal resistance to Fin-FET cells. We demonstrate that the implications of GAA on device temperature are not a constraint to realizing the full technology benefits with proper thermal management.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127813182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reliability of a transparent Ag/indium-gallium-zinc-oxide (InGaZnO)/ITO ReRAM was assessed in terms of its dc-endurance and retention while InGaZnO contained optically active platinum nanodisks (Pt-ND) in it. It was observed that, $lambda mathbf{=500}$ nm can improve margin between HRS and LRS due to localized surface plasmon resonance (LSPR) that creates active surfaces on the Pt-NDs as suitable for chemical reduction of $mathbf{Ag}^{+}$ cations and growth of conductive filament (CF) under SET bias; LSPR also reduces HRS current due to localized electrons around the surfaces of Pt-NDs. On the contrary, CF was unstable during longer $lambda$ (700 nm) interaction with Pt-NDs, due to larger extinction cross sections of large diameter NDs that liberate more hot electrons through non-radiative channels preventing easy reoxidation/dissociation of CF under dc-cycles
{"title":"Reliability of InGaZnO Transparent ReRAM with Optically Active Pt-Nanodisks","authors":"Kavita Vishwakarma, Rishabh Kishore, Suman Gora, Mandeep Jangra, Arnab Datta","doi":"10.1109/IRPS48203.2023.10118092","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118092","url":null,"abstract":"Reliability of a transparent Ag/indium-gallium-zinc-oxide (InGaZnO)/ITO ReRAM was assessed in terms of its dc-endurance and retention while InGaZnO contained optically active platinum nanodisks (Pt-ND) in it. It was observed that, $lambda mathbf{=500}$ nm can improve margin between HRS and LRS due to localized surface plasmon resonance (LSPR) that creates active surfaces on the Pt-NDs as suitable for chemical reduction of $mathbf{Ag}^{+}$ cations and growth of conductive filament (CF) under SET bias; LSPR also reduces HRS current due to localized electrons around the surfaces of Pt-NDs. On the contrary, CF was unstable during longer $lambda$ (700 nm) interaction with Pt-NDs, due to larger extinction cross sections of large diameter NDs that liberate more hot electrons through non-radiative channels preventing easy reoxidation/dissociation of CF under dc-cycles","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121189885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117953
S. Kim, Hyerim Park, Eunyu Choi, Young Han Kim, Dahyub Kim, H. Shim, Shin-Young Chung, Paul Jung
In this paper, we report reliability assessment of the Multi-Bridge-Channel FET (MBCFET) adopted 3nm gate all around (GAA) logic technology in comparison with the 4 and 8nm FinFET logic technologies. A notable improvement on negative bias temperature instability (NBTI) of MBCFET is observed thanks to {100} dominance. Gate oxide time-dependent-dielectric-breakdown (TDDB) of the 3nm MBCFETs is comparable to that of the 4nm and 8nm FinFETs. Self-heat decoupled hot-carrier-injection (HCI) is similar to that of the 4nm FinFETs. Reduced conductance maximum (Gm, max) indicates that HCI degradation of the 3nm MBCFETs is dominated by interface damage mechanism. Middle-of-the-line (MOL) TDDB Weibull distribution shows that the 3nm MBCFETs have shorter time-to-failure (TTF) due to reduced lateral distance from gate to diffusion contact than other FinFET logic technologies. Due to an adoption of self-aligned-contact (SAC), the 3nm MBCFETs have similar behavior on MOL breakdown voltage (Vbd) at various diffusion contact misalignment to the 4nm FinFETs. The 3nm MBCFETs show antenna immunity up to 3x antenna ratio. Lastly, thermal cycle (TC) results indicate that the 3nm GAA logic technology has little lattice-related defects.
{"title":"Reliability Assessment of 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FETs","authors":"S. Kim, Hyerim Park, Eunyu Choi, Young Han Kim, Dahyub Kim, H. Shim, Shin-Young Chung, Paul Jung","doi":"10.1109/IRPS48203.2023.10117953","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117953","url":null,"abstract":"In this paper, we report reliability assessment of the Multi-Bridge-Channel FET (MBCFET) adopted 3nm gate all around (GAA) logic technology in comparison with the 4 and 8nm FinFET logic technologies. A notable improvement on negative bias temperature instability (NBTI) of MBCFET is observed thanks to {100} dominance. Gate oxide time-dependent-dielectric-breakdown (TDDB) of the 3nm MBCFETs is comparable to that of the 4nm and 8nm FinFETs. Self-heat decoupled hot-carrier-injection (HCI) is similar to that of the 4nm FinFETs. Reduced conductance maximum (Gm, max) indicates that HCI degradation of the 3nm MBCFETs is dominated by interface damage mechanism. Middle-of-the-line (MOL) TDDB Weibull distribution shows that the 3nm MBCFETs have shorter time-to-failure (TTF) due to reduced lateral distance from gate to diffusion contact than other FinFET logic technologies. Due to an adoption of self-aligned-contact (SAC), the 3nm MBCFETs have similar behavior on MOL breakdown voltage (Vbd) at various diffusion contact misalignment to the 4nm FinFETs. The 3nm MBCFETs show antenna immunity up to 3x antenna ratio. Lastly, thermal cycle (TC) results indicate that the 3nm GAA logic technology has little lattice-related defects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127562651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117828
Huimei Zhou, Miaomiao Wang, N. Loubet, A. Gaul, Y. Sulehria
NBTI impact from gate stack thermal budget in Gate-All-Around Nanosheet (GAA NS) architecture is presented in this work. Varying effects of post high-k deposition anneal (PDA), spike-anneal (SA), and laser annealing (LSA) are studied in terms of the NBTI-induced threshold voltage shifts. It is observed that the NBTI, gate leakage, and mobility are significantly modulated by interfacial layer (IL) formation and Nitrogen (N) concentration from varying annealing and thermal budget. Optimized thermal process is identified to improve NBTI reliability without mobility and gate leakage degradation.
{"title":"Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type Devices","authors":"Huimei Zhou, Miaomiao Wang, N. Loubet, A. Gaul, Y. Sulehria","doi":"10.1109/IRPS48203.2023.10117828","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117828","url":null,"abstract":"NBTI impact from gate stack thermal budget in Gate-All-Around Nanosheet (GAA NS) architecture is presented in this work. Varying effects of post high-k deposition anneal (PDA), spike-anneal (SA), and laser annealing (LSA) are studied in terms of the NBTI-induced threshold voltage shifts. It is observed that the NBTI, gate leakage, and mobility are significantly modulated by interfacial layer (IL) formation and Nitrogen (N) concentration from varying annealing and thermal budget. Optimized thermal process is identified to improve NBTI reliability without mobility and gate leakage degradation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126624551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118155
L. Laurin, M. Baldo, E. Petroni, G. Samanni, Lorenzo Turconi, A. Motta, M. Borghi, A. Serafini, D. Codegoni, M. Scuderi, S. Ran, A. Claverie, D. Ielmini, R. Annunziata, A. Redaelli
In this work, a comprehensive study of Ge-rich Phase Change Memory set and reset state retention realized by coupling electrical and physical characterizations is presented. The presence of amorphous residuals inside the active region of PCM devices is, for the first time, demonstrated through High Resolution Scanning Transmission Electron Microscopy. The role of such formations was studied by means of electrical character-ization and supported by modeling analysis. By comparing the low and high state resistive behavior the retention physics has been analytically modeled with the same framework for both states.
{"title":"Unveiling Retention Physical Mechanism of Ge-rich GST ePCM Technology","authors":"L. Laurin, M. Baldo, E. Petroni, G. Samanni, Lorenzo Turconi, A. Motta, M. Borghi, A. Serafini, D. Codegoni, M. Scuderi, S. Ran, A. Claverie, D. Ielmini, R. Annunziata, A. Redaelli","doi":"10.1109/IRPS48203.2023.10118155","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118155","url":null,"abstract":"In this work, a comprehensive study of Ge-rich Phase Change Memory set and reset state retention realized by coupling electrical and physical characterizations is presented. The presence of amorphous residuals inside the active region of PCM devices is, for the first time, demonstrated through High Resolution Scanning Transmission Electron Microscopy. The role of such formations was studied by means of electrical character-ization and supported by modeling analysis. By comparing the low and high state resistive behavior the retention physics has been analytically modeled with the same framework for both states.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126181438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117874
M. Frank, Ning Li, M. Rasch, Shubham Jain, Ching-Tzu Chen, R. Muralidhar, Jin P. Han, V. Narayanan, T. Philip, K. Brew, A. Simon, Iqbal Saraf, N. Saulnier, I. Boybat, Stanisław Woźniak, A. Sebastian, P. Narayanan, C. Mackin, An Chen, H. Tsai, G. Burr
Among the emerging approaches for deep learning acceleration, compute-in-memory (CIM) in crossbar arrays, in conjunction with optimized digital computation and communication, is attractive for achieving high execution speeds and energy efficiency. Analog phase-change memory (PCM) is particularly promising for this purpose. However, resistance typically drifts, which can degrade deep learning accuracy over time. Herein, we first discuss drift and noise mitigation by integrating projection liners into analog mushroom-type PCM devices, as well as tradeoffs with dynamic range. We then study their impact on inference accuracy for the Transformer-based language model BERT. We find that accuracy loss after extended drift can be minimal with an optimized mapping of weights to cells comprising two pairs of liner PCM devices of varying significance. Finally, we address the impact of drift on energy consumption during inference through a combination of drift, circuit, and architecture simulations. For a range of typical drift coefficients, we show that the peak vector-matrix multiplication (VMM) energy efficiency of a recently proposed heterogeneous CIM accelerator in 14 nm technology can increase by 3% to 15% over the course of one day to ten years. For convolutional neural network (CNN), long short-term memory (LSTM) and Transformer benchmarks, the increase in sustained energy efficiency remains below 10%, being greatest for models dominated by analog computation. Longer VMM integration times increase the energy impact of drift.
{"title":"Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)","authors":"M. Frank, Ning Li, M. Rasch, Shubham Jain, Ching-Tzu Chen, R. Muralidhar, Jin P. Han, V. Narayanan, T. Philip, K. Brew, A. Simon, Iqbal Saraf, N. Saulnier, I. Boybat, Stanisław Woźniak, A. Sebastian, P. Narayanan, C. Mackin, An Chen, H. Tsai, G. Burr","doi":"10.1109/IRPS48203.2023.10117874","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117874","url":null,"abstract":"Among the emerging approaches for deep learning acceleration, compute-in-memory (CIM) in crossbar arrays, in conjunction with optimized digital computation and communication, is attractive for achieving high execution speeds and energy efficiency. Analog phase-change memory (PCM) is particularly promising for this purpose. However, resistance typically drifts, which can degrade deep learning accuracy over time. Herein, we first discuss drift and noise mitigation by integrating projection liners into analog mushroom-type PCM devices, as well as tradeoffs with dynamic range. We then study their impact on inference accuracy for the Transformer-based language model BERT. We find that accuracy loss after extended drift can be minimal with an optimized mapping of weights to cells comprising two pairs of liner PCM devices of varying significance. Finally, we address the impact of drift on energy consumption during inference through a combination of drift, circuit, and architecture simulations. For a range of typical drift coefficients, we show that the peak vector-matrix multiplication (VMM) energy efficiency of a recently proposed heterogeneous CIM accelerator in 14 nm technology can increase by 3% to 15% over the course of one day to ten years. For convolutional neural network (CNN), long short-term memory (LSTM) and Transformer benchmarks, the increase in sustained energy efficiency remains below 10%, being greatest for models dominated by analog computation. Longer VMM integration times increase the energy impact of drift.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117720
J. Mendoza, Jimmy-Bao Le, C. Kim, H. Lin
This paper reports new methods of detecting damages and failures in packaging interconnects in fully packaged devices with sufficient sensitivity and selectivity for damages in interconnects. Exploration on various electrical methods leads to the conclusion that a few electrical measurement techniques, especially one using a low frequency AC signal, may provide effective mechanism of detecting the damages under interest. Impedance and derived parameters such as capacitance and inductance show sensitivity to silicon-package-interaction damages, with satisfactory immunity to parasitic signals present in fully assembled/packaged test chips such as the probe/pad contact resistance and stray capacitance from various sources. Two highlighting examples based on the “open circuit test pattern” are introduced in this paper to demonstrate the effectiveness of developed methods. The first is the damage detection in the high resistance open circuit pattern, which consists of small metal serpentines strategically placed on the failure prone places in BEOL of Si chip. Small damage develop in the metal serpentine makes the circuits to produce LC resonance-like signals useful in detecting presence of damage and its location. The second is the impedance method sensitive to the damage/failure in low resistance open circuit pattern like solder interconnects. The method measures the impedance as a function of frequency and design to detects the crack and/or void trapped/developed at the solder joints mainly using the skin effect in AC resistance. The technique is with its own limitations but can enable effective characterization of damages in package interconnects.
{"title":"Advanced Methods of Detecting Physical Damages in Packaging and BEOL Interconnects","authors":"J. Mendoza, Jimmy-Bao Le, C. Kim, H. Lin","doi":"10.1109/IRPS48203.2023.10117720","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117720","url":null,"abstract":"This paper reports new methods of detecting damages and failures in packaging interconnects in fully packaged devices with sufficient sensitivity and selectivity for damages in interconnects. Exploration on various electrical methods leads to the conclusion that a few electrical measurement techniques, especially one using a low frequency AC signal, may provide effective mechanism of detecting the damages under interest. Impedance and derived parameters such as capacitance and inductance show sensitivity to silicon-package-interaction damages, with satisfactory immunity to parasitic signals present in fully assembled/packaged test chips such as the probe/pad contact resistance and stray capacitance from various sources. Two highlighting examples based on the “open circuit test pattern” are introduced in this paper to demonstrate the effectiveness of developed methods. The first is the damage detection in the high resistance open circuit pattern, which consists of small metal serpentines strategically placed on the failure prone places in BEOL of Si chip. Small damage develop in the metal serpentine makes the circuits to produce LC resonance-like signals useful in detecting presence of damage and its location. The second is the impedance method sensitive to the damage/failure in low resistance open circuit pattern like solder interconnects. The method measures the impedance as a function of frequency and design to detects the crack and/or void trapped/developed at the solder joints mainly using the skin effect in AC resistance. The technique is with its own limitations but can enable effective characterization of damages in package interconnects.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124497218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117667
D. Favero, A. Cavaliere, C. D. Santi, M. Borga, W. G. Filho, K. Geens, B. Bakeroot, S. Decoutere, G. Meneghesso, E. Zanoni, M. Meneghini
For the first time we investigate the positive threshold voltage instability in GaN-based trench gate MOSFETs in the high-temperature regime (150–240 °C). First, by inverse Laplace transform we determine the equivalent distribution of activation energies of the traps responsible for PBTI, with a peak at 0.75 eV from the conduction band of GaN. Second, we demonstrate that the recovery transients have a non-monotonic trend. This result, never described before, is attributed to the interplay between electron de-trapping from border traps, and hole de-trapping from defects in the p-type body layer, located 0.65 eV above the valence band energy of GaN, and preliminary ascribed to gallium vacancies in the semiconductor. Results provide relevant insight for optimizing the high-temperature stability of GaN vertical FETs.
{"title":"High- Temperature PBTI in Trench-Gate Vertical GaN Power MOSFETs: Role of Border and Semiconductor Traps","authors":"D. Favero, A. Cavaliere, C. D. Santi, M. Borga, W. G. Filho, K. Geens, B. Bakeroot, S. Decoutere, G. Meneghesso, E. Zanoni, M. Meneghini","doi":"10.1109/IRPS48203.2023.10117667","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117667","url":null,"abstract":"For the first time we investigate the positive threshold voltage instability in GaN-based trench gate MOSFETs in the high-temperature regime (150–240 °C). First, by inverse Laplace transform we determine the equivalent distribution of activation energies of the traps responsible for PBTI, with a peak at 0.75 eV from the conduction band of GaN. Second, we demonstrate that the recovery transients have a non-monotonic trend. This result, never described before, is attributed to the interplay between electron de-trapping from border traps, and hole de-trapping from defects in the p-type body layer, located 0.65 eV above the valence band energy of GaN, and preliminary ascribed to gallium vacancies in the semiconductor. Results provide relevant insight for optimizing the high-temperature stability of GaN vertical FETs.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122477690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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