Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117677
Longda Zhou, Jie Li, Zheng Qiao, P. Ren, Zixuan Sun, Jianping Wang, Blacksmith Wu, Zhigang Ji, Runsheng Wang, Kanyu Cao, Ru Huang
The double-sided row hammer (rh) effect at the silicon level for sub-20 nm dynamic random access memory (DRAM) is systematically investigated for the first time. Based on 3D TCAD simulation, the impacts of capacitive crosstalk and electron migration are investigated. The latter with trap assistance is found the dominant mechanism behind the enhancement of 1 failure and the alleviation of 0 failure for double-sided rh. Moreover, rh dependences on data pattern, timing parameters and technology nodes are compared under different rh conditions. A trade-off of retention time (tret) between 1 failure and 0 failure should be considered when suppressing the double-sided rh effect. With the co-optimization of key process parameters, tret for double-sided rh-induced 1 failure can be improved by 220 times.
{"title":"Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation","authors":"Longda Zhou, Jie Li, Zheng Qiao, P. Ren, Zixuan Sun, Jianping Wang, Blacksmith Wu, Zhigang Ji, Runsheng Wang, Kanyu Cao, Ru Huang","doi":"10.1109/IRPS48203.2023.10117677","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117677","url":null,"abstract":"The double-sided row hammer (rh) effect at the silicon level for sub-20 nm dynamic random access memory (DRAM) is systematically investigated for the first time. Based on 3D TCAD simulation, the impacts of capacitive crosstalk and electron migration are investigated. The latter with trap assistance is found the dominant mechanism behind the enhancement of 1 failure and the alleviation of 0 failure for double-sided rh. Moreover, rh dependences on data pattern, timing parameters and technology nodes are compared under different rh conditions. A trade-off of retention time (tret) between 1 failure and 0 failure should be considered when suppressing the double-sided rh effect. With the co-optimization of key process parameters, tret for double-sided rh-induced 1 failure can be improved by 220 times.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A physical model is derived to characterize the thermal safe-operating area (T-SOA) of power transistor. This model provides a concise methodology to get the precise and instant solutions of the temperature, and time to failure corresponding to IV for power transistor during the T-SOA measurement.
{"title":"A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor","authors":"Jian-Hsing Lee, Gong-Kai Lin, Chun-Chih Chen, Li-Fan Chen, Chien-Wei Wang, Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Ke-Horng Chen","doi":"10.1109/IRPS48203.2023.10117633","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117633","url":null,"abstract":"A physical model is derived to characterize the thermal safe-operating area (T-SOA) of power transistor. This model provides a concise methodology to get the precise and instant solutions of the temperature, and time to failure corresponding to IV for power transistor during the T-SOA measurement.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127573385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117795
Y. H. Lin, C. C. Lee, C. Liao, M. H. Lin, W. Tu, R. Chen, H. P. Chen, W. Shue, M. Cao
Process-induced warpage caused by high-density interconnects in the back-end of line (BEOL) structure, may affect the performance and the reliability of the product during the packaging process. In this paper, a BEOL structure is used to develop a process-oriented simulation methodology to optimize the design and predict warpage. To reduce simulation time and obtain accurate predictions, the equivalent material method and equivalent residual stress are used in our proposed method. The layer-by-layer warpage predictions matched the measurement data.
{"title":"A Novel Methodology to Predict Process-Induced Warpage in Advanced BEOL Interconnects","authors":"Y. H. Lin, C. C. Lee, C. Liao, M. H. Lin, W. Tu, R. Chen, H. P. Chen, W. Shue, M. Cao","doi":"10.1109/IRPS48203.2023.10117795","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117795","url":null,"abstract":"Process-induced warpage caused by high-density interconnects in the back-end of line (BEOL) structure, may affect the performance and the reliability of the product during the packaging process. In this paper, a BEOL structure is used to develop a process-oriented simulation methodology to optimize the design and predict warpage. To reduce simulation time and obtain accurate predictions, the equivalent material method and equivalent residual stress are used in our proposed method. The layer-by-layer warpage predictions matched the measurement data.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127685510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117586
L. Cattaneo, M. Baldo, N. Lepri, Flavio Sancandi, M. Borghi, E. Petroni, A. Serafini, R. Annunziata, A. Redaelli, D. Ielmini
In the era of the internet of things (IoT), hardware physical unclonable functions (PUFs) have become an essential feature for authentication of any system on chip (SoC). Identifying physical entropy sources is essential for developing low-cost, low-power, highly reliable PUFs. This work presents a new PUF circuit based on embedded PCM, called MVPUF. The new PUF relies on the random virgin state of the PCM combined with a new selection technique of challenge-response pairs (CRPs), thus showing better reliability compared to PUFs based on resistive switching memory (RRAM).
{"title":"Enhancing reliability of a strong physical unclonable function (PUF) solution based on virgin-state phase change memory (PCM)","authors":"L. Cattaneo, M. Baldo, N. Lepri, Flavio Sancandi, M. Borghi, E. Petroni, A. Serafini, R. Annunziata, A. Redaelli, D. Ielmini","doi":"10.1109/IRPS48203.2023.10117586","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117586","url":null,"abstract":"In the era of the internet of things (IoT), hardware physical unclonable functions (PUFs) have become an essential feature for authentication of any system on chip (SoC). Identifying physical entropy sources is essential for developing low-cost, low-power, highly reliable PUFs. This work presents a new PUF circuit based on embedded PCM, called MVPUF. The new PUF relies on the random virgin state of the PCM combined with a new selection technique of challenge-response pairs (CRPs), thus showing better reliability compared to PUFs based on resistive switching memory (RRAM).","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"726 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127013886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118073
Hui Wang, Pengyu Lai, Zhongren Chen
The utilization of parasitic bipolar structures inside a typical P+/N-well as an additional electrostatic discharge (ESD) path is explored. The optimization on the lateral PNP (LPNP) is discussed. Device transmission line pulse (TLP) characterizations and technology computer aided design (TCAD) simulations by Silvaco have been performed to investigate the stand-alone LPNP ESD performance and effects of the base current injection on ESD behaviors of parasitic bipolar transistors.
{"title":"Current Injection Effect on ESD Behaviors of the Parasitic Bipolar Transistors inside P+/N-well diode","authors":"Hui Wang, Pengyu Lai, Zhongren Chen","doi":"10.1109/IRPS48203.2023.10118073","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118073","url":null,"abstract":"The utilization of parasitic bipolar structures inside a typical P+/N-well as an additional electrostatic discharge (ESD) path is explored. The optimization on the lateral PNP (LPNP) is discussed. Device transmission line pulse (TLP) characterizations and technology computer aided design (TCAD) simulations by Silvaco have been performed to investigate the stand-alone LPNP ESD performance and effects of the base current injection on ESD behaviors of parasitic bipolar transistors.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114243488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117817
Kang Yang, Suhui Yang, Yan Ouyang, Sheng-Chieh Yang, Kun Han, Yi He
Backside (BS) interconnects has shown significant advantages in 3D integral circuits for tackling the technology scaling induced frontside (FS) back-end-of-line (BEOL) routing congestion and RC delay challenge. As a representative BS interconnects architecture, Xtacking ® 1.0 & 2.0 innovated by YMTC employs one Al metal layer at backside of memory cell wafer as BS interconnect routing for signal transfer. In this paper, we exploit the effect of silicon substrate to stress migration (SM) reliability of such Al BS interconnects, and offer several process approaches by film stack or film behavior optimization to improve SM performance of Al interconnects with the assistance of numerical simulation. An index of RSM is proposed to reveal the statistic SM performance. Combining experiments and simulation result, a positive relationship is found between hydrostatic stress in numerical simulation and RSM, and it brings a quantitative solution for SM in numerical simulation.
{"title":"Stress Migration of Aluminum Backside Interconnect in Xtacking®","authors":"Kang Yang, Suhui Yang, Yan Ouyang, Sheng-Chieh Yang, Kun Han, Yi He","doi":"10.1109/IRPS48203.2023.10117817","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117817","url":null,"abstract":"Backside (BS) interconnects has shown significant advantages in 3D integral circuits for tackling the technology scaling induced frontside (FS) back-end-of-line (BEOL) routing congestion and RC delay challenge. As a representative BS interconnects architecture, Xtacking ® 1.0 & 2.0 innovated by YMTC employs one Al metal layer at backside of memory cell wafer as BS interconnect routing for signal transfer. In this paper, we exploit the effect of silicon substrate to stress migration (SM) reliability of such Al BS interconnects, and offer several process approaches by film stack or film behavior optimization to improve SM performance of Al interconnects with the assistance of numerical simulation. An index of RSM is proposed to reveal the statistic SM performance. Combining experiments and simulation result, a positive relationship is found between hydrostatic stress in numerical simulation and RSM, and it brings a quantitative solution for SM in numerical simulation.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123606661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117810
Simon Thomann, Albi Mema, Kai Ni, H. Amrouch
Inherent domain stochasticity induced by the random spatial distribution of domains inside the ferroelectric (FE) layer along with Cycle-to-Cycle (CTC) and Device-to-Device (DTD) variability seriously hamper our ability to tune the FeFET threshold voltage ($V_{TH}$) towards the desired analog states required to realize neuromorphic computing. In this work, we present an framework that enables the joint modeling of Domain Stochasticity (DS), CTC, and DTD variability, through coupling TCAD models (accurately capturing the distributed channel of the underlying FET) with a multi-domain model that accurately captures the switching dynamics of the individual domains in the above FE layer. Hence, the hidden interaction between the spatial polarization fluctuation in FE and the distributed channel is unveiled. As a result, accurate modeling of $V_{TH}$ distribution under various write scenarios is obtained. This, in turn, provides designers with guidelines on how analog states can be reliably programmed towards engineering reliable neuromorphic on unreliable FeFET.
{"title":"Reliable FeFET-based Neuromorphic Computing through Joint Modeling of Cycle-to-Cycle Variability, Device-to-Device Variability, and Domain Stochasticity","authors":"Simon Thomann, Albi Mema, Kai Ni, H. Amrouch","doi":"10.1109/IRPS48203.2023.10117810","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117810","url":null,"abstract":"Inherent domain stochasticity induced by the random spatial distribution of domains inside the ferroelectric (FE) layer along with Cycle-to-Cycle (CTC) and Device-to-Device (DTD) variability seriously hamper our ability to tune the FeFET threshold voltage ($V_{TH}$) towards the desired analog states required to realize neuromorphic computing. In this work, we present an framework that enables the joint modeling of Domain Stochasticity (DS), CTC, and DTD variability, through coupling TCAD models (accurately capturing the distributed channel of the underlying FET) with a multi-domain model that accurately captures the switching dynamics of the individual domains in the above FE layer. Hence, the hidden interaction between the spatial polarization fluctuation in FE and the distributed channel is unveiled. As a result, accurate modeling of $V_{TH}$ distribution under various write scenarios is obtained. This, in turn, provides designers with guidelines on how analog states can be reliably programmed towards engineering reliable neuromorphic on unreliable FeFET.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127368786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118043
P. Srinivasan, J. Lestage, S. Syed, X. Hui, S. Moss, O. D. Restrepo, Oscar H. Gonzalez, Y. Chen, T. Mckay, A. Bandyopadhyay, N. Cahoon, F. Guarín, B. Min, M. Gall, S. Ludvik
RF long term aging and large signal reliability in 22FDX Wi-Fi Power Amplifier (P A) designs is investigated. Packaged PA operating at 5.4GHz., 3.3V VDD with LDMOS as Common Gate and SLVT as Common Source is stressed under accelerated DC and RF power conditions for +1.5kPOH at TA=25 C. A custom built Power Amplifier Test System (PATS) tool capable of large signal on packaged samples is used for long term stress. Initial RF performance of ~26 dBm., with gain 14~15 is seen before stress. Power sweeps at regular stress intervals were performed to validate PA degradation. Self-heating effect is studied by correlating TA to junction temp TJ using thermal models. Thermal images confirm that higher Pdiss leads to higher TJ. Output power degradation of < 0.5dB is seen at accelerated voltage of 4.2V after + 1.5kPOH which is correlated to voltage swings. Key limiting mechanism for common gate and source devices are identified, demonstrating the viability of CMOS FDSOI technology for 5G applications.
{"title":"RF long term aging behavior and reliability in 22FDX WiFi Power Amplifier designs for 5G applications","authors":"P. Srinivasan, J. Lestage, S. Syed, X. Hui, S. Moss, O. D. Restrepo, Oscar H. Gonzalez, Y. Chen, T. Mckay, A. Bandyopadhyay, N. Cahoon, F. Guarín, B. Min, M. Gall, S. Ludvik","doi":"10.1109/IRPS48203.2023.10118043","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118043","url":null,"abstract":"RF long term aging and large signal reliability in 22FDX Wi-Fi Power Amplifier (P A) designs is investigated. Packaged PA operating at 5.4GHz., 3.3V VDD with LDMOS as Common Gate and SLVT as Common Source is stressed under accelerated DC and RF power conditions for +1.5kPOH at TA=25 C. A custom built Power Amplifier Test System (PATS) tool capable of large signal on packaged samples is used for long term stress. Initial RF performance of ~26 dBm., with gain 14~15 is seen before stress. Power sweeps at regular stress intervals were performed to validate PA degradation. Self-heating effect is studied by correlating TA to junction temp TJ using thermal models. Thermal images confirm that higher Pdiss leads to higher TJ. Output power degradation of < 0.5dB is seen at accelerated voltage of 4.2V after + 1.5kPOH which is correlated to voltage swings. Key limiting mechanism for common gate and source devices are identified, demonstrating the viability of CMOS FDSOI technology for 5G applications.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118168
J. H. Lee, B. Woo, Y. M. Lee, N. Lee, S. Lee, Y. S. Lee, H. S. Kim, S. Pae
Advanced DRAM with the reduced dangling bonds defects for the transistors could be manufactured by temperature control of passivation and optimizing BEOL process application. The decrease in passivation temperature increased hydrogen ion diffusion from the passivation layer. Passivation of the dangling bonds resulted in the increase of the retention time. Negative bias temperature instability (NBTI) of periphery device was relatively constant due to the pre-existing Si-H bonds. However, back end of line (BEOL) reliability showed drastic deterioration in time dependent dielectric breakdown (TDDB) and electro-migration (EM). Deterioration of Cu adhesion by water molecules and void formation was the main factor of drastic exacerbation of TDDB and EM lifetime. In order to strengthen the Cu adhesion, the optimized BEOL process was applied and the BEOL reliability was improved. As a result, the DRAM cell characteristic has been improved.
{"title":"Reliability Improvement with Optimized BEOL Process in Advanced DRAM","authors":"J. H. Lee, B. Woo, Y. M. Lee, N. Lee, S. Lee, Y. S. Lee, H. S. Kim, S. Pae","doi":"10.1109/IRPS48203.2023.10118168","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118168","url":null,"abstract":"Advanced DRAM with the reduced dangling bonds defects for the transistors could be manufactured by temperature control of passivation and optimizing BEOL process application. The decrease in passivation temperature increased hydrogen ion diffusion from the passivation layer. Passivation of the dangling bonds resulted in the increase of the retention time. Negative bias temperature instability (NBTI) of periphery device was relatively constant due to the pre-existing Si-H bonds. However, back end of line (BEOL) reliability showed drastic deterioration in time dependent dielectric breakdown (TDDB) and electro-migration (EM). Deterioration of Cu adhesion by water molecules and void formation was the main factor of drastic exacerbation of TDDB and EM lifetime. In order to strengthen the Cu adhesion, the optimized BEOL process was applied and the BEOL reliability was improved. As a result, the DRAM cell characteristic has been improved.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133028252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117650
Ivana Kovacevic-Badstuebner, S. Race, U. Grossner, E. Mengotti, C. Kenel, E. Bianda, J. Jormanainen
This paper presents an extended analysis of TO-packaged SiC power MOSFETs after power cycling (PC) tests. Namely, it is shown that initially present voids in soft lead-based solder die attach disappear not only after certain number of active PC tests, but also after thermal shock tests. Hereby, the conclusion that solder die attach is not the weak spot of SiC power MOSFET packages with an epoxy mold compound (EMC) encapsulation is further supported. Furthermore, an electro-thermo-mechanical (ETM) model developed in-house is used to correlate the dominant wear-out failure of bond wires to the PC test parameters such as heating current, temperature amplitude, and heating on-time, as well as to the thickness of top source die metallization.
{"title":"Extended Analysis of Power Cycling Behavior of TO-Packaged SiC Power MOSFETs","authors":"Ivana Kovacevic-Badstuebner, S. Race, U. Grossner, E. Mengotti, C. Kenel, E. Bianda, J. Jormanainen","doi":"10.1109/IRPS48203.2023.10117650","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117650","url":null,"abstract":"This paper presents an extended analysis of TO-packaged SiC power MOSFETs after power cycling (PC) tests. Namely, it is shown that initially present voids in soft lead-based solder die attach disappear not only after certain number of active PC tests, but also after thermal shock tests. Hereby, the conclusion that solder die attach is not the weak spot of SiC power MOSFET packages with an epoxy mold compound (EMC) encapsulation is further supported. Furthermore, an electro-thermo-mechanical (ETM) model developed in-house is used to correlate the dominant wear-out failure of bond wires to the PC test parameters such as heating current, temperature amplitude, and heating on-time, as well as to the thickness of top source die metallization.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133466297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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