Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117992
M. Jamil, S. Mukhopadhay, M. Ghoneim, A. Shailos, C. Prasad, I. Meric, S. Ramey
The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or better reliability while extending Moore's law in the areas of power, performance, and scaling over its predecessor. Industry-leading technology scaling comes with numerous challenges, including co-optimization of yield, performance, and reliability. This paper reports the development of Intel 4 technology with industry-standard reliability while delivering significant advancement in generational performance and density.
{"title":"Reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS Technology","authors":"M. Jamil, S. Mukhopadhay, M. Ghoneim, A. Shailos, C. Prasad, I. Meric, S. Ramey","doi":"10.1109/IRPS48203.2023.10117992","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117992","url":null,"abstract":"The Intel 4 CMOS FinFET technology delivers over 20% performance gains at iso-power over the prior generation (Intel 7). This paper reports reliability studies on the Intel 4 technology that demonstrate matched or better reliability while extending Moore's law in the areas of power, performance, and scaling over its predecessor. Industry-leading technology scaling comes with numerous challenges, including co-optimization of yield, performance, and reliability. This paper reports the development of Intel 4 technology with industry-standard reliability while delivering significant advancement in generational performance and density.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123299108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118220
H. B. Variar, S. K. Gautam, Ashita Kumar, K. M. Amogh, Juan Luo, Ning Shi, D. Marreiro, S. Mallikarjunaswamy, M. Shrivastava
This work demonstrates an SCR-Diode series ESD Protection concept, which can be engineered to provide a custom TLP I-V characteristic. SCRs and diodes with dimensional variations have been used in different combinations and width ratios, which results in a range of TLP I-V characteristics. This protection circuit comes with several advantages as adaptability for various ESD protection windows, the benefits of using SCR as a protection device and the ease of designing the circuit. Along with TCAD studies, experimental data demonstrates that N-well and P-well doping of SCR can be used to further tune the Vhold and Ron of the protection circuit.
{"title":"Engineering Custom TLP I-V Characteristic Using a SCR-Diode Series ESD Protection Concept","authors":"H. B. Variar, S. K. Gautam, Ashita Kumar, K. M. Amogh, Juan Luo, Ning Shi, D. Marreiro, S. Mallikarjunaswamy, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10118220","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118220","url":null,"abstract":"This work demonstrates an SCR-Diode series ESD Protection concept, which can be engineered to provide a custom TLP I-V characteristic. SCRs and diodes with dimensional variations have been used in different combinations and width ratios, which results in a range of TLP I-V characteristics. This protection circuit comes with several advantages as adaptability for various ESD protection windows, the benefits of using SCR as a protection device and the ease of designing the circuit. Along with TCAD studies, experimental data demonstrates that N-well and P-well doping of SCR can be used to further tune the Vhold and Ron of the protection circuit.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131497862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117774
Manisha Sharma, Hokyung Park, Yinghong Zhao, Ki-Don Lee, Liangshan Chen, J. Yoon, R. Ranjan, Caleb Dongkyan Kwon, H. Shim, M. Yeo, Shin-Young Chung, J. Haefner
Stress polarity dependency of MOL-TDDB (Middle of Line-Time Dependent Dielectric Breakdown) is investigated on FinFET devices. Due to asymmetry in spacer dielectrics between Gate (PC) and Contact (CA), MOL-TDDB reliability can be different by bias polarity. From Vramp and TDDB evaluations, we observed MOL-TDDB reliability becomes worse when positive bias is applied to the CA side. Leakage current analysis and energy band diagram study suggested this reliability degradation can be explained by either more trap generation or more electron trapping in high-k layer (on PC side). This behavior can be suppressed by Vt-tuning capping layer.
{"title":"Polarity Dependency of MOL-TDDB in FinFET","authors":"Manisha Sharma, Hokyung Park, Yinghong Zhao, Ki-Don Lee, Liangshan Chen, J. Yoon, R. Ranjan, Caleb Dongkyan Kwon, H. Shim, M. Yeo, Shin-Young Chung, J. Haefner","doi":"10.1109/IRPS48203.2023.10117774","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117774","url":null,"abstract":"Stress polarity dependency of MOL-TDDB (Middle of Line-Time Dependent Dielectric Breakdown) is investigated on FinFET devices. Due to asymmetry in spacer dielectrics between Gate (PC) and Contact (CA), MOL-TDDB reliability can be different by bias polarity. From Vramp and TDDB evaluations, we observed MOL-TDDB reliability becomes worse when positive bias is applied to the CA side. Leakage current analysis and energy band diagram study suggested this reliability degradation can be explained by either more trap generation or more electron trapping in high-k layer (on PC side). This behavior can be suppressed by Vt-tuning capping layer.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131748237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117954
K. Joshi, D. Nminibapiel, M. Ghoneim, D. Ali, R. Ramamurthy, L. Pantisano, I. Meric, S. Ramey
The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.
{"title":"A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies","authors":"K. Joshi, D. Nminibapiel, M. Ghoneim, D. Ali, R. Ramamurthy, L. Pantisano, I. Meric, S. Ramey","doi":"10.1109/IRPS48203.2023.10117954","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117954","url":null,"abstract":"The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper compares various OSS methodologies available in the literature and discusses how source-to-drain punch-through affects off-state breakdown and reliability. The proposed Drain-stress with Offset (DSO) OSS methodology limits punch-through to better reflect the actual field dependence of OSS breakdown for scaled tri-gate MOSFET technologies.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"44 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120874149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118280
A. Goda, K. K. Muchherla, Peter Feeley
The 3D NAND Flash technologies have been successful, having realized the high density, high performance and highly reliable storage systems. With the continuous technology scaling, significant challenges and opportunities are expected in the future. SLC NAND technology plays a critical role for the high performance systems. The increased block size with further layer stacking requires innovative solutions to realize enhanced system performance and cost scaling. For the bits per cell (BPC) scaling beyond QLC, the reduction of the total cost of ownership (TCO) at the system level is the key. In this paper, we review and discuss the challenges and opportunities of 3D NAND reliability from the storage system perspectives.
3D NAND闪存技术已经取得了成功，实现了高密度、高性能和高可靠性的存储系统。随着技术的不断扩展，未来将面临巨大的挑战和机遇。SLC NAND技术在高性能系统中起着至关重要的作用。随着层的进一步堆叠而增加的块大小需要创新的解决方案来实现增强的系统性能和成本扩展。对于超越QLC的每单元位(BPC)扩展，降低系统级的总拥有成本(TCO)是关键。在本文中，我们从存储系统的角度回顾和讨论了3D NAND可靠性的挑战和机遇。
{"title":"Reliability of 3D NAND Flash for Future Storage Systems (Invited)","authors":"A. Goda, K. K. Muchherla, Peter Feeley","doi":"10.1109/IRPS48203.2023.10118280","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118280","url":null,"abstract":"The 3D NAND Flash technologies have been successful, having realized the high density, high performance and highly reliable storage systems. With the continuous technology scaling, significant challenges and opportunities are expected in the future. SLC NAND technology plays a critical role for the high performance systems. The increased block size with further layer stacking requires innovative solutions to realize enhanced system performance and cost scaling. For the bits per cell (BPC) scaling beyond QLC, the reduction of the total cost of ownership (TCO) at the system level is the key. In this paper, we review and discuss the challenges and opportunities of 3D NAND reliability from the storage system perspectives.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131112800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117790
X. Federspiel, A. Griffon, Marios Barlas, P. Lamontagne
Dielectric relaxation phenomena in High-K capacitors have been reported to induce transitory effects. We present here a TDDB analysis including DC and pulsed DC stress applied on HK capacitors. We evidence a significant effect of frequency on TDDB. Using a model based on dielectric polarization dynamics, we found a good agreement with TDDB evolution with frequency but also a consistent behavior in terms of voltage acceleration factor as well as activation energy.
{"title":"Effect of Frequency on Reliability Of High-K MIM Capacitors","authors":"X. Federspiel, A. Griffon, Marios Barlas, P. Lamontagne","doi":"10.1109/IRPS48203.2023.10117790","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117790","url":null,"abstract":"Dielectric relaxation phenomena in High-K capacitors have been reported to induce transitory effects. We present here a TDDB analysis including DC and pulsed DC stress applied on HK capacitors. We evidence a significant effect of frequency on TDDB. Using a model based on dielectric polarization dynamics, we found a good agreement with TDDB evolution with frequency but also a consistent behavior in terms of voltage acceleration factor as well as activation energy.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128086690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117643
Xinyi Xu, Hongchao Zhang, Chuanpeng Jiang, Jinhao Li, Shi-Ji Lu, Yunpeng Li, H. Du, Xueying Zhang, Zhaohao Wang, K. Cao, Weisheng Zhao, Shuqin Lyu, Hao Xu, Bonian Jiang, Le Wang, Bowen Man, Cong Zhang, Dandan Li, Shuhui Li, Xiaofei Fan, Gefei Wang, Hong-xi Liu
We have systematically investigated the reliability performance of spin-orbit torque (SOT) magnetic random access memory (MRAM) devices, including electromigration (EM), stress migration (SM), endurance and data retention. The results show that the SOT-MRAM devices pass the EM requirement over 10 years lifetime under the operation condition, and pass the SM requirement over 1000 hours baking at 175°C. Moreover, high endurance close to 1014 cycles and robust data retention over 10 years storage time were demonstrated for the same SOT-MRAM devices. This full characterization fills the blank of SOT-MRAM reliability research and would contribute to the commercialization of the SOT-MRAM.
{"title":"Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays","authors":"Xinyi Xu, Hongchao Zhang, Chuanpeng Jiang, Jinhao Li, Shi-Ji Lu, Yunpeng Li, H. Du, Xueying Zhang, Zhaohao Wang, K. Cao, Weisheng Zhao, Shuqin Lyu, Hao Xu, Bonian Jiang, Le Wang, Bowen Man, Cong Zhang, Dandan Li, Shuhui Li, Xiaofei Fan, Gefei Wang, Hong-xi Liu","doi":"10.1109/IRPS48203.2023.10117643","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117643","url":null,"abstract":"We have systematically investigated the reliability performance of spin-orbit torque (SOT) magnetic random access memory (MRAM) devices, including electromigration (EM), stress migration (SM), endurance and data retention. The results show that the SOT-MRAM devices pass the EM requirement over 10 years lifetime under the operation condition, and pass the SM requirement over 1000 hours baking at 175°C. Moreover, high endurance close to 1014 cycles and robust data retention over 10 years storage time were demonstrated for the same SOT-MRAM devices. This full characterization fills the blank of SOT-MRAM reliability research and would contribute to the commercialization of the SOT-MRAM.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117962
Sungman Rhee, Hyunjin Kim, Sangku Park, T. Uemura, Yuchul Hwang, S. Choo, Jinju Kim, H. Rhee, Shin-Young Chung
In this paper, we propose for the first time a breakdown voltage $(mathrm{V}_{text{BD}})$ prediction method using structural parameters measured in-process for early detection of reliability risks in Middle-Of-Line (MOL). $boldsymbol{mathrm{V}_{text{BD}}}$ of the MOL is proportional to the distance of the Gate (PC) to Source/Drain-Contact (CA). Since PC to CA space can be calculated using MOL-related structural parameters at the early stage of the process, we created and validated models predicting V-ramp $boldsymbol{mathrm{V}_{text{BD}}}$ using five fab parameters measured in-process by optical critical dimension scatterometry (OCD). And we compared three modeling methods. The first is the geometrical calculation model (GCM), the second is multiple-linear-regression (MLR) method, and the last is the Multi-Layer Perceptions (MLP) model based on the machine learning (ML). We found the highest predictive consistency $boldsymbol{mathrm{R}^{2}0.6}$ in ML method, and it is expected to contribute to the early prediction of MOL V-ramp $mathrm{V}_{text{BD}}$ through additional consistency improvements.
{"title":"Machine Learning Based V-ramp VBD Predictive Model Using OCD-measured Fab Parameters for Early Detection of MOL Reliability Risk","authors":"Sungman Rhee, Hyunjin Kim, Sangku Park, T. Uemura, Yuchul Hwang, S. Choo, Jinju Kim, H. Rhee, Shin-Young Chung","doi":"10.1109/IRPS48203.2023.10117962","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117962","url":null,"abstract":"In this paper, we propose for the first time a breakdown voltage $(mathrm{V}_{text{BD}})$ prediction method using structural parameters measured in-process for early detection of reliability risks in Middle-Of-Line (MOL). $boldsymbol{mathrm{V}_{text{BD}}}$ of the MOL is proportional to the distance of the Gate (PC) to Source/Drain-Contact (CA). Since PC to CA space can be calculated using MOL-related structural parameters at the early stage of the process, we created and validated models predicting V-ramp $boldsymbol{mathrm{V}_{text{BD}}}$ using five fab parameters measured in-process by optical critical dimension scatterometry (OCD). And we compared three modeling methods. The first is the geometrical calculation model (GCM), the second is multiple-linear-regression (MLR) method, and the last is the Multi-Layer Perceptions (MLP) model based on the machine learning (ML). We found the highest predictive consistency $boldsymbol{mathrm{R}^{2}0.6}$ in ML method, and it is expected to contribute to the early prediction of MOL V-ramp $mathrm{V}_{text{BD}}$ through additional consistency improvements.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116142274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117870
Y. Ding, O. Pedreira, M. Lofrano, H. Zahedmanesh, T. Chavez, Hosain Farr, I. Wolf, K. Croes
Using a dedicated test structure, the main physical parameters of void formation due to thermomigration (TM) were assessed. Based on physical and electrical void-analyses, we experimentally determined the time to void nucleation and estimated the heat of transport parameter $Q^{ast}= 0.21$ eV for Cu interconnects with CD~1µm, Our studies show that TM has a 6x higher contribution to metal flux compared to the initial stress migration (SM) induced by the coefficient of thermal expansion (CTE) mismatch.
{"title":"Thermomigration-induced void formation in Cu-interconnects - Assessment of main physical parameters","authors":"Y. Ding, O. Pedreira, M. Lofrano, H. Zahedmanesh, T. Chavez, Hosain Farr, I. Wolf, K. Croes","doi":"10.1109/IRPS48203.2023.10117870","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117870","url":null,"abstract":"Using a dedicated test structure, the main physical parameters of void formation due to thermomigration (TM) were assessed. Based on physical and electrical void-analyses, we experimentally determined the time to void nucleation and estimated the heat of transport parameter $Q^{ast}= 0.21$ eV for Cu interconnects with CD~1µm, Our studies show that TM has a 6x higher contribution to metal flux compared to the initial stress migration (SM) induced by the coefficient of thermal expansion (CTE) mismatch.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125827797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117978
Rupali Verma, Utpreksh Patbhaje, J. Kumar, A. Rai, M. Shrivastava
This work reports the hot-hole injection-originated instability in the electrical characteristics (or the photodetection performance) of a monolayer WS2 Field Effect Transistor (FET) photodetector. When a reverse bias (i.e., OFF-state bias or negative gate voltage) temporal stress with a lateral electric field is applied under visible light illumination, the photocurrent is found to vary with time by up to 1 to 2 orders of magnitude. Instability in the dark current is also observed post the stress under illumination, which is reflected in the variation in the transfer and the output characteristics of the FET. The observations impose severe limitations on the reverse-biased back-gated FET for sensitive photodetection applications using transparent single-layer WS2 as the photoactive material.
{"title":"OFF State Reliability Challenges of Monolayer WS2 FET Photodetector: Impact on the Dark and Photo-Illuminated State","authors":"Rupali Verma, Utpreksh Patbhaje, J. Kumar, A. Rai, M. Shrivastava","doi":"10.1109/IRPS48203.2023.10117978","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117978","url":null,"abstract":"This work reports the hot-hole injection-originated instability in the electrical characteristics (or the photodetection performance) of a monolayer WS2 Field Effect Transistor (FET) photodetector. When a reverse bias (i.e., OFF-state bias or negative gate voltage) temporal stress with a lateral electric field is applied under visible light illumination, the photocurrent is found to vary with time by up to 1 to 2 orders of magnitude. Instability in the dark current is also observed post the stress under illumination, which is reflected in the variation in the transfer and the output characteristics of the FET. The observations impose severe limitations on the reverse-biased back-gated FET for sensitive photodetection applications using transparent single-layer WS2 as the photoactive material.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121867223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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