Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117846
A. Padovani, P. L. Torraca, J. Strand, A. Shluger, Valerio Milo, L. Larcher
We present a microscopic breakdown (BD) model in which chemical bonds are weakened by carrier injection and trapping into pre-existing structural defects (precursors) and by the electric field. The model goes much beyond the existing ones by consistently explaining the role of both current (a weakness of the E model) and temperature (a weakness of the power-law model), along with the role of the electric field. It also explains the non-Arrhenius temperature dependence of BD. It suggests a new comprehensive physics-based framework (with tight connections to material properties) reconciling the many breakdown theories proposed so far (E, power-law, 1/E,…) within a more universal breakdown model.
{"title":"Towards a Universal Model of Dielectric Breakdown","authors":"A. Padovani, P. L. Torraca, J. Strand, A. Shluger, Valerio Milo, L. Larcher","doi":"10.1109/IRPS48203.2023.10117846","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117846","url":null,"abstract":"We present a microscopic breakdown (BD) model in which chemical bonds are weakened by carrier injection and trapping into pre-existing structural defects (precursors) and by the electric field. The model goes much beyond the existing ones by consistently explaining the role of both current (a weakness of the E model) and temperature (a weakness of the power-law model), along with the role of the electric field. It also explains the non-Arrhenius temperature dependence of BD. It suggests a new comprehensive physics-based framework (with tight connections to material properties) reconciling the many breakdown theories proposed so far (E, power-law, 1/E,…) within a more universal breakdown model.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122949601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117748
M. Y. Li, J. P. Lee, C. H. Liu, J. C. Guo, S.S. Chung
In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current $(< mu mathrm{A})$, high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.
在本文中，我们成功地展示了一个四电平单元(QLC)的电阻门存储器。在成熟的逻辑平台上，在集成FinFET核心的1k位芯片上实现。已对综合可靠性进行了检验。结果表明，该芯片具有无成形特性，编程电流$(< mu mathrm{A})$小，耐用性好，数据保存性能好。可以达到创纪录的5×108耐力。此外，还成功地演示了每个单元4位(16个级别)。还分析了芯片级性能，显示在SET/RESET, READ期间具有良好的抗干扰性，保持了健康的信噪比，为2-3倍。这种架构是下一代电阻存储器的有力候选。
{"title":"A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 108 Endurance and Excellent Retention","authors":"M. Y. Li, J. P. Lee, C. H. Liu, J. C. Guo, S.S. Chung","doi":"10.1109/IRPS48203.2023.10117748","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117748","url":null,"abstract":"In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current $(< mu mathrm{A})$, high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124898067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117740
M. W. Feil, Katja Waschneck, H. Reisinger, J. Berens, T. Aichinger, P. Salmen, G. Rescher, W. Gustin, T. Grasser
Bias temperature instability (BTI) is a well-investigated degradation mechanism in technologies based on silicon, gallium nitride, or silicon carbide (SiC). Essentially, it leads to a drift in the threshold voltage and to a reduction in mobility after application of a gate bias, and becomes worse at elevated temperatures. However, as discovered recently, the threshold voltage drift of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) has different properties than those known from BTI when the gate terminal of the device is switched in a bipolar mode. This new degradation mechanism has recently been termed gate switching instability (GSI). To further understand this degradation mechanism and the underlying physics, we have used pre- and post-stress impedance characterization and in-situ ultra-fast threshold voltage measurements. Most importantly, we show that the gate switching leads to the creation of fast, acceptor-like interface defects that lead to a shift in threshold voltage, and hence appear to be responsible for GSI.
{"title":"Towards Understanding the Physics of Gate Switching Instability in Silicon Carbide MOSFETs","authors":"M. W. Feil, Katja Waschneck, H. Reisinger, J. Berens, T. Aichinger, P. Salmen, G. Rescher, W. Gustin, T. Grasser","doi":"10.1109/IRPS48203.2023.10117740","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117740","url":null,"abstract":"Bias temperature instability (BTI) is a well-investigated degradation mechanism in technologies based on silicon, gallium nitride, or silicon carbide (SiC). Essentially, it leads to a drift in the threshold voltage and to a reduction in mobility after application of a gate bias, and becomes worse at elevated temperatures. However, as discovered recently, the threshold voltage drift of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) has different properties than those known from BTI when the gate terminal of the device is switched in a bipolar mode. This new degradation mechanism has recently been termed gate switching instability (GSI). To further understand this degradation mechanism and the underlying physics, we have used pre- and post-stress impedance characterization and in-situ ultra-fast threshold voltage measurements. Most importantly, we show that the gate switching leads to the creation of fast, acceptor-like interface defects that lead to a shift in threshold voltage, and hence appear to be responsible for GSI.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128687029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118334
J. Martín-Martínez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodríguez, R. Castro-López, E. Roca, F. Fernández, M. Nafría
Time-Dependent Variability (TDV) phenomena represent a serious concern for device and circuit reliability. To address the TDV impact at circuit level, Reliability-Aware Design (RAD) tools can be used by circuit designers to achieve more reliable circuits. However, this is not a straightforward task, since the development of RAD tools comprises several steps such as the characterization, modeling and simulation of TDV phenomena. Furthermore, in deeply-scaled CMOS technologies, TDV reveals a stochastic nature that can complicate those steps. In this invited paper, we review some of the main challenges that appear in each step of the flow towards the development of RAD tools, providing our solutions to them.
{"title":"Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability","authors":"J. Martín-Martínez, J. Diaz-Fortuny, P. Saraza-Canflanca, R. Rodríguez, R. Castro-López, E. Roca, F. Fernández, M. Nafría","doi":"10.1109/IRPS48203.2023.10118334","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118334","url":null,"abstract":"Time-Dependent Variability (TDV) phenomena represent a serious concern for device and circuit reliability. To address the TDV impact at circuit level, Reliability-Aware Design (RAD) tools can be used by circuit designers to achieve more reliable circuits. However, this is not a straightforward task, since the development of RAD tools comprises several steps such as the characterization, modeling and simulation of TDV phenomena. Furthermore, in deeply-scaled CMOS technologies, TDV reveals a stochastic nature that can complicate those steps. In this invited paper, we review some of the main challenges that appear in each step of the flow towards the development of RAD tools, providing our solutions to them.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129116499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117971
Z.J. Zhang, Q. Li, Z. Dong, W.T. Wang, S. T. Lai, X. Yang, F. Liang, C.L. Wang, Changzhi Luo, L. Lyu, Z. Li, J.M. Xu, X. Wu
The development of integrated circuits greatly enhances brain-computer interface technology. The degradation of the implanted neural electrodes is a key issue. The scanning electron microscope and energy dispersive spectrometer techniques are used to characterize the evolution of the microscopic morphology and element migration of implanted microwire electrodes containing 32 channels together with the recorded neural signals at different implantation times. The spike amplitude decreases over time of implantation, leading to poorer identification of neural signals. The effect of degradation on the local field potential detection is neglectable. This work could guide the reliability improvement of the neural electrodes.
{"title":"Microscopic Characterization of Failure Mechanisms in Long-Term Implanted Microwire Neural Electrodes","authors":"Z.J. Zhang, Q. Li, Z. Dong, W.T. Wang, S. T. Lai, X. Yang, F. Liang, C.L. Wang, Changzhi Luo, L. Lyu, Z. Li, J.M. Xu, X. Wu","doi":"10.1109/IRPS48203.2023.10117971","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117971","url":null,"abstract":"The development of integrated circuits greatly enhances brain-computer interface technology. The degradation of the implanted neural electrodes is a key issue. The scanning electron microscope and energy dispersive spectrometer techniques are used to characterize the evolution of the microscopic morphology and element migration of implanted microwire electrodes containing 32 channels together with the recorded neural signals at different implantation times. The spike amplitude decreases over time of implantation, leading to poorer identification of neural signals. The effect of degradation on the local field potential detection is neglectable. This work could guide the reliability improvement of the neural electrodes.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128749012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118144
T. Brożek, Alberto A. P. Cattaneo, L. Weiland, M. Quarantelli, Alberto Coccoli, S. Saxena, C. Hess, A. Strojwas
We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV® Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging at final test or during burn-in. During EWS, the wafer-level stress test can be used to identify a marginal chip, help material dispositioning for burn-in, or support additional grading for chiplet matching for multi-chip modules. The aging sensors can also be used during the chip lifetime to monitor the device wear-out and alarm users about abnormal silicon aging rates against target mission profile. In this work, we show the wafer level test results for PMOS transistor degradation rates under NBTI stress, within wafer variability, and correlation of degradation rates between sensors stressed under different conditions.
{"title":"In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk","authors":"T. Brożek, Alberto A. P. Cattaneo, L. Weiland, M. Quarantelli, Alberto Coccoli, S. Saxena, C. Hess, A. Strojwas","doi":"10.1109/IRPS48203.2023.10118144","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118144","url":null,"abstract":"We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV® Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging at final test or during burn-in. During EWS, the wafer-level stress test can be used to identify a marginal chip, help material dispositioning for burn-in, or support additional grading for chiplet matching for multi-chip modules. The aging sensors can also be used during the chip lifetime to monitor the device wear-out and alarm users about abnormal silicon aging rates against target mission profile. In this work, we show the wafer level test results for PMOS transistor degradation rates under NBTI stress, within wafer variability, and correlation of degradation rates between sensors stressed under different conditions.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129046870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117652
Yueying Liu, John Wood, Zongyang Hu, S. Ganguly, J. Fisher, M. Watts, S. Sheppard, D. Gajewski, Basim Noori
As GaN on SiC technology becomes accessible to commercial users for 5G applications, modeling needs from transistor to system level has become a big challenge for designers. In this work we demonstrated the strategy of using multi-physics modeling for a high power GaN HEMT PA design to achieve the stringent design target goal on the product level. The simulation result shows excellent agreement between measurements and models. Meanwhile, to facilitate the design process at system level, behavioral modeling is used to predict module level performance by integrating models in complex signal scheme environment. The final product used with Wolfspeed's 5G targeted process with reliability test validity is demonstrated in the paper as well.
随着5G应用的商业用户可以使用GaN on SiC技术，从晶体管到系统级的建模需求已成为设计人员面临的一大挑战。在这项工作中，我们展示了在高功率GaN HEMT PA设计中使用多物理场建模的策略，以在产品层面上实现严格的设计目标。仿真结果表明，实测数据与模型吻合良好。同时，为了方便系统级的设计过程，通过对复杂信号方案环境下的模型进行集成，利用行为建模来预测模块级的性能。文中还展示了Wolfspeed 5G目标工艺的最终产品，并进行了信度测试效度的验证。
{"title":"GaN HEMTs Design and Modeling for 5G","authors":"Yueying Liu, John Wood, Zongyang Hu, S. Ganguly, J. Fisher, M. Watts, S. Sheppard, D. Gajewski, Basim Noori","doi":"10.1109/IRPS48203.2023.10117652","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117652","url":null,"abstract":"As GaN on SiC technology becomes accessible to commercial users for 5G applications, modeling needs from transistor to system level has become a big challenge for designers. In this work we demonstrated the strategy of using multi-physics modeling for a high power GaN HEMT PA design to achieve the stringent design target goal on the product level. The simulation result shows excellent agreement between measurements and models. Meanwhile, to facilitate the design process at system level, behavioral modeling is used to predict module level performance by integrating models in complex signal scheme environment. The final product used with Wolfspeed's 5G targeted process with reliability test validity is demonstrated in the paper as well.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127706047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118343
J. Tan, J. H. Lim, J. Kwon, V. B. Naik, N. Raghavan, K. Pey
Spin-transfer-torque magnetic random-access memory (STT-MRAM) is a proven technology for embedded non-volatile memory applications. The backhopping phenomena in STT-MRAM, whereby the resistance of the device oscillates under higher current, has been recently explored for emerging spiking neural network applications. We report a detailed characterization of backhopping in foundry compatible STT-MRAM having ~15kb bit-cell arrays by analyzing the behavior of backhopping spike rate versus applied current and temperature. Our study shows that the backhopping in STT-MRAM exhibits the Poisson statistics with a controllable spike rate with current that displays three regimes: non-backhopping, exponential and linear. This mimics the behavior of a rectified linear unit (ReLU) neuron, a commonly used activation function in deep learning models. A spiking neural network (SNN) communication channel is simulated using the derived statistics and a first principles mathematical framework to analyze the reliability performance of backhopping-based SNN in terms of trading-off the accuracy and applied current.
{"title":"Backhopping-based STT-MRAM Poisson Spiking Neuron for Neuromorphic Computation","authors":"J. Tan, J. H. Lim, J. Kwon, V. B. Naik, N. Raghavan, K. Pey","doi":"10.1109/IRPS48203.2023.10118343","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118343","url":null,"abstract":"Spin-transfer-torque magnetic random-access memory (STT-MRAM) is a proven technology for embedded non-volatile memory applications. The backhopping phenomena in STT-MRAM, whereby the resistance of the device oscillates under higher current, has been recently explored for emerging spiking neural network applications. We report a detailed characterization of backhopping in foundry compatible STT-MRAM having ~15kb bit-cell arrays by analyzing the behavior of backhopping spike rate versus applied current and temperature. Our study shows that the backhopping in STT-MRAM exhibits the Poisson statistics with a controllable spike rate with current that displays three regimes: non-backhopping, exponential and linear. This mimics the behavior of a rectified linear unit (ReLU) neuron, a commonly used activation function in deep learning models. A spiking neural network (SNN) communication channel is simulated using the derived statistics and a first principles mathematical framework to analyze the reliability performance of backhopping-based SNN in terms of trading-off the accuracy and applied current.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10118053
P. Lenahan, E. Frantz, S. King, M. Anders, S. Moxim, J. P. Ashton, Kyle J. Myers, M. Flatté, N. Harmon
A relatively simple addition to many widely utilized semiconductor device characterization techniques can allow one to identify much of the atomic scale structure of point defects which play important roles in the electronic properties of the devices under study. This simple addition can also open up the possible exploration of the kinetics involved in some reliability phenomena as well as in multiple transport mechanisms. This addition is a small (0 to a few mT) time varying magnetic field centered upon zero field. A readily observable difference between various device responses at zero and small fields can be observed in a wide range of measurements often used in semiconductor device characterization. These measurements include metal-oxide-semiconductor field-effect transistor (MOSFET) charge pumping, metal-oxide-semiconductor (MOS) gated diode recombination current, so called direct current current-voltage (DCIV) measurements, deep level transient spectroscopy, and simple current measurements in dielectric films and in pn junctions. Multiple materials systems of great technological interest can be explored with the techniques. They are based on near zero field magnetoresistance (NZFMR) phenomena, spin-based quantum effects involving magnetic field induced changes which occur in multiple electronic transport phenomena. Because these spin-based changes are strongly affected by fundamentally well understood spin-spin interactions such as electron-nuclear hyperfine interactions or electron-electron dipolar interactions, this NZFMR response has quite substantial analytical power. The NZFMR techniques can be gainfully applied to device structures based upon numerous materials systems, among them being silicon dioxide, silicon, silicon carbide, silicon nitride and amorphous SiOC:H films utilized in interlayer dielectrics.
{"title":"Near Zero Field Magnetoresistance Spectroscopy: A New Tool in Semiconductor Reliability Physics","authors":"P. Lenahan, E. Frantz, S. King, M. Anders, S. Moxim, J. P. Ashton, Kyle J. Myers, M. Flatté, N. Harmon","doi":"10.1109/IRPS48203.2023.10118053","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10118053","url":null,"abstract":"A relatively simple addition to many widely utilized semiconductor device characterization techniques can allow one to identify much of the atomic scale structure of point defects which play important roles in the electronic properties of the devices under study. This simple addition can also open up the possible exploration of the kinetics involved in some reliability phenomena as well as in multiple transport mechanisms. This addition is a small (0 to a few mT) time varying magnetic field centered upon zero field. A readily observable difference between various device responses at zero and small fields can be observed in a wide range of measurements often used in semiconductor device characterization. These measurements include metal-oxide-semiconductor field-effect transistor (MOSFET) charge pumping, metal-oxide-semiconductor (MOS) gated diode recombination current, so called direct current current-voltage (DCIV) measurements, deep level transient spectroscopy, and simple current measurements in dielectric films and in pn junctions. Multiple materials systems of great technological interest can be explored with the techniques. They are based on near zero field magnetoresistance (NZFMR) phenomena, spin-based quantum effects involving magnetic field induced changes which occur in multiple electronic transport phenomena. Because these spin-based changes are strongly affected by fundamentally well understood spin-spin interactions such as electron-nuclear hyperfine interactions or electron-electron dipolar interactions, this NZFMR response has quite substantial analytical power. The NZFMR techniques can be gainfully applied to device structures based upon numerous materials systems, among them being silicon dioxide, silicon, silicon carbide, silicon nitride and amorphous SiOC:H films utilized in interlayer dielectrics.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127908183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1109/IRPS48203.2023.10117885
J. Hai, F. Cacho, X. Federspiel, T. Garba-Seybou, A. Divay, E. Lauga-Larroze, J. Arnould
Dynamic off-state stress for RF applications is investigated via integrated test circuits to enable GHz level testing. We have performed characterization of test circuits to ensure the dynamic stress signal waveform integrity, which is verified against model simulation data. We report a x2 gain on time-to-breakdown at 1GHz against DC TDDB off-state stress. Based on extraction of $boldsymbol{mathrm{I}_{text{Dlin}}}$ degradation, no frequency effect is observed from DC to 1GHz off-state stress conditions. Modeling of on-state and off-state interactions based on sum of degradations modes is then demonstrated and supported by experimental data.
{"title":"Integrated Test Circuit for Off-State Dynamic Drain Stress Evaluation","authors":"J. Hai, F. Cacho, X. Federspiel, T. Garba-Seybou, A. Divay, E. Lauga-Larroze, J. Arnould","doi":"10.1109/IRPS48203.2023.10117885","DOIUrl":"https://doi.org/10.1109/IRPS48203.2023.10117885","url":null,"abstract":"Dynamic off-state stress for RF applications is investigated via integrated test circuits to enable GHz level testing. We have performed characterization of test circuits to ensure the dynamic stress signal waveform integrity, which is verified against model simulation data. We report a x2 gain on time-to-breakdown at 1GHz against DC TDDB off-state stress. Based on extraction of $boldsymbol{mathrm{I}_{text{Dlin}}}$ degradation, no frequency effect is observed from DC to 1GHz off-state stress conditions. Modeling of on-state and off-state interactions based on sum of degradations modes is then demonstrated and supported by experimental data.","PeriodicalId":159030,"journal":{"name":"2023 IEEE International Reliability Physics Symposium (IRPS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116191989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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