Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638198
N. Tošić, B. Pešić, N. Stojadinovic
The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated failure mechanisms in power VDMOSFETs subjected to HTRB (High-Temperature-Reverse-Bias) test at different temperatures. It has been found that electromigration at the source/drain contacts, intermetallic processes at the solder joint and gate oxide breakdown are the major failure mechanisms limiting the reliability of investigated devices.
{"title":"Investigation of failure mechanisms in power VDMOSFETs","authors":"N. Tošić, B. Pešić, N. Stojadinovic","doi":"10.1109/IPFA.1997.638198","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638198","url":null,"abstract":"The specific application of power devices has imposed the requirement for intensive investigation of their reliability. In this paper we have investigated failure mechanisms in power VDMOSFETs subjected to HTRB (High-Temperature-Reverse-Bias) test at different temperatures. It has been found that electromigration at the source/drain contacts, intermetallic processes at the solder joint and gate oxide breakdown are the major failure mechanisms limiting the reliability of investigated devices.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638208
J. Evans, J. Evans, M. Li
Three dimensional electronics packaging technologies are emerging for many electronics system applications. Characterizing failure mechanisms, was the focus of this research. Accelerated testing and observing samples at various stages of the testing, with an Environmental Scanning Electron Microscope, were the primary methods used. Interfacial debonding of polyimides and fatigue cracking in bus structures were observed in humidity cycling and thermal cycling. These failures were the result of differential expansion of polyimide adhesives and dielectrics and interfacial degradation by moisture absorption.
{"title":"Effects of humidity and temperature cycling on 3-D packaging","authors":"J. Evans, J. Evans, M. Li","doi":"10.1109/IPFA.1997.638208","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638208","url":null,"abstract":"Three dimensional electronics packaging technologies are emerging for many electronics system applications. Characterizing failure mechanisms, was the focus of this research. Accelerated testing and observing samples at various stages of the testing, with an Environmental Scanning Electron Microscope, were the primary methods used. Interfacial debonding of polyimides and fatigue cracking in bus structures were observed in humidity cycling and thermal cycling. These failures were the result of differential expansion of polyimide adhesives and dielectrics and interfacial degradation by moisture absorption.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121461642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638125
Y. Doong, Jui-Mei Fu, Y. Hsieh
A sub-0.25 /spl mu/m defect characterization study was conducted by using in-line inspection machines to locate defects and focused ion beam system (FIB) equipped with a navigation tool to generate cross-sectional transmission electron microscopy (TEM) samples/sup 4-8/. Two failure analysis cases regarding invisible defects in optical microscope were reported in this work. One described the micro-trench formed at the bird's beak of field oxide, and the other one illustrated the etching pit formation during Poly-Si etching process.
{"title":"Combination of focused ion beam (FIB) and transmission electron microscopy (TEM) as sub-0.25 /spl mu/m defect characterization tool","authors":"Y. Doong, Jui-Mei Fu, Y. Hsieh","doi":"10.1109/IPFA.1997.638125","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638125","url":null,"abstract":"A sub-0.25 /spl mu/m defect characterization study was conducted by using in-line inspection machines to locate defects and focused ion beam system (FIB) equipped with a navigation tool to generate cross-sectional transmission electron microscopy (TEM) samples/sup 4-8/. Two failure analysis cases regarding invisible defects in optical microscope were reported in this work. One described the micro-trench formed at the bird's beak of field oxide, and the other one illustrated the etching pit formation during Poly-Si etching process.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114177770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638173
I. Kitagawa, R. Baumann, I. Takigasaki, K. Maeda, Y. Ohashi, Y. Kikuchi, S. Murata
Channel hot carrier (CHC) effects in PMOS transistors increase the drive current and reduce the threshold voltage (Vt). While these changes improve the device switching speed, the decreased Vt renders the transistor harder to "turn off". This work focused on defining the punch through voltage (BVDSS) of PMOS transistors from a CMOS submicron process as a function of gate length and stress voltage. A model and predictions of PMOS device lifetimes based on the CHC-induced BVDSS degradation is presented.
{"title":"Channel hot carrier impact on the reliability performance of PMOS submicron transistors","authors":"I. Kitagawa, R. Baumann, I. Takigasaki, K. Maeda, Y. Ohashi, Y. Kikuchi, S. Murata","doi":"10.1109/IPFA.1997.638173","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638173","url":null,"abstract":"Channel hot carrier (CHC) effects in PMOS transistors increase the drive current and reduce the threshold voltage (Vt). While these changes improve the device switching speed, the decreased Vt renders the transistor harder to \"turn off\". This work focused on defining the punch through voltage (BVDSS) of PMOS transistors from a CMOS submicron process as a function of gate length and stress voltage. A model and predictions of PMOS device lifetimes based on the CHC-induced BVDSS degradation is presented.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121071682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638120
C. Lee, R. Tan Check-Eng, J. Ong Wai-Lian, R. Gopalakrishnan, K. Nyunt, A. Wong
An investigation of O/sub 2/, Ar and Ar/H/sub 2/ plasma cleaning was carried out on PBGA substrates to study its effects on surface cleanliness, wire bondability and moulding compound/solder mask adhesion. Optimisation of the plasma parameters was achieved using the contact angle method and verified by AES, XPS and wedge pull test. Generally, it was noted that the wedge bond quality and moisture sensitivity of a 225 I/O PBGA were improved after plasma cleaning. Furthermore, AFM characterization revealed that the solder mask has undergone plasma induced surface modification. Cross-contamination of Au and F traces on the solder mask which has occurred during plasma cleaning was analysed by XPS. Results from this study have demonstrated the benefits and consequences of plasma cleaning for PBGA.
{"title":"Plasma cleaning for plastic ball grid array (PBGA): a study on surface cleanliness, wire bondability and adhesion","authors":"C. Lee, R. Tan Check-Eng, J. Ong Wai-Lian, R. Gopalakrishnan, K. Nyunt, A. Wong","doi":"10.1109/IPFA.1997.638120","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638120","url":null,"abstract":"An investigation of O/sub 2/, Ar and Ar/H/sub 2/ plasma cleaning was carried out on PBGA substrates to study its effects on surface cleanliness, wire bondability and moulding compound/solder mask adhesion. Optimisation of the plasma parameters was achieved using the contact angle method and verified by AES, XPS and wedge pull test. Generally, it was noted that the wedge bond quality and moisture sensitivity of a 225 I/O PBGA were improved after plasma cleaning. Furthermore, AFM characterization revealed that the solder mask has undergone plasma induced surface modification. Cross-contamination of Au and F traces on the solder mask which has occurred during plasma cleaning was analysed by XPS. Results from this study have demonstrated the benefits and consequences of plasma cleaning for PBGA.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"128 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133255695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638186
G. L. Teh, W. Chim
A change in the pre-breakdown trap generation under constant voltage stressing (CVS) was observed in thin oxides subjected to positive ESD pulses applied to the gate electrode. Results show that ESD pulses will create both positive and neutral traps, the latter being highly susceptible to electron trapping. It was also found that the damage in oxides subjected to low-level ESD events (i.e. number of ESD pulses less than 20) can be annealed out electrically. These annealed oxides show electrical characteristics that are identical to that of a non-ESD-stressed oxide.
{"title":"Pre-breakdown charge trapping in ESD stressed thin MOS gate oxides","authors":"G. L. Teh, W. Chim","doi":"10.1109/IPFA.1997.638186","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638186","url":null,"abstract":"A change in the pre-breakdown trap generation under constant voltage stressing (CVS) was observed in thin oxides subjected to positive ESD pulses applied to the gate electrode. Results show that ESD pulses will create both positive and neutral traps, the latter being highly susceptible to electron trapping. It was also found that the damage in oxides subjected to low-level ESD events (i.e. number of ESD pulses less than 20) can be annealed out electrically. These annealed oxides show electrical characteristics that are identical to that of a non-ESD-stressed oxide.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131805894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638342
J. Mun, Hae-cheon Kim, Chung-Hwan Kim, Min-Gun Kim, Jae Jin Lee, K. Pyun
The noise degradation of GaAs MESFETs was investigated by thermal step stress tests with no bias in atmosphere. Minimum noise figure, associated gain, scattering parameters, and C-V profiles were measured during the tests. The noise degradation is mainly attributed to the decrease of AC transconductance, resulting from the carrier compensation by Ga vacancies in the channel. The decrease of effective carrier concentration resulting from the thermally activated interdiffusion between the gate metal and the GaAs channel layer is proposed to be the main failure mechanism for noise degradation of GaAs MESFETs.
{"title":"Failure analysis of noise characteristics in GaAs MESFETs with parametric modeling approach","authors":"J. Mun, Hae-cheon Kim, Chung-Hwan Kim, Min-Gun Kim, Jae Jin Lee, K. Pyun","doi":"10.1109/IPFA.1997.638342","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638342","url":null,"abstract":"The noise degradation of GaAs MESFETs was investigated by thermal step stress tests with no bias in atmosphere. Minimum noise figure, associated gain, scattering parameters, and C-V profiles were measured during the tests. The noise degradation is mainly attributed to the decrease of AC transconductance, resulting from the carrier compensation by Ga vacancies in the channel. The decrease of effective carrier concentration resulting from the thermally activated interdiffusion between the gate metal and the GaAs channel layer is proposed to be the main failure mechanism for noise degradation of GaAs MESFETs.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132186450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638123
H. Sumitomo, T. Nakamura
An easy and rapid failure analysis method to detect CMOS-LSI open faults has been developed. This method exploits both the properties of CMOS structure and the voltage contrast image. By supplying pulsed signal to VDD and GND, and observing the voltage contrast image, open faults appear different from the rest of the LSI. An image processing system is proposed which improves image observability and thereby decreases inspection time.
{"title":"Open fault detection method for CMOS-LSI by supplying pulsed voltage signal to VDD and GND lines","authors":"H. Sumitomo, T. Nakamura","doi":"10.1109/IPFA.1997.638123","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638123","url":null,"abstract":"An easy and rapid failure analysis method to detect CMOS-LSI open faults has been developed. This method exploits both the properties of CMOS structure and the voltage contrast image. By supplying pulsed signal to VDD and GND, and observing the voltage contrast image, open faults appear different from the rest of the LSI. An image processing system is proposed which improves image observability and thereby decreases inspection time.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638177
C. Lou, C. Tan, W. Chim, D. Chan
We present a new measurement technique-the drain current-conductance method (DCCM) to extract the gate-bias dependent effective channel mobility (/spl mu//sub eff/) and series resistances (R/sub s/ and R/sub d/) of drain-engineered MOSFETs. Experimental verification for devices with differing channel lengths and after hot-carrier stresses showed that this technique is accurate and effective. The parameters extracted has provided further insight into the asymmetries of graded junctions, and the damage mechanisms of hot-carrier degraded MOSFETs.
{"title":"Effective channel mobility and series resistance extraction for fresh and hot-carrier stressed graded junction MOSFETs using a single device","authors":"C. Lou, C. Tan, W. Chim, D. Chan","doi":"10.1109/IPFA.1997.638177","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638177","url":null,"abstract":"We present a new measurement technique-the drain current-conductance method (DCCM) to extract the gate-bias dependent effective channel mobility (/spl mu//sub eff/) and series resistances (R/sub s/ and R/sub d/) of drain-engineered MOSFETs. Experimental verification for devices with differing channel lengths and after hot-carrier stresses showed that this technique is accurate and effective. The parameters extracted has provided further insight into the asymmetries of graded junctions, and the damage mechanisms of hot-carrier degraded MOSFETs.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1964 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638119
N. Zhang, M. Mcnicholas, N. Colvin
A PVD Cr-CrCu-Cu metal scheme for flip chip applications was investigated varying the conditions of deposition power and temperature, and film thickness. The thin film stress and resistivity of the Cr-CrCu-Cu multilayers and the effect of film and thermal cycle reliability were studied. Thermal cycle reliability results proved to be a function of both the CrCu alloy and the Cu overlayer thickness. Analytical Electron Microscopy (AEM) results support the diffusion barrier relationship of CrCu layer.
{"title":"Microstructural and compositional failure analysis of Cr-CrCu-Cu thin films for ball grid array (BGA) applications","authors":"N. Zhang, M. Mcnicholas, N. Colvin","doi":"10.1109/IPFA.1997.638119","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638119","url":null,"abstract":"A PVD Cr-CrCu-Cu metal scheme for flip chip applications was investigated varying the conditions of deposition power and temperature, and film thickness. The thin film stress and resistivity of the Cr-CrCu-Cu multilayers and the effect of film and thermal cycle reliability were studied. Thermal cycle reliability results proved to be a function of both the CrCu alloy and the Cu overlayer thickness. Analytical Electron Microscopy (AEM) results support the diffusion barrier relationship of CrCu layer.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130579923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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