Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638151
W. Wong, J. Thong, J. Phang
Common charging artifacts in the scanning electron microscope (SEM) are discussed. A novel method employing front-end control of the SEM beam voltage and scanning to achieve charging compensation was also discussed. Results show that the new technique is effective in reducing highly-negative charging as well as providing a means for the experimental measurement of charging using the electrostatic mirror.
{"title":"Charging identification and compensation in the scanning electron microscope","authors":"W. Wong, J. Thong, J. Phang","doi":"10.1109/IPFA.1997.638151","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638151","url":null,"abstract":"Common charging artifacts in the scanning electron microscope (SEM) are discussed. A novel method employing front-end control of the SEM beam voltage and scanning to achieve charging compensation was also discussed. Results show that the new technique is effective in reducing highly-negative charging as well as providing a means for the experimental measurement of charging using the electrostatic mirror.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638329
C. Y. Chiang
Typically, latch-up is associated with higher input voltage at port pins as compared to power pins, Vcc, causing damage to the protection circuitry or input buffer circuitry. However, for one of the products that is manufactured in Intel, Penang, there have been a number of line yield losses due to latch-up at the RAM control circuitry which happened during burn-in. In this study we have shown the latch-up failures that occasionally caused some yield loss are related to the noise that is generated during high speed switching of transistors in the RAM. We have established the failure mechanism and root cause of the latch-up through layout, schematic and device physics analysis. Implementation of a lower burn-in frequency managed to eliminate the failure mode.
{"title":"Latch-up at RAM control circuitry","authors":"C. Y. Chiang","doi":"10.1109/IPFA.1997.638329","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638329","url":null,"abstract":"Typically, latch-up is associated with higher input voltage at port pins as compared to power pins, Vcc, causing damage to the protection circuitry or input buffer circuitry. However, for one of the products that is manufactured in Intel, Penang, there have been a number of line yield losses due to latch-up at the RAM control circuitry which happened during burn-in. In this study we have shown the latch-up failures that occasionally caused some yield loss are related to the noise that is generated during high speed switching of transistors in the RAM. We have established the failure mechanism and root cause of the latch-up through layout, schematic and device physics analysis. Implementation of a lower burn-in frequency managed to eliminate the failure mode.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116686700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638070
Taekoo Lee, Jin-Hyuk Lee, I. Jung
In this study, the failure mechanism of solder ball connect in chip scale packaging (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis. The macro-micro-coupling technique was used in the current model. There exist two contributors to solder ball cracking: shear stress and warpage of the package. It was recognized that shear stress prevailed over warpage of the package in impact on solder ball cracking in the present type of CSP.
{"title":"Finite element analysis for solder ball failures in chip scale package","authors":"Taekoo Lee, Jin-Hyuk Lee, I. Jung","doi":"10.1109/IPFA.1997.638070","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638070","url":null,"abstract":"In this study, the failure mechanism of solder ball connect in chip scale packaging (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis. The macro-micro-coupling technique was used in the current model. There exist two contributors to solder ball cracking: shear stress and warpage of the package. It was recognized that shear stress prevailed over warpage of the package in impact on solder ball cracking in the present type of CSP.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116369056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638206
W. Lau, P. Qian, R. Zhao
For shallow n/sup +//p and p/sup +//n junctions with TiSi/sub 2/ contacts, the leakage current quite frequently increases after silicidation. When the Ti layer for silicidation is thick, the leakage current of shallow p/sup +//n junctions increases much more strongly than shallow n/sup +//p junctions after silicidation. This is usually explained by Si consumption due to silicidation. When the Ti layer for silicidation is thin, the leakage current of shallow n/sup +//p junctions increases more strongly than shallow p/sup +//n junctions after silicidation. In this paper, a new mechanism of Ti/sup +/ drift due to the built-in electric field is proposed to explain the larger leakage current of shallow n/sup +//p junctions than that of shallow p/sup +//n junctions after silicidation. A numerical simulation with the pc-1d software package was performed to calculate the electric field distribution for shallow junctions under various conditions.
{"title":"A new mechanism of leakage current in ultra-shallow junctions with TiSi/sub 2/ contacts","authors":"W. Lau, P. Qian, R. Zhao","doi":"10.1109/IPFA.1997.638206","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638206","url":null,"abstract":"For shallow n/sup +//p and p/sup +//n junctions with TiSi/sub 2/ contacts, the leakage current quite frequently increases after silicidation. When the Ti layer for silicidation is thick, the leakage current of shallow p/sup +//n junctions increases much more strongly than shallow n/sup +//p junctions after silicidation. This is usually explained by Si consumption due to silicidation. When the Ti layer for silicidation is thin, the leakage current of shallow n/sup +//p junctions increases more strongly than shallow p/sup +//n junctions after silicidation. In this paper, a new mechanism of Ti/sup +/ drift due to the built-in electric field is proposed to explain the larger leakage current of shallow n/sup +//p junctions than that of shallow p/sup +//n junctions after silicidation. A numerical simulation with the pc-1d software package was performed to calculate the electric field distribution for shallow junctions under various conditions.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638154
Tang Ting-Nguon, C. Prancis, Teh Swee-Thian
Failure finger-print recognition is an effective and speedy method towards accurate root cause determination. This paper demonstrates the method of identifying ESD HBM and CDM failure finger-print through simulation on an EPROM. Through the use of CDM failure finger-print, the root cause of a catastrophic fallout was determined and corrective action effected.
{"title":"ESD failure finger-print-an effective and accurate method for root cause determination","authors":"Tang Ting-Nguon, C. Prancis, Teh Swee-Thian","doi":"10.1109/IPFA.1997.638154","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638154","url":null,"abstract":"Failure finger-print recognition is an effective and speedy method towards accurate root cause determination. This paper demonstrates the method of identifying ESD HBM and CDM failure finger-print through simulation on an EPROM. Through the use of CDM failure finger-print, the root cause of a catastrophic fallout was determined and corrective action effected.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122169183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638064
T. Roh, D. Lee, Jongdae Kim, K. Baek, J. Koo, D. Lee, K. Nam
The reliability of new ultrathin oxides grown by high pressure oxidation (HIPOX) has been evaluated in order to use gate insulators for ULSI MOSFETs. From the results of the TDDB characteristics of 75 /spl Aring/ thick HIPOX oxide nitrided at 1100/spl deg/C for 30 sec, the lifetime of the nitrided-HIPOX oxide at negative constant current stress, -1.0/spl times/10/sup -6/ A/cm/sup 2/ is about 1.2/spl times/10/sup 9/ sec. Initially, the midgap interface trap density (D/sub itm/) of 75 /spl Aring/ thick nitrided-HIPOX oxide is about 2.0/spl times/10/sup 10/ cm/sup -2//spl middot/eV/sup -1/ which is comparable to that of control oxide grown by conventional thermal oxidation. The /spl Delta/D/sub itm/ of the nitrided-HIPOX oxide subjected to the stressing time of 1/spl times/10/sup 4/ sec under -0.1 A/cm/sup 2/ is 1.1/spl times/10/sup 11/ cm/sup -2//spl middot/eV/sup -1/ which is lower than that (1.5/spl times/10/sup 11/ cm/sup -2//spl middot/eV/sup -1/) of the control oxide under the same stressing condition.
{"title":"Reliability investigation of ultrathin oxides grown by high pressure oxidation and nitrided in N/sub 2/O for ULSI device applications","authors":"T. Roh, D. Lee, Jongdae Kim, K. Baek, J. Koo, D. Lee, K. Nam","doi":"10.1109/IPFA.1997.638064","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638064","url":null,"abstract":"The reliability of new ultrathin oxides grown by high pressure oxidation (HIPOX) has been evaluated in order to use gate insulators for ULSI MOSFETs. From the results of the TDDB characteristics of 75 /spl Aring/ thick HIPOX oxide nitrided at 1100/spl deg/C for 30 sec, the lifetime of the nitrided-HIPOX oxide at negative constant current stress, -1.0/spl times/10/sup -6/ A/cm/sup 2/ is about 1.2/spl times/10/sup 9/ sec. Initially, the midgap interface trap density (D/sub itm/) of 75 /spl Aring/ thick nitrided-HIPOX oxide is about 2.0/spl times/10/sup 10/ cm/sup -2//spl middot/eV/sup -1/ which is comparable to that of control oxide grown by conventional thermal oxidation. The /spl Delta/D/sub itm/ of the nitrided-HIPOX oxide subjected to the stressing time of 1/spl times/10/sup 4/ sec under -0.1 A/cm/sup 2/ is 1.1/spl times/10/sup 11/ cm/sup -2//spl middot/eV/sup -1/ which is lower than that (1.5/spl times/10/sup 11/ cm/sup -2//spl middot/eV/sup -1/) of the control oxide under the same stressing condition.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"194 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132764507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638067
A. Trigg
An infrared photoemission microscope (IRPEM) based on a cadmium mercury telluride (CMT) focal plane array, developed originally for astronomical applications and covering the wavelength range 800 to 2500 nm, has been used to characterise emission phenomena in several semiconductor devices. Using the p-n junction of a simple transistor it was found that in forward bias three emission mechanisms operate. As well as the expected band gap emission, localised emission was wavelengths. There was also corresponding to a temperature rise of 2-3/spl deg/C. In reverse bias, emission was localised to one or more sites depending on the current. The ability of the system to detect emission from the backside of an un-thinned integrated circuit was demonstrated using a subscriber line interface circuit (SLIC) and BiCMOS buffer.
{"title":"The infrared photoemission microscope as a tool for semiconductor device failure analysis","authors":"A. Trigg","doi":"10.1109/IPFA.1997.638067","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638067","url":null,"abstract":"An infrared photoemission microscope (IRPEM) based on a cadmium mercury telluride (CMT) focal plane array, developed originally for astronomical applications and covering the wavelength range 800 to 2500 nm, has been used to characterise emission phenomena in several semiconductor devices. Using the p-n junction of a simple transistor it was found that in forward bias three emission mechanisms operate. As well as the expected band gap emission, localised emission was wavelengths. There was also corresponding to a temperature rise of 2-3/spl deg/C. In reverse bias, emission was localised to one or more sites depending on the current. The ability of the system to detect emission from the backside of an un-thinned integrated circuit was demonstrated using a subscriber line interface circuit (SLIC) and BiCMOS buffer.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129698958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638150
T. Sheng, G. Goh, C. Tung, J.L.F. Wang, J. K. Cheng
A new precision transmission electron microscopy (XTEM) sample preparation method was developed and reported here. No mechanical polishing and grinding are needed. The main difference of this method over conventional method using focused ion beam (FIB) is that the sample sectioned with FIB can be extracted directly from the wafer site and transferred to a carbon supporting film for TEM examination. With this technique, a cross section TEM sample can be prepared easily and quickly, thus enhancing both productivity and turnaround time.
{"title":"FIB precision TEM sample preparation using carbon replica","authors":"T. Sheng, G. Goh, C. Tung, J.L.F. Wang, J. K. Cheng","doi":"10.1109/IPFA.1997.638150","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638150","url":null,"abstract":"A new precision transmission electron microscopy (XTEM) sample preparation method was developed and reported here. No mechanical polishing and grinding are needed. The main difference of this method over conventional method using focused ion beam (FIB) is that the sample sectioned with FIB can be extracted directly from the wafer site and transferred to a carbon supporting film for TEM examination. With this technique, a cross section TEM sample can be prepared easily and quickly, thus enhancing both productivity and turnaround time.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638356
T. Sheng, C. Tung, J.L.F. Wang
Transmission electron microscopic examination (TEM) on VLSI process device is presented. Local step coverage and non-uniformity on silicidation has induced high sheet resistance and high contact resistance problems. Native oxide within submicron contacts also increases contact resistivity.
{"title":"Transmission electron microscopy of high threshold voltage, high contact resistance, and high sheet resistance of MOS device","authors":"T. Sheng, C. Tung, J.L.F. Wang","doi":"10.1109/IPFA.1997.638356","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638356","url":null,"abstract":"Transmission electron microscopic examination (TEM) on VLSI process device is presented. Local step coverage and non-uniformity on silicidation has induced high sheet resistance and high contact resistance problems. Native oxide within submicron contacts also increases contact resistivity.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125526002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638343
X. Liu, J. Phang, D. Chan, W. Chim
We report a new concept for the localisation of metallization defects by using cathodoluminescence (CL) imaging. The CL image contrast, which is due to the difference in light reflection characteristics of the contact metal and substrate materials, is used for the localisation of metallization defects. This method is applicable to devices with a luminescent passivation layer and a non-luminescent substrate. Experimental study of a silicon device with a passivation layer of Si/sub 3/N/sub 4//a-SiO/sub 2/ is reported.
{"title":"A new method for the localisation of metallization defects using cathodoluminescence imaging","authors":"X. Liu, J. Phang, D. Chan, W. Chim","doi":"10.1109/IPFA.1997.638343","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638343","url":null,"abstract":"We report a new concept for the localisation of metallization defects by using cathodoluminescence (CL) imaging. The CL image contrast, which is due to the difference in light reflection characteristics of the contact metal and substrate materials, is used for the localisation of metallization defects. This method is applicable to devices with a luminescent passivation layer and a non-luminescent substrate. Experimental study of a silicon device with a passivation layer of Si/sub 3/N/sub 4//a-SiO/sub 2/ is reported.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123588757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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