Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638367
K. Tan, S.H. Tan, S. H. Ong
Photoinduced current can be measured and used to modulate the gray-level of the OBIC images. Thus, the OBIC image can be used to localize the damaged transistor in LSI and VLSI devices. This is because when the pn junctions are destroyed, the leakage path no longer exhibits any blocking behavior, and thus no OBIC effect will be present. This paper presents two cases of failure analysis performed on analog devices using OBIC technique. The analysis steps and methodology used to determine the failure mechanism are described.
{"title":"Functional failure analysis on analog device by optical beam induced current technique","authors":"K. Tan, S.H. Tan, S. H. Ong","doi":"10.1109/IPFA.1997.638367","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638367","url":null,"abstract":"Photoinduced current can be measured and used to modulate the gray-level of the OBIC images. Thus, the OBIC image can be used to localize the damaged transistor in LSI and VLSI devices. This is because when the pn junctions are destroyed, the leakage path no longer exhibits any blocking behavior, and thus no OBIC effect will be present. This paper presents two cases of failure analysis performed on analog devices using OBIC technique. The analysis steps and methodology used to determine the failure mechanism are described.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129905473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638063
L. Balk, R. M. Cramer, G.B.M. Fiege
The continuous decrease of the lateral dimensions of state-of-the-art integrated devices has led to a steady increase of their power densities. As a result, local heating effects are known to cause malfunctions or the destruction of these devices. In order to overcome these problems related with localized heat dissipation, new techniques for thermal analyses with high spatial resolutions have to be developed. This includes temperature as well as thermal conductivity or diffusivity measurements. In this work we discuss the recent progress of scanning probe microscopy based thermal analysis techniques and present concepts for further improvements.
{"title":"Thermal analyses by means of scanning probe microscopy [CMOS ICs]","authors":"L. Balk, R. M. Cramer, G.B.M. Fiege","doi":"10.1109/IPFA.1997.638063","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638063","url":null,"abstract":"The continuous decrease of the lateral dimensions of state-of-the-art integrated devices has led to a steady increase of their power densities. As a result, local heating effects are known to cause malfunctions or the destruction of these devices. In order to overcome these problems related with localized heat dissipation, new techniques for thermal analyses with high spatial resolutions have to be developed. This includes temperature as well as thermal conductivity or diffusivity measurements. In this work we discuss the recent progress of scanning probe microscopy based thermal analysis techniques and present concepts for further improvements.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128677799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638156
T. Yeoh
Electrostatic discharge (ESD) damage is a common failure mechanism that is seen on CMOS integrated circuit devices. Due to the ever increasing shrinkage in transistor geometries, prevention of ESD damage will become increasingly important. This paper discusses the various device level ESD in the form of power supply clamps. There are numerous power supply clamps that are currently available such as the grounded gate, thick field oxide (TFO), diode string and cantilever diode structures. Selection of the right ESD power supply clamp is essential from the aspects of their limitations, weaknesses, silicon space and effectiveness to ensure robustness during to ESD stresses on devices.
{"title":"ESD effects on power supply clamps [CMOS ICs]","authors":"T. Yeoh","doi":"10.1109/IPFA.1997.638156","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638156","url":null,"abstract":"Electrostatic discharge (ESD) damage is a common failure mechanism that is seen on CMOS integrated circuit devices. Due to the ever increasing shrinkage in transistor geometries, prevention of ESD damage will become increasingly important. This paper discusses the various device level ESD in the form of power supply clamps. There are numerous power supply clamps that are currently available such as the grounded gate, thick field oxide (TFO), diode string and cantilever diode structures. Selection of the right ESD power supply clamp is essential from the aspects of their limitations, weaknesses, silicon space and effectiveness to ensure robustness during to ESD stresses on devices.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"56 18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114443404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638152
M. Ker, Tung-Yang Chen, Chung-Yu Wu
Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower poly-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.
{"title":"New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area","authors":"M. Ker, Tung-Yang Chen, Chung-Yu Wu","doi":"10.1109/IPFA.1997.638152","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638152","url":null,"abstract":"Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower poly-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127344004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638201
W. Tan, Goh Ko Kah, D. Corum
EOS (Electrical Over-Stress) and ESD (Electro-Static Discharge) damage in sub-micron integrated circuits are often subtle and difficult to characterize. As transistor sizes shrink, we need to be more and more concerned about channel hot electrons (CHC), charge trapping and other "invisible" mechanisms that can degrade device performance. This paper describes an example of just such an occurrence in 0.6 um DRAM where various disciplines were required to successfully isolate the problem. This particular case involved a catastrophic Vt shift at a transistor in the RAS control buffer. Even though this Vt shift was catastrophic from a transistor view-point, the overall electrical performance based on system use conditions was unaffected. This would imply that similar EOS events in system applications could create "walking wounded" devices that may be potential reliability problems.
亚微米集成电路中的电气过应力(EOS)和静电放电(ESD)损伤通常是微妙且难以表征的。随着晶体管尺寸的缩小，我们需要越来越关注通道热电子(CHC)、电荷捕获和其他可能降低器件性能的“不可见”机制。本文描述了在0.6 um DRAM中发生的这种情况的一个例子，其中需要各种学科来成功地隔离问题。这种特殊情况涉及到RAS控制缓冲器中晶体管的灾难性Vt移位。尽管从晶体管的角度来看，这种Vt位移是灾难性的，但基于系统使用条件的整体电气性能并未受到影响。这意味着系统应用程序中类似的EOS事件可能会创建“行走受伤”的设备，这可能是潜在的可靠性问题。
{"title":"EOS induced transistor shift in submicron DRAMs","authors":"W. Tan, Goh Ko Kah, D. Corum","doi":"10.1109/IPFA.1997.638201","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638201","url":null,"abstract":"EOS (Electrical Over-Stress) and ESD (Electro-Static Discharge) damage in sub-micron integrated circuits are often subtle and difficult to characterize. As transistor sizes shrink, we need to be more and more concerned about channel hot electrons (CHC), charge trapping and other \"invisible\" mechanisms that can degrade device performance. This paper describes an example of just such an occurrence in 0.6 um DRAM where various disciplines were required to successfully isolate the problem. This particular case involved a catastrophic Vt shift at a transistor in the RAS control buffer. Even though this Vt shift was catastrophic from a transistor view-point, the overall electrical performance based on system use conditions was unaffected. This would imply that similar EOS events in system applications could create \"walking wounded\" devices that may be potential reliability problems.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122595940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638203
Y. Hsieh, Yang-Chu Hwang, Jui-Mei Fu, Yuan-Ching Peng, Lih-Juann Chen
Ion implantation into contact holes has been widely used to dope the specific contact area and to reduce the contact resistance. In this study, mask edge defects were observed at the edge area of small contact holes (<0.5 um) with high aspect ratio (a/c>4), which resulted in multiplied dislocations penetrating into Si substrate for more than 0.3 um after back-end processings. Those dislocations were identified to be Schockley partials dislocations and stair rod dislocations lying on 4 sets of inclined (111)Si planes.
{"title":"Dislocation multiplication inside contact holes","authors":"Y. Hsieh, Yang-Chu Hwang, Jui-Mei Fu, Yuan-Ching Peng, Lih-Juann Chen","doi":"10.1109/IPFA.1997.638203","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638203","url":null,"abstract":"Ion implantation into contact holes has been widely used to dope the specific contact area and to reduce the contact resistance. In this study, mask edge defects were observed at the edge area of small contact holes (<0.5 um) with high aspect ratio (a/c>4), which resulted in multiplied dislocations penetrating into Si substrate for more than 0.3 um after back-end processings. Those dislocations were identified to be Schockley partials dislocations and stair rod dislocations lying on 4 sets of inclined (111)Si planes.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115166952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638126
M. Natarajan, T. Sheng, K. Pey, Y. Lee, M. Radhakrishnan
The results of physical analysis carried out on Dynamic Random Access Memory (DRAM) devices, using Scanning Capacitance Microscopy (SCM) and Transmission Electron Microscopy (TEM) to investigate specifically the dopant profile at the sidewall of the trench capacitor structures is presented here. The SCM results provide information on the dopant metrology on samples, whereas the TEM analysis, which includes junction delineation, further supports the finding of dopant distribution as well as other physical phenomena.
{"title":"Analysis of dopant metrology using scanning capacitance microscopy and transmission electron microscopy as complementary techniques","authors":"M. Natarajan, T. Sheng, K. Pey, Y. Lee, M. Radhakrishnan","doi":"10.1109/IPFA.1997.638126","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638126","url":null,"abstract":"The results of physical analysis carried out on Dynamic Random Access Memory (DRAM) devices, using Scanning Capacitance Microscopy (SCM) and Transmission Electron Microscopy (TEM) to investigate specifically the dopant profile at the sidewall of the trench capacitor structures is presented here. The SCM results provide information on the dopant metrology on samples, whereas the TEM analysis, which includes junction delineation, further supports the finding of dopant distribution as well as other physical phenomena.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638214
M. Mohanbabu, S. Y. Khim, E. Durai
This paper describes the surface crack on the Silicon die of a LOC packaged DRAM device. Surface crack was found to occur on the die at one edge, after reliability tests. The root cause was found to be the interaction of the LOC tape that exceed the die area covered by the protective PIX, and the scribe structures at the saw street due to thermal stress on the tape. This paper presents the fractographical analysis done on a failed unit to find the root cause, sample preparation needed, and the micrographs of the nature of the crack and the striations observed in the crack site using the optical microscope, SEM and the Laser Scan Microscope (LSM) confocal imaging.
{"title":"Fractographic analysis on the die surface crack of a LOC packaged DRAM","authors":"M. Mohanbabu, S. Y. Khim, E. Durai","doi":"10.1109/IPFA.1997.638214","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638214","url":null,"abstract":"This paper describes the surface crack on the Silicon die of a LOC packaged DRAM device. Surface crack was found to occur on the die at one edge, after reliability tests. The root cause was found to be the interaction of the LOC tape that exceed the die area covered by the protective PIX, and the scribe structures at the saw street due to thermal stress on the tape. This paper presents the fractographical analysis done on a failed unit to find the root cause, sample preparation needed, and the micrographs of the nature of the crack and the striations observed in the crack site using the optical microscope, SEM and the Laser Scan Microscope (LSM) confocal imaging.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131858814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638065
K.V. Loiko, I.V. Peidous, H. Ho, E.K.B. Quek, D.H.Y. Lim
The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation manufacturing are presented. The described method for reliability analysis allows one to reveal the potential capability of a current technology.
{"title":"Methodology for ULSI LOCOS isolation built-in reliability analysis","authors":"K.V. Loiko, I.V. Peidous, H. Ho, E.K.B. Quek, D.H.Y. Lim","doi":"10.1109/IPFA.1997.638065","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638065","url":null,"abstract":"The results of studying the mechanisms of CMOS ULSI LOCOS isolation failures and an effective approach to qualifying the technological processes of isolation manufacturing are presented. The described method for reliability analysis allows one to reveal the potential capability of a current technology.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124053562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-07-21DOI: 10.1109/IPFA.1997.638188
M. Bahrami, B. Fishbein, P. Lindo
Time Dependent Dielectric Breakdown analysis is performed on large area gate oxide to characterize the extrinsic portion of distribution. We use failure distribution comparison to identify the proper failure criteria, and calculate acceleration parameters. A thermal activation energy of 0.32 eV was obtained for the extrinsic population. Failure analysis was performed an samples from early fail and extrinsic populations and found different mechanisms responsible for the failures. Two scaling models were evaluated for their effectiveness for correlating fast and slow oxide tests, and predicting fallout under burn-in and operating conditions.
{"title":"Low-field time dependent dielectric breakdown characterization of very large area gate oxide [CMOS]","authors":"M. Bahrami, B. Fishbein, P. Lindo","doi":"10.1109/IPFA.1997.638188","DOIUrl":"https://doi.org/10.1109/IPFA.1997.638188","url":null,"abstract":"Time Dependent Dielectric Breakdown analysis is performed on large area gate oxide to characterize the extrinsic portion of distribution. We use failure distribution comparison to identify the proper failure criteria, and calculate acceleration parameters. A thermal activation energy of 0.32 eV was obtained for the extrinsic population. Failure analysis was performed an samples from early fail and extrinsic populations and found different mechanisms responsible for the failures. Two scaling models were evaluated for their effectiveness for correlating fast and slow oxide tests, and predicting fallout under burn-in and operating conditions.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114759099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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