Facial recognition technology has made significant progress. However, variable lighting conditions can affect its performance. Considering the need to scan facial skin for recognition purposes, this study proposes a miniature optoelectronic acquisition system for skin in the near-infrared range. The system utilizes the C11708MA photodetector from Hamamatsu Photonics’ MS series as the probe for spectral data acquisition. Other hardware components are designed accordingly. A three-stage amplification buffer circuit is employed as the front-end acquisition and preprocessing circuit. The AD7671 chip from Analog Devices Inc. is selected as the AD converter, and the communication module utilizes the CY7C68013 chip from Cypress’ EZ-USB FX2 series. The control and transmission module employs the EP2C5T144C8N FPGA chip from ALTERA’s Cyclone II generation. In order to address the power supply requirements of the CY7C68013 USB chip (3.3 V), the FPGA core (1.2 V), and the AD7671 and front-end preprocessing circuit (5 V), AMS1117 voltage regulator chips are designed for stable 5 V–1.2 V and 5 V–3.3 V power supplies. In the experiments, wavelength calibration and spectral preprocessing are performed on the system prior to data processing. Near-infrared reflectance spectra of different skin conditions (melanoma, vitiligo) are compared with normal skin. The results demonstrate the accurate assessment capability of the designed infrared optoelectronic skin detection system. Facial skin data obtained from the system are used to generate facial images, and the recognition performance of different detection systems is compared in an algorithmic environment, thereby demonstrating the promising application prospects of the infrared optoelectronic skin detection system in the field of facial recognition.
面部识别技术取得了重大进展。然而，多变的光照条件会影响其性能。考虑到需要扫描面部皮肤以进行识别，本研究提出了一种近红外范围的微型皮肤光电采集系统。该系统采用滨松光电公司的MS系列C11708MA光电探测器作为光谱数据采集探头。其他硬件组件也相应设计。采用三级放大缓冲电路作为前端采集和预处理电路。AD转换器选用Analog Devices公司的AD7671芯片，通信模块采用Cypress公司EZ-USB FX2系列的CY7C68013芯片。控制和传输模块采用ALTERA Cyclone II代的EP2C5T144C8N FPGA芯片。为了解决CY7C68013 USB芯片(3.3 V)、FPGA核心(1.2 V)、AD7671和前端预处理电路(5 V)的供电需求，设计了AMS1117稳压芯片，提供稳定的5 V - 1.2 V和5 V - 3.3 V电源。在实验中，在数据处理之前对系统进行了波长校准和光谱预处理。不同皮肤状况(黑色素瘤、白癜风)的近红外反射光谱与正常皮肤进行比较。结果表明，所设计的红外光电皮肤检测系统具有准确的评估能力。利用系统获取的面部皮肤数据生成面部图像，并在算法环境下比较不同检测系统的识别性能，从而展示了红外光电皮肤检测系统在面部识别领域的良好应用前景。
{"title":"Skin Detection System Using Infrared Optoelectronic Technology and Its Application in Facial Recognition","authors":"Liangxue Zhu, Guangyu Zhu","doi":"10.1166/jno.2023.3451","DOIUrl":"https://doi.org/10.1166/jno.2023.3451","url":null,"abstract":"Facial recognition technology has made significant progress. However, variable lighting conditions can affect its performance. Considering the need to scan facial skin for recognition purposes, this study proposes a miniature optoelectronic acquisition system for skin in the near-infrared range. The system utilizes the C11708MA photodetector from Hamamatsu Photonics’ MS series as the probe for spectral data acquisition. Other hardware components are designed accordingly. A three-stage amplification buffer circuit is employed as the front-end acquisition and preprocessing circuit. The AD7671 chip from Analog Devices Inc. is selected as the AD converter, and the communication module utilizes the CY7C68013 chip from Cypress’ EZ-USB FX2 series. The control and transmission module employs the EP2C5T144C8N FPGA chip from ALTERA’s Cyclone II generation. In order to address the power supply requirements of the CY7C68013 USB chip (3.3 V), the FPGA core (1.2 V), and the AD7671 and front-end preprocessing circuit (5 V), AMS1117 voltage regulator chips are designed for stable 5 V–1.2 V and 5 V–3.3 V power supplies. In the experiments, wavelength calibration and spectral preprocessing are performed on the system prior to data processing. Near-infrared reflectance spectra of different skin conditions (melanoma, vitiligo) are compared with normal skin. The results demonstrate the accurate assessment capability of the designed infrared optoelectronic skin detection system. Facial skin data obtained from the system are used to generate facial images, and the recognition performance of different detection systems is compared in an algorithmic environment, thereby demonstrating the promising application prospects of the infrared optoelectronic skin detection system in the field of facial recognition.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of Charge Couple Device (CCD) technology is particularly rapid in the fields of image sensors and non-contact measurement. In this study, a data acquisition device applied to CCD photoelectric detection system is designed. Among them, the design of the Differential Amplification (DA) module, Analog-to-Digital Converter (ADC) module, First In First Out (FIFO) cache module, and Complex Programmable Logic Device (CPLD) module in this device are emphasized. The ADC circuit in the ADC module converts two 4 MHz analog photoelectric signals generated by the CCD sensor at a frequency of 8 MHz, and then outputs 12-bit digital signals. The collected photoelectric signal is used to detect the damage to the surface of ancient buildings with the machine vision technology of artificial intelligence (AI). In the test, the DA circuit can adjust the voltage range of two photoelectric analog signals output by CCD to a predetermined range (1.5 V∼2.0 V). In the ADC circuit test, there is no data in the FIFO when there is no input conversion, and the converted data will be stored in the internal FIFO during the conversion clock period. Based on machine vision technology, surface damage types of ancient buildings are defined, namely spalling, cracks, and disruption, and surface image samples are generated from collected signals. The samples are trained using the convolutional neural network, and the classifier is generated. The test reveals that the designed photoelectric signal acquisition device and AI machine vision technology can accurately classify the surface damage of ancient buildings.
电荷耦合器件(CCD)技术在图像传感器和非接触式测量领域的发展尤为迅速。本课题设计了一种应用于CCD光电检测系统的数据采集装置。其中，着重介绍了该器件中差分放大(DA)模块、模数转换器(ADC)模块、先进先出(FIFO)缓存模块和复杂可编程逻辑器件(CPLD)模块的设计。ADC模块中的ADC电路将CCD传感器产生的2个频率为8mhz的4mhz模拟光电信号进行转换，然后输出12位数字信号。利用人工智能的机器视觉技术，将采集到的光电信号用于古建筑表面的损伤检测。在测试中，DA电路可以将CCD输出的两个光电模拟信号的电压范围调整到预定范围(1.5 V ~ 2.0 V)，在ADC电路测试中，当没有输入转换时，FIFO中没有数据，转换后的数据将在转换时钟周期内存储在内部FIFO中。基于机器视觉技术，定义古建筑的表面损伤类型，即剥落、裂缝和破坏，并根据采集到的信号生成表面图像样本。使用卷积神经网络对样本进行训练，生成分类器。试验表明，所设计的光电信号采集装置和人工智能机器视觉技术能够对古建筑表面损伤进行准确分类。
{"title":"Charge Couple Device (CCD) Photoelectric Signal Data Acquisition and Its Application in the Machine Vision of Artificial Intelligence","authors":"Yan Liu, Jianhang Zeng","doi":"10.1166/jno.2023.3450","DOIUrl":"https://doi.org/10.1166/jno.2023.3450","url":null,"abstract":"The development of Charge Couple Device (CCD) technology is particularly rapid in the fields of image sensors and non-contact measurement. In this study, a data acquisition device applied to CCD photoelectric detection system is designed. Among them, the design of the Differential Amplification (DA) module, Analog-to-Digital Converter (ADC) module, First In First Out (FIFO) cache module, and Complex Programmable Logic Device (CPLD) module in this device are emphasized. The ADC circuit in the ADC module converts two 4 MHz analog photoelectric signals generated by the CCD sensor at a frequency of 8 MHz, and then outputs 12-bit digital signals. The collected photoelectric signal is used to detect the damage to the surface of ancient buildings with the machine vision technology of artificial intelligence (AI). In the test, the DA circuit can adjust the voltage range of two photoelectric analog signals output by CCD to a predetermined range (1.5 V∼2.0 V). In the ADC circuit test, there is no data in the FIFO when there is no input conversion, and the converted data will be stored in the internal FIFO during the conversion clock period. Based on machine vision technology, surface damage types of ancient buildings are defined, namely spalling, cracks, and disruption, and surface image samples are generated from collected signals. The samples are trained using the convolutional neural network, and the classifier is generated. The test reveals that the designed photoelectric signal acquisition device and AI machine vision technology can accurately classify the surface damage of ancient buildings.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the deficiency of low utilization ratio of transformer excitation energy, complex circuit structure, low efficiency and low output power in the existing magnetic reset technology, a secondary parallel LCD forward converter which can avoid reverse charging of additional capacitor is proposed. According to the different working modes of inductors in the proposed converter, the converter is divided into different combined working modes, and the working principles of different combined working modes are analyzed in detail. At the same time, the influence of additional LCD circuit on the performance of the proposed converter is deeply studied based on the working principles of different combination modes. According to the performance analysis, the analytical expression of additional capacitance on the working mode is derived, and the optimal design scheme of additional capacitance parameters is put forward. Finally, in order to verify the effect of the additional capacitance C 2 on the operation mode of the converter, an experimental analysis of the secondary parallel LCD forward converter which can avoid the reverse charging of the additional capacitor is carried out. The experimental waveform analysis verifies the correctness of the theoretical analysis and the feasibility of the design method of the additional capacitor parameters.
{"title":"Analysis of Energy Transmission and Design of Additional Capacitance for a Novel Secondary Side Parallel LCD Forward Converter","authors":"Gao-Zhong Zhu, Shu-Lin Liu","doi":"10.1166/jno.2023.3457","DOIUrl":"https://doi.org/10.1166/jno.2023.3457","url":null,"abstract":"For the deficiency of low utilization ratio of transformer excitation energy, complex circuit structure, low efficiency and low output power in the existing magnetic reset technology, a secondary parallel LCD forward converter which can avoid reverse charging of additional capacitor is proposed. According to the different working modes of inductors in the proposed converter, the converter is divided into different combined working modes, and the working principles of different combined working modes are analyzed in detail. At the same time, the influence of additional LCD circuit on the performance of the proposed converter is deeply studied based on the working principles of different combination modes. According to the performance analysis, the analytical expression of additional capacitance on the working mode is derived, and the optimal design scheme of additional capacitance parameters is put forward. Finally, in order to verify the effect of the additional capacitance C 2 on the operation mode of the converter, an experimental analysis of the secondary parallel LCD forward converter which can avoid the reverse charging of the additional capacitor is carried out. The experimental waveform analysis verifies the correctness of the theoretical analysis and the feasibility of the design method of the additional capacitor parameters.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wen-Xiao Chen, Nan Sun, Yue Shen, Xue-Feng Yan, Yan Ma, Mohamed Hashem, Hassan Fouad
This study investigates the thermal insulation performance of SiO 2 aerogel fabric using infrared thermal imaging. Surface temperature and heat distribution were measured utilizing an infrared thermometer. The impact of various factors, including molding process, weight, and layers, on the fabric’s thermal insulation performance was systematically analyzed. The findings reveal that fabric produced through fiber mixing with aerogel powder exhibits superior thermal insulation properties compared to powder impregnation. Moreover, an increase in layers and weight corresponds to a reduction in surface temperature and an expansion in the area with lower temperatures. This effect indicates an enhancement in heat propagation range and an improvement in overall insulation performance.
{"title":"Infrared Thermal Imaging Analysis of Thermal Insulation Performance in SiO<sub>2</sub> Aerogel Fabric","authors":"Wen-Xiao Chen, Nan Sun, Yue Shen, Xue-Feng Yan, Yan Ma, Mohamed Hashem, Hassan Fouad","doi":"10.1166/jno.2023.3453","DOIUrl":"https://doi.org/10.1166/jno.2023.3453","url":null,"abstract":"This study investigates the thermal insulation performance of SiO 2 aerogel fabric using infrared thermal imaging. Surface temperature and heat distribution were measured utilizing an infrared thermometer. The impact of various factors, including molding process, weight, and layers, on the fabric’s thermal insulation performance was systematically analyzed. The findings reveal that fabric produced through fiber mixing with aerogel powder exhibits superior thermal insulation properties compared to powder impregnation. Moreover, an increase in layers and weight corresponds to a reduction in surface temperature and an expansion in the area with lower temperatures. This effect indicates an enhancement in heat propagation range and an improvement in overall insulation performance.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Feng, Hai-Chuan Wang, Kun-Fang Li, Yu-Dong Li, Lin Wen, Qi Guo
The industrial operation of nuclear power plant under the strong radiation environment requires the detection of environmental visual information by the camera mounted on the nuclear robot. CMOS Image Sensor, as the core component of camera, will be affected by γ -ray radiation when working in nuclear radiation environment, which will degrade photoelectric sensitive parameters and bring in visual noise, embodied in a decrease of signal-to-noise ratio of the camera. This study carried out the experiments of CMOS Image Sensor and camera system under γ -ray irradiation, analyzed the degradation mechanism of dark current and quantum efficiency of CMOS image sensor under γ -ray radiation, and analysis their impact mechanism on signal-to-noise ratio of the camera. A quantitative evaluation formula was established to evaluate the impact of dark current and quantum efficiency of the CMOS image sensor on signal-to-noise ratio of camera in γ -ray radiation environment. This study provides the theoretical basis for the evaluation of the anti-radiation camera operating under strong nuclear radiation environment and contributes to the future development of nuclear industry.
{"title":"Impact of <i>γ</i> Irradiation Damage to CMOS Image Sensor on Camera Signal-To-Noise Ratio","authors":"Jie Feng, Hai-Chuan Wang, Kun-Fang Li, Yu-Dong Li, Lin Wen, Qi Guo","doi":"10.1166/jno.2023.3459","DOIUrl":"https://doi.org/10.1166/jno.2023.3459","url":null,"abstract":"The industrial operation of nuclear power plant under the strong radiation environment requires the detection of environmental visual information by the camera mounted on the nuclear robot. CMOS Image Sensor, as the core component of camera, will be affected by γ -ray radiation when working in nuclear radiation environment, which will degrade photoelectric sensitive parameters and bring in visual noise, embodied in a decrease of signal-to-noise ratio of the camera. This study carried out the experiments of CMOS Image Sensor and camera system under γ -ray irradiation, analyzed the degradation mechanism of dark current and quantum efficiency of CMOS image sensor under γ -ray radiation, and analysis their impact mechanism on signal-to-noise ratio of the camera. A quantitative evaluation formula was established to evaluate the impact of dark current and quantum efficiency of the CMOS image sensor on signal-to-noise ratio of camera in γ -ray radiation environment. This study provides the theoretical basis for the evaluation of the anti-radiation camera operating under strong nuclear radiation environment and contributes to the future development of nuclear industry.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"129 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ever-increasing complexity and prohibitive fabrication costs associated with VLSI circuits necessitate the development of techniques that prioritize low power consumption and high-speed analog blocks. In today’s era of smart IoT devices, which are pervasive and heavily reliant on efficient battery backups, the demand for low power architectures is paramount to preserve battery life and reduce weight. Simultaneously, maintaining high-speed performance and incorporating additional features is crucial in the wireless industry. Amplifiers, being fundamental front-ends in transceiver design, significantly impact the overall performance of transceivers. Consequently, this study aims to provide a comprehensive and systematic review of amplifier techniques, with a specific focus on low-power and high-speed approaches, following the Preferred Reporting Items for Systematic Review and Meta-Analysis (PRISMA) methodology. The findings presented herein identify the current state of research in the defined area and highlight potential avenues for future exploration.
{"title":"Meta Analytic Review on Recent Advancements of Class AB Power Amplifiers","authors":"Shikha Soni, Vandana Niranjan, Ashwni Kumar","doi":"10.1166/jno.2023.3452","DOIUrl":"https://doi.org/10.1166/jno.2023.3452","url":null,"abstract":"The ever-increasing complexity and prohibitive fabrication costs associated with VLSI circuits necessitate the development of techniques that prioritize low power consumption and high-speed analog blocks. In today’s era of smart IoT devices, which are pervasive and heavily reliant on efficient battery backups, the demand for low power architectures is paramount to preserve battery life and reduce weight. Simultaneously, maintaining high-speed performance and incorporating additional features is crucial in the wireless industry. Amplifiers, being fundamental front-ends in transceiver design, significantly impact the overall performance of transceivers. Consequently, this study aims to provide a comprehensive and systematic review of amplifier techniques, with a specific focus on low-power and high-speed approaches, following the Preferred Reporting Items for Systematic Review and Meta-Analysis (PRISMA) methodology. The findings presented herein identify the current state of research in the defined area and highlight potential avenues for future exploration.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"129 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The integration of on-chip temperature sensors within various systems, industrial Internet of Things (IoT), and wireless sensor networks is greatly facilitated by their small size, cost-effectiveness, and capability to provide direct digital output. However, the diverse application scenarios pose challenges in designing these sensors. On one hand, real-time clock calibration demands high-precision temperature sensors, while on-chip heat management emphasizes compactness and low-voltage operation. Additionally, streamlining the calibration cost for mass production holds significant practical value. Addressing these challenges, this study systematically investigates on-chip complementary metal-oxide-semiconductor (CMOS) temperature sensors based on distinct signal domains processed by temperature readout circuits. Specifically, the research commences by analyzing the issues of several degeneracy points in the front-end circuit of a bipolar junction transistor (BJT) temperature sensor with current gain compensation technology. To address the intricate design challenges in advanced technologies and calibration complexities in industrial applications, dynamic component matching, current gain compensation, and chopper stabilization are harnessed. A novel dynamic current gain canceling technique for temperature readout is introduced, enhancing temperature measurement accuracy without incurring additional power consumption or area overhead. Ultimately, an all-digital CMOS temperature sensor is realized using the SMIC 55 nm CMOS process. Occupying a mere 0.29 mm2 of core area, the design operates efficiently across a wide supply voltage range of 1.2 V to 3.6 V. Covering a temperature spectrum from −40 °C to 125 °C, the sensor demonstrates a calibration error of just ±0.7 °C. This achievement is attributed to the incorporation of the proposed dynamic current gain compensation technique.
{"title":"Design of High Precision Temperature Sensor with Current Gain Compensation Technology for On-Chip Application","authors":"Le Luo","doi":"10.1166/jno.2023.3454","DOIUrl":"https://doi.org/10.1166/jno.2023.3454","url":null,"abstract":"The integration of on-chip temperature sensors within various systems, industrial Internet of Things (IoT), and wireless sensor networks is greatly facilitated by their small size, cost-effectiveness, and capability to provide direct digital output. However, the diverse application scenarios pose challenges in designing these sensors. On one hand, real-time clock calibration demands high-precision temperature sensors, while on-chip heat management emphasizes compactness and low-voltage operation. Additionally, streamlining the calibration cost for mass production holds significant practical value. Addressing these challenges, this study systematically investigates on-chip complementary metal-oxide-semiconductor (CMOS) temperature sensors based on distinct signal domains processed by temperature readout circuits. Specifically, the research commences by analyzing the issues of several degeneracy points in the front-end circuit of a bipolar junction transistor (BJT) temperature sensor with current gain compensation technology. To address the intricate design challenges in advanced technologies and calibration complexities in industrial applications, dynamic component matching, current gain compensation, and chopper stabilization are harnessed. A novel dynamic current gain canceling technique for temperature readout is introduced, enhancing temperature measurement accuracy without incurring additional power consumption or area overhead. Ultimately, an all-digital CMOS temperature sensor is realized using the SMIC 55 nm CMOS process. Occupying a mere 0.29 mm2 of core area, the design operates efficiently across a wide supply voltage range of 1.2 V to 3.6 V. Covering a temperature spectrum from −40 °C to 125 °C, the sensor demonstrates a calibration error of just ±0.7 °C. This achievement is attributed to the incorporation of the proposed dynamic current gain compensation technique.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135856476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, LED with high brightness or ultra-high brightness has appeared. Because of its low production cost, it has been widely used. Compared with other display media, LED has the advantages of rich display content, wide dynamic range, vivid picture, no pollution, long life, etc., so it is used in building curtain wall facade decoration. This research designs LED curtain wall control system, the use of SD600 chip dimming control of LED, the use of absorbing current mode LED drive, further design of single SD600 chip application circuit, multi-SD600 chip application circuit. LED curtain wall display text need to design the corresponding graphic processing hardware, the hardware is composed of ARM microprocessor LPC2210 and its related peripheral circuits. The core chip of the LPC2210 processor chip needs 1.8 V working voltage, and the I/O interface voltage is 3.3 V, so it is necessary to design the corresponding power circuit; The system clock is adjusted through the internal PLL circuit to make the system run faster and design its crystal oscillator circuit; The power monitoring chip CAT1025JI-30 is adopted to build reset circuit, 20-pin interface type JTAG interface circuit; It is considered that the UARTO interface can’t be directly connected with the RS232 interface of PC, the MAX3232 chip is introduced for level conversion, and the serial interface circuit based on LPC2210 is designed. In the experiment, the new technology is used for outdoor lighting LED curtain wall construction, and the development tool uses the ADS1.2 provided by ARM company. The μ C/OS-II embedded operating system is introduced to control the graphic processing hardware resources, reading the file from the SD card, and writing the text file and BMP file into the three-dimensional array, the corresponding text and pattern effect are displayed in the LED curtain wall.
{"title":"Design of New LED Curtain Wall Controller and Its Effect in Architectural Decoration","authors":"Rongrong Cui","doi":"10.1166/jno.2023.3446","DOIUrl":"https://doi.org/10.1166/jno.2023.3446","url":null,"abstract":"In recent years, LED with high brightness or ultra-high brightness has appeared. Because of its low production cost, it has been widely used. Compared with other display media, LED has the advantages of rich display content, wide dynamic range, vivid picture, no pollution, long life, etc., so it is used in building curtain wall facade decoration. This research designs LED curtain wall control system, the use of SD600 chip dimming control of LED, the use of absorbing current mode LED drive, further design of single SD600 chip application circuit, multi-SD600 chip application circuit. LED curtain wall display text need to design the corresponding graphic processing hardware, the hardware is composed of ARM microprocessor LPC2210 and its related peripheral circuits. The core chip of the LPC2210 processor chip needs 1.8 V working voltage, and the I/O interface voltage is 3.3 V, so it is necessary to design the corresponding power circuit; The system clock is adjusted through the internal PLL circuit to make the system run faster and design its crystal oscillator circuit; The power monitoring chip CAT1025JI-30 is adopted to build reset circuit, 20-pin interface type JTAG interface circuit; It is considered that the UARTO interface can’t be directly connected with the RS232 interface of PC, the MAX3232 chip is introduced for level conversion, and the serial interface circuit based on LPC2210 is designed. In the experiment, the new technology is used for outdoor lighting LED curtain wall construction, and the development tool uses the ADS1.2 provided by ARM company. The μ C/OS-II embedded operating system is introduced to control the graphic processing hardware resources, reading the file from the SD card, and writing the text file and BMP file into the three-dimensional array, the corresponding text and pattern effect are displayed in the LED curtain wall.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135142791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new discrete-time sliding mode predictive control (DSMPC) strategy with a PID sliding function is proposed for synchronous DC–DC Buck converter. The model predictive control, along with digital sliding mode control (DSMC) is able to further reducing the chattering phenomenon, steady-state error, overshoot, and undershoot of the converter output voltage. The proposed control method implementation only requires output error voltage evaluation. The effectiveness of the proposed DSMPC is proved through simulation results executed by the MATLAB/SIMULINK software. These results demonstrate its performance is superior to DSMC. The selected synchronous Buck converter in this paper has 380 V input voltage and 48 V output voltage that can be applied in sections of DC distribution systems.
{"title":"Design of Sliding Mode Controller Based on 7 nm Gate Logic","authors":"Li Yan, Liang Wenbin, Liao Jie, Yu Xian","doi":"10.1166/jno.2023.3440","DOIUrl":"https://doi.org/10.1166/jno.2023.3440","url":null,"abstract":"In this paper, a new discrete-time sliding mode predictive control (DSMPC) strategy with a PID sliding function is proposed for synchronous DC–DC Buck converter. The model predictive control, along with digital sliding mode control (DSMC) is able to further reducing the chattering phenomenon, steady-state error, overshoot, and undershoot of the converter output voltage. The proposed control method implementation only requires output error voltage evaluation. The effectiveness of the proposed DSMPC is proved through simulation results executed by the MATLAB/SIMULINK software. These results demonstrate its performance is superior to DSMC. The selected synchronous Buck converter in this paper has 380 V input voltage and 48 V output voltage that can be applied in sections of DC distribution systems.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135143052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A track static misalignment prediction model based on track median deviation is created using an IGA-BP neural network in order to precisely predict the trend of ballastless track static misalignment. The historical static track median deviation detection data are matched using actual compensation edit distance (ERP) to finish the correspondence processing of the original data. The precisely matched data are used to train the model, forecast irregularities in the track median, and compare results with other traditional prediction techniques. The outcomes demonstrate that the IGA-BP neural network can more accurately predict the nonlinear time series data development trend. In comparison to other prediction models, the IGA-BP neural network model’s average relative error and root mean square error are 0.091 and 0.110, respectively. The prediction accuracy is raised by between 43% and 60%, demonstrating the IGA-BP neural network model’s efficacy in predicting static upsets on ballastless tracks and presenting a workable strategy for track predictive maintenance.
{"title":"Track Unevenness Prediction Based on Static Track Inspection Data Matching","authors":"Jianpu Xi, Changle Zhou, Xuetao Qiao, Zhuolin Zhou, Laihua Luo, Qing Yang, Zexiang Zhao","doi":"10.1166/jno.2023.3439","DOIUrl":"https://doi.org/10.1166/jno.2023.3439","url":null,"abstract":"A track static misalignment prediction model based on track median deviation is created using an IGA-BP neural network in order to precisely predict the trend of ballastless track static misalignment. The historical static track median deviation detection data are matched using actual compensation edit distance (ERP) to finish the correspondence processing of the original data. The precisely matched data are used to train the model, forecast irregularities in the track median, and compare results with other traditional prediction techniques. The outcomes demonstrate that the IGA-BP neural network can more accurately predict the nonlinear time series data development trend. In comparison to other prediction models, the IGA-BP neural network model’s average relative error and root mean square error are 0.091 and 0.110, respectively. The prediction accuracy is raised by between 43% and 60%, demonstrating the IGA-BP neural network model’s efficacy in predicting static upsets on ballastless tracks and presenting a workable strategy for track predictive maintenance.","PeriodicalId":16446,"journal":{"name":"Journal of Nanoelectronics and Optoelectronics","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135143054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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