Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967604
L. Shan, M. Meghelli, Joong-Ho Kim, J. Trewhella, M. Taubenblatt, M. Oprysko
A 40 Gb/s package design is introduced in this work. The package includes high-speed coaxial connectors, transmission lines on ceramic substrate, and ribbon bonds. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the package. Both small signal measurements and operational tests were performed to verify the design and modeling concepts. The package was operated up to 50 Gb/s with low degradation to input digital waveforms.
{"title":"Millimeter wave package design: a comparison of simulation and measurement results","authors":"L. Shan, M. Meghelli, Joong-Ho Kim, J. Trewhella, M. Taubenblatt, M. Oprysko","doi":"10.1109/EPEP.2001.967604","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967604","url":null,"abstract":"A 40 Gb/s package design is introduced in this work. The package includes high-speed coaxial connectors, transmission lines on ceramic substrate, and ribbon bonds. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the package. Both small signal measurements and operational tests were performed to verify the design and modeling concepts. The package was operated up to 50 Gb/s with low degradation to input digital waveforms.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"12 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967646
Y. Mabuchi, M. Suwa, H. Fukumoto, A. Nakamura
Simultaneous switching noise (SSN) on bus lines is calculated by accurately modeling printed circuit boards and LSI packages using coupled circuit and electromagnetic simulation. Contribution of crosstalk and ground bounce to SSN is qualitatively estimated. With relatively low inductance package such as BGA, the main cause of SSN is cross talk which results in increasing SSN voltage along the length of bus line. The results of simulation are compared with those of experiment, the both results agree within 10% difference at maximum peak of SSN.
{"title":"Simultaneous switching noise analysis on bus lines using coupled circuit and electromagnetic simulation","authors":"Y. Mabuchi, M. Suwa, H. Fukumoto, A. Nakamura","doi":"10.1109/EPEP.2001.967646","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967646","url":null,"abstract":"Simultaneous switching noise (SSN) on bus lines is calculated by accurately modeling printed circuit boards and LSI packages using coupled circuit and electromagnetic simulation. Contribution of crosstalk and ground bounce to SSN is qualitatively estimated. With relatively low inductance package such as BGA, the main cause of SSN is cross talk which results in increasing SSN voltage along the length of bus line. The results of simulation are compared with those of experiment, the both results agree within 10% difference at maximum peak of SSN.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115494182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967677
R. Ito, R. Carrillo-Ramirez, R. Jackson
In this paper, we present a modeling technique for finding a lumped element model of a via interconnection that can be used in conjunction with a coarse grid two-dimensional transmission line matrix method (2D-TLM) analysis. The technique allows the use of very simple 2D TLM analysis to simultaneously compute insertion loss, return loss, and isolation of multiple via transitions through a power-ground plane pair in a multilayer package. The accuracy of this technique is validated by comparison to HFSS.
{"title":"RF modeling of vertical interconnection between power-ground plane combined with 2D TLM","authors":"R. Ito, R. Carrillo-Ramirez, R. Jackson","doi":"10.1109/EPEP.2001.967677","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967677","url":null,"abstract":"In this paper, we present a modeling technique for finding a lumped element model of a via interconnection that can be used in conjunction with a coarse grid two-dimensional transmission line matrix method (2D-TLM) analysis. The technique allows the use of very simple 2D TLM analysis to simultaneously compute insertion loss, return loss, and isolation of multiple via transitions through a power-ground plane pair in a multilayer package. The accuracy of this technique is validated by comparison to HFSS.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115658114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967615
H. Kubota, A. Kamo, T. Watanabe, H. Asai
With the progress of integration of circuits and PCBs (printed circuit boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain interconnects with nonlinear terminations. This simulator is based on the ASSIST environmental tool constructed for development of the circuit simulators, and is combined with PRIMA (passive reduced-order interconnect macromodeling algorithm). In this simulator, an efficient implementation of PRIMA is considered with use of a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of simple PCBs, and the validity is verified.
{"title":"Analysis of power/ground planes by PCB simulator with model order reduction technique","authors":"H. Kubota, A. Kamo, T. Watanabe, H. Asai","doi":"10.1109/EPEP.2001.967615","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967615","url":null,"abstract":"With the progress of integration of circuits and PCBs (printed circuit boards), novel techniques have been required for verification of signal integrity. Noise analysis of the power/ground planes is one of the most important issues. This paper describes a high-speed simulator for PCBs which contain interconnects with nonlinear terminations. This simulator is based on the ASSIST environmental tool constructed for development of the circuit simulators, and is combined with PRIMA (passive reduced-order interconnect macromodeling algorithm). In this simulator, an efficient implementation of PRIMA is considered with use of a voltage-controlled current source (VCCS) model. Finally, this simulator is applied to the analysis of power/ground planes of simple PCBs, and the validity is verified.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"39 2-3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967670
J. Andrews, S. Kabir
This paper proposes a procedure for extracting package models from multi-port S-parameters. By utilizing all the elements in an n/spl times/n S-parameter matrix, the proposed deterministic procedure provides a better starting point for S-parameter optimization when compared with underdetermined extraction procedures based on multiple 2-port S-matrices using EIA/JEDEC Standard 123. An efficient procedure is discussed for generating a ladder model consisting of an arbitrary number of identical sections.
{"title":"Package model extraction from multi-port S-parameters","authors":"J. Andrews, S. Kabir","doi":"10.1109/EPEP.2001.967670","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967670","url":null,"abstract":"This paper proposes a procedure for extracting package models from multi-port S-parameters. By utilizing all the elements in an n/spl times/n S-parameter matrix, the proposed deterministic procedure provides a better starting point for S-parameter optimization when compared with underdetermined extraction procedures based on multiple 2-port S-matrices using EIA/JEDEC Standard 123. An efficient procedure is discussed for generating a ladder model consisting of an arbitrary number of identical sections.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967611
T. Zeeff, T. Hubing
Power bus structures in printed circuit boards with solid power and ground planes exhibit resonances. When the power bus is resonant, the power bus impedance can increase dramatically. This paper explores the effect of component equivalent series resistance (ESR) on power bus resonances. General guidelines for selecting an optimum ESR are provided and are supported by laboratory measurements and numerical simulations.
{"title":"Reducing power bus impedance at resonance with lossy components","authors":"T. Zeeff, T. Hubing","doi":"10.1109/EPEP.2001.967611","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967611","url":null,"abstract":"Power bus structures in printed circuit boards with solid power and ground planes exhibit resonances. When the power bus is resonant, the power bus impedance can increase dramatically. This paper explores the effect of component equivalent series resistance (ESR) on power bus resonances. General guidelines for selecting an optimum ESR are provided and are supported by laboratory measurements and numerical simulations.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126340391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967609
Zhaoqing Chen, A. Ruehli
This paper describes a time-domain scattering method using triangle impulse response for modeling electronic packaging components such as connectors and vias. The method provides a direct data interface for linear component models to time-domain EM/circuit simulation tools.
{"title":"Time-domain scattering method using triangle impulse responses for modeling electronic packaging components","authors":"Zhaoqing Chen, A. Ruehli","doi":"10.1109/EPEP.2001.967609","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967609","url":null,"abstract":"This paper describes a time-domain scattering method using triangle impulse response for modeling electronic packaging components such as connectors and vias. The method provides a direct data interface for linear component models to time-domain EM/circuit simulation tools.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130391632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967600
P. Marino, A. Street
We are amidst the perfect storm for wireless portable systems that are powered by embedded DSP technology. Better known as the electronic industry third wave, wireless personal systems - such as cell phones, PDAs, internet appliances, 2-way pagers, and GPS systems, are demanding more technology and software performance, while requiring minimal system power consumption. High-performance low-power DSP core architectures are the key enablers driving the consumer experiences with wireless devices. This discussion will focus on how the development of Motorola DSP platforms and process technology advancements are enabling competitive low power system solutions, through architecture design, memory advancement, and signal processing techniques. As a result, OEMs are designing cool and affordable wireless products, that allow consumers to experience connectivity anywhere anytime with longer system battery life.
{"title":"Digital signal processors (DSPs) for low power consumption wireless applications","authors":"P. Marino, A. Street","doi":"10.1109/EPEP.2001.967600","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967600","url":null,"abstract":"We are amidst the perfect storm for wireless portable systems that are powered by embedded DSP technology. Better known as the electronic industry third wave, wireless personal systems - such as cell phones, PDAs, internet appliances, 2-way pagers, and GPS systems, are demanding more technology and software performance, while requiring minimal system power consumption. High-performance low-power DSP core architectures are the key enablers driving the consumer experiences with wireless devices. This discussion will focus on how the development of Motorola DSP platforms and process technology advancements are enabling competitive low power system solutions, through architecture design, memory advancement, and signal processing techniques. As a result, OEMs are designing cool and affordable wireless products, that allow consumers to experience connectivity anywhere anytime with longer system battery life.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133719043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967664
M. Tsuk, R. Dame, D. Dvorscak, C. Houghton, J. Laurent
The latest generation Alpha microprocessor, the 21364, uses a ceramic LGA package with mesh power and ground planes. Electromagnetic modeling and measurements were used to verify the validity of the design of the package, and to suggest improvements to the layout to minimize crosstalk.
{"title":"Modeling and measurement of the Alpha 21364 package","authors":"M. Tsuk, R. Dame, D. Dvorscak, C. Houghton, J. Laurent","doi":"10.1109/EPEP.2001.967664","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967664","url":null,"abstract":"The latest generation Alpha microprocessor, the 21364, uses a ceramic LGA package with mesh power and ground planes. Electromagnetic modeling and measurements were used to verify the validity of the design of the package, and to suggest improvements to the layout to minimize crosstalk.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126959246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967599
A. Correale
Technology continues to shrink lithographic images producing smaller chips which require lower voltages. The lower voltage has helped the overall power dissipation per device, but the number of devices that can be integrated has increased by a faster rate. The result is often power-constrained designs. To help alleviate the explosion in power, designers have been faced with many design challenges. Clock power management is now the norm with multiple operation modes. On-board dynamic frequency adjustment and temperature detectors are now employed to ensure that the product does not exceed its maximum thermal limits. Another aspect of power management is the use of multiple voltages. The author discusses power management from a packaging perspective and concludes that power efficiency has become a mandate for success.
{"title":"\"Watts\" the matter: power reduction issues","authors":"A. Correale","doi":"10.1109/EPEP.2001.967599","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967599","url":null,"abstract":"Technology continues to shrink lithographic images producing smaller chips which require lower voltages. The lower voltage has helped the overall power dissipation per device, but the number of devices that can be integrated has increased by a faster rate. The result is often power-constrained designs. To help alleviate the explosion in power, designers have been faced with many design challenges. Clock power management is now the norm with multiple operation modes. On-board dynamic frequency adjustment and temperature detectors are now employed to ensure that the product does not exceed its maximum thermal limits. Another aspect of power management is the use of multiple voltages. The author discusses power management from a packaging perspective and concludes that power efficiency has become a mandate for success.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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